Lines Matching refs:bridge
156 struct mvebu_sw_pci_bridge bridge; member
420 if (port->bridge.iolimit < port->bridge.iobase || in mvebu_pcie_handle_iobase_change()
421 port->bridge.iolimitupper < port->bridge.iobaseupper || in mvebu_pcie_handle_iobase_change()
422 !(port->bridge.command & PCI_COMMAND_IO)) { in mvebu_pcie_handle_iobase_change()
441 desired.remap = ((port->bridge.iobase & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
442 (port->bridge.iobaseupper << 16); in mvebu_pcie_handle_iobase_change()
444 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
445 (port->bridge.iolimitupper << 16)) - in mvebu_pcie_handle_iobase_change()
458 if (port->bridge.memlimit < port->bridge.membase || in mvebu_pcie_handle_membase_change()
459 !(port->bridge.command & PCI_COMMAND_MEMORY)) { in mvebu_pcie_handle_membase_change()
471 desired.base = ((port->bridge.membase & 0xFFF0) << 16); in mvebu_pcie_handle_membase_change()
472 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - in mvebu_pcie_handle_membase_change()
485 struct mvebu_sw_pci_bridge *bridge = &port->bridge; in mvebu_sw_pci_bridge_init() local
487 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); in mvebu_sw_pci_bridge_init()
489 bridge->class = PCI_CLASS_BRIDGE_PCI; in mvebu_sw_pci_bridge_init()
490 bridge->vendor = PCI_VENDOR_ID_MARVELL; in mvebu_sw_pci_bridge_init()
491 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; in mvebu_sw_pci_bridge_init()
492 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; in mvebu_sw_pci_bridge_init()
493 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; in mvebu_sw_pci_bridge_init()
494 bridge->cache_line_size = 0x10; in mvebu_sw_pci_bridge_init()
497 bridge->iobase = PCI_IO_RANGE_TYPE_32; in mvebu_sw_pci_bridge_init()
498 bridge->iolimit = PCI_IO_RANGE_TYPE_32; in mvebu_sw_pci_bridge_init()
501 bridge->status = PCI_STATUS_CAP_LIST; in mvebu_sw_pci_bridge_init()
511 struct mvebu_sw_pci_bridge *bridge = &port->bridge; in mvebu_sw_pci_bridge_read() local
515 *value = bridge->device << 16 | bridge->vendor; in mvebu_sw_pci_bridge_read()
519 *value = bridge->command | bridge->status << 16; in mvebu_sw_pci_bridge_read()
523 *value = bridge->class << 16 | bridge->interface << 8 | in mvebu_sw_pci_bridge_read()
524 bridge->revision; in mvebu_sw_pci_bridge_read()
528 *value = bridge->bist << 24 | bridge->header_type << 16 | in mvebu_sw_pci_bridge_read()
529 bridge->latency_timer << 8 | bridge->cache_line_size; in mvebu_sw_pci_bridge_read()
533 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; in mvebu_sw_pci_bridge_read()
537 *value = (bridge->secondary_latency_timer << 24 | in mvebu_sw_pci_bridge_read()
538 bridge->subordinate_bus << 16 | in mvebu_sw_pci_bridge_read()
539 bridge->secondary_bus << 8 | in mvebu_sw_pci_bridge_read()
540 bridge->primary_bus); in mvebu_sw_pci_bridge_read()
545 *value = bridge->secondary_status << 16; in mvebu_sw_pci_bridge_read()
547 *value = (bridge->secondary_status << 16 | in mvebu_sw_pci_bridge_read()
548 bridge->iolimit << 8 | in mvebu_sw_pci_bridge_read()
549 bridge->iobase); in mvebu_sw_pci_bridge_read()
553 *value = (bridge->memlimit << 16 | bridge->membase); in mvebu_sw_pci_bridge_read()
561 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); in mvebu_sw_pci_bridge_read()
591 *value |= bridge->pcie_devctl; in mvebu_sw_pci_bridge_read()
608 *value = bridge->pcie_sltcap; in mvebu_sw_pci_bridge_read()
616 *value = bridge->pcie_rtctl; in mvebu_sw_pci_bridge_read()
652 struct mvebu_sw_pci_bridge *bridge = &port->bridge; in mvebu_sw_pci_bridge_write() local
674 u32 old = bridge->command; in mvebu_sw_pci_bridge_write()
679 bridge->command = value & 0xffff; in mvebu_sw_pci_bridge_write()
680 if ((old ^ bridge->command) & PCI_COMMAND_IO) in mvebu_sw_pci_bridge_write()
682 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) in mvebu_sw_pci_bridge_write()
688 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; in mvebu_sw_pci_bridge_write()
697 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; in mvebu_sw_pci_bridge_write()
698 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; in mvebu_sw_pci_bridge_write()
703 bridge->membase = value & 0xffff; in mvebu_sw_pci_bridge_write()
704 bridge->memlimit = value >> 16; in mvebu_sw_pci_bridge_write()
709 bridge->iobaseupper = value & 0xffff; in mvebu_sw_pci_bridge_write()
710 bridge->iolimitupper = value >> 16; in mvebu_sw_pci_bridge_write()
715 bridge->primary_bus = value & 0xff; in mvebu_sw_pci_bridge_write()
716 bridge->secondary_bus = (value >> 8) & 0xff; in mvebu_sw_pci_bridge_write()
717 bridge->subordinate_bus = (value >> 16) & 0xff; in mvebu_sw_pci_bridge_write()
718 bridge->secondary_latency_timer = (value >> 24) & 0xff; in mvebu_sw_pci_bridge_write()
719 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); in mvebu_sw_pci_bridge_write()
791 bus->number >= port->bridge.secondary_bus && in mvebu_pcie_find_port()
792 bus->number <= port->bridge.subordinate_bus) in mvebu_pcie_find_port()