Lines Matching refs:bridge
527 struct pci_dev *bridge = bus->self; in pci_setup_cardbus() local
531 dev_info(&bridge->dev, "CardBus bridge to %pR\n", in pci_setup_cardbus()
535 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_cardbus()
541 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_cardbus()
542 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, in pci_setup_cardbus()
544 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, in pci_setup_cardbus()
549 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_cardbus()
551 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_cardbus()
552 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, in pci_setup_cardbus()
554 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, in pci_setup_cardbus()
559 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_cardbus()
561 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_cardbus()
562 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, in pci_setup_cardbus()
564 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, in pci_setup_cardbus()
569 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_cardbus()
571 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_cardbus()
572 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, in pci_setup_cardbus()
574 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, in pci_setup_cardbus()
591 static void pci_setup_bridge_io(struct pci_dev *bridge) in pci_setup_bridge_io() argument
601 if (bridge->io_window_1k) in pci_setup_bridge_io()
605 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; in pci_setup_bridge_io()
606 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_bridge_io()
608 pci_read_config_word(bridge, PCI_IO_BASE, &l); in pci_setup_bridge_io()
614 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_bridge_io()
621 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); in pci_setup_bridge_io()
623 pci_write_config_word(bridge, PCI_IO_BASE, l); in pci_setup_bridge_io()
625 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); in pci_setup_bridge_io()
628 static void pci_setup_bridge_mmio(struct pci_dev *bridge) in pci_setup_bridge_mmio() argument
635 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; in pci_setup_bridge_mmio()
636 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_bridge_mmio()
640 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_bridge_mmio()
644 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); in pci_setup_bridge_mmio()
647 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) in pci_setup_bridge_mmio_pref() argument
656 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); in pci_setup_bridge_mmio_pref()
660 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; in pci_setup_bridge_mmio_pref()
661 pcibios_resource_to_bus(bridge->bus, ®ion, res); in pci_setup_bridge_mmio_pref()
669 dev_info(&bridge->dev, " bridge window %pR\n", res); in pci_setup_bridge_mmio_pref()
673 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); in pci_setup_bridge_mmio_pref()
676 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); in pci_setup_bridge_mmio_pref()
677 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); in pci_setup_bridge_mmio_pref()
682 struct pci_dev *bridge = bus->self; in __pci_setup_bridge() local
684 dev_info(&bridge->dev, "PCI bridge to %pR\n", in __pci_setup_bridge()
688 pci_setup_bridge_io(bridge); in __pci_setup_bridge()
691 pci_setup_bridge_mmio(bridge); in __pci_setup_bridge()
694 pci_setup_bridge_mmio_pref(bridge); in __pci_setup_bridge()
696 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); in __pci_setup_bridge()
713 int pci_claim_bridge_resource(struct pci_dev *bridge, int i) in pci_claim_bridge_resource() argument
718 if (pci_claim_resource(bridge, i) == 0) in pci_claim_bridge_resource()
721 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) in pci_claim_bridge_resource()
724 if (!pci_bus_clip_resource(bridge, i)) in pci_claim_bridge_resource()
729 pci_setup_bridge_io(bridge); in pci_claim_bridge_resource()
732 pci_setup_bridge_mmio(bridge); in pci_claim_bridge_resource()
735 pci_setup_bridge_mmio_pref(bridge); in pci_claim_bridge_resource()
741 if (pci_claim_resource(bridge, i) == 0) in pci_claim_bridge_resource()
754 struct pci_dev *bridge = bus->self; in pci_bridge_check_ranges() local
757 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; in pci_bridge_check_ranges()
760 pci_read_config_word(bridge, PCI_IO_BASE, &io); in pci_bridge_check_ranges()
762 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); in pci_bridge_check_ranges()
763 pci_read_config_word(bridge, PCI_IO_BASE, &io); in pci_bridge_check_ranges()
764 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); in pci_bridge_check_ranges()
772 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) in pci_bridge_check_ranges()
775 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); in pci_bridge_check_ranges()
777 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, in pci_bridge_check_ranges()
779 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); in pci_bridge_check_ranges()
780 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); in pci_bridge_check_ranges()
794 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, in pci_bridge_check_ranges()
796 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, in pci_bridge_check_ranges()
798 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); in pci_bridge_check_ranges()
801 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, in pci_bridge_check_ranges()
1135 struct pci_dev *bridge = bus->self; in pci_bus_size_cardbus() local
1136 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; in pci_bus_size_cardbus()
1151 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, in pci_bus_size_cardbus()
1163 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, in pci_bus_size_cardbus()
1169 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); in pci_bus_size_cardbus()
1172 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); in pci_bus_size_cardbus()
1173 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); in pci_bus_size_cardbus()
1180 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); in pci_bus_size_cardbus()
1183 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); in pci_bus_size_cardbus()
1184 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); in pci_bus_size_cardbus()
1201 add_to_list(realloc_head, bridge, b_res+2, in pci_bus_size_cardbus()
1217 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, in pci_bus_size_cardbus()
1500 static void __pci_bridge_assign_resources(const struct pci_dev *bridge, in __pci_bridge_assign_resources() argument
1506 pdev_assign_resources_sorted((struct pci_dev *)bridge, in __pci_bridge_assign_resources()
1509 b = bridge->subordinate; in __pci_bridge_assign_resources()
1515 switch (bridge->class >> 8) { in __pci_bridge_assign_resources()
1525 dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", in __pci_bridge_assign_resources()
1860 if (ACPI_HANDLE(root_bus->bridge)) in pci_assign_unassigned_resources()
1861 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); in pci_assign_unassigned_resources()
1865 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) in pci_assign_unassigned_bridge_resources() argument
1867 struct pci_bus *parent = bridge->subordinate; in pci_assign_unassigned_bridge_resources()
1879 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); in pci_assign_unassigned_bridge_resources()
1919 retval = pci_reenable_device(bridge); in pci_assign_unassigned_bridge_resources()
1921 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); in pci_assign_unassigned_bridge_resources()
1922 pci_set_master(bridge); in pci_assign_unassigned_bridge_resources()