Lines Matching refs:BIT
92 # define IRQSTATUS_LATCHED_MSG BIT(0)
93 # define IRQSTATUS_LATCHED_IO BIT(1)
94 # define IRQSTATUS_LATCHED_CD BIT(2)
95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
96 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
99 # define IRQSTATUS_TIMER_IRQ BIT(7)
100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
101 # define IRQSTATUS_PCI_IRQ BIT(9)
102 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
103 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
104 # define PCI_IRQ_MASK BIT(12)
105 # define TIMER_IRQ_MASK BIT(13)
106 # define FIFO_IRQ_MASK BIT(14)
107 # define SCSI_IRQ_MASK BIT(15)
123 # define CB_MMIO_MODE BIT(0)
124 # define CB_IO_MODE BIT(1)
125 # define BM_TEST BIT(2)
126 # define BM_TEST_DIR BIT(3)
127 # define DUAL_EDGE_ENABLE BIT(4)
128 # define NO_TRANSFER_TO_HOST BIT(5)
129 # define TRANSFER_GO BIT(7)
130 # define BLIEND_MODE BIT(8)
131 # define BM_START BIT(9)
132 # define ADVANCED_BM_WRITE BIT(10)
133 # define BM_SINGLE_MODE BIT(11)
134 # define FIFO_TRUE_FULL BIT(12)
135 # define FIFO_TRUE_EMPTY BIT(13)
136 # define ALL_COUNTER_CLR BIT(14)
137 # define FIFOTEST BIT(15)
143 # define TIMER_STOP BIT(8)
150 # define FIFO_EMPTY_SHLD_FLAG BIT(14)
151 # define FIFO_FULL_SHLD_FLAG BIT(15)
154 # define SREQSMPLRATE_RATE0 BIT(0)
155 # define SREQSMPLRATE_RATE1 BIT(1)
156 # define SAMPLING_ENABLE BIT(2)
162 # define BUSCTL_SEL BIT(0)
163 # define BUSCTL_RST BIT(1)
164 # define BUSCTL_DATAOUT_ENB BIT(2)
165 # define BUSCTL_ATN BIT(3)
166 # define BUSCTL_ACK BIT(4)
167 # define BUSCTL_BSY BIT(5)
168 # define AUTODIRECTION BIT(6)
169 # define ACKENB BIT(7)
172 # define ACK_COUNTER_CLR BIT(0)
173 # define SREQ_COUNTER_CLR BIT(1)
174 # define FIFO_HOST_POINTER_CLR BIT(2)
175 # define FIFO_REST_COUNT_CLR BIT(3)
176 # define BM_COUNTER_CLR BIT(4)
177 # define SAVED_ACK_CLR BIT(5)
186 # define BUSMON_MSG BIT(0)
187 # define BUSMON_IO BIT(1)
188 # define BUSMON_CD BIT(2)
189 # define BUSMON_BSY BIT(3)
190 # define BUSMON_ACK BIT(4)
191 # define BUSMON_REQ BIT(5)
192 # define BUSMON_SEL BIT(6)
193 # define BUSMON_ATN BIT(7)
198 # define PARITY_CHECK_ENABLE BIT(0)
199 # define PARITY_ERROR_CLEAR BIT(1)
202 # define PARITY_ERROR_NORMAL BIT(1)
203 # define PARITY_ERROR_LSB BIT(1)
204 # define PARITY_ERROR_MSB BIT(2)
209 # define CLEAR_CDB_FIFO_POINTER BIT(0)
210 # define AUTO_COMMAND_PHASE BIT(1)
211 # define AUTOSCSI_START BIT(2)
212 # define AUTOSCSI_RESTART BIT(3)
213 # define AUTO_PARAMETER BIT(4)
214 # define AUTO_ATN BIT(5)
215 # define AUTO_MSGIN_00_OR_04 BIT(6)
216 # define AUTO_MSGIN_02 BIT(7)
217 # define AUTO_MSGIN_03 BIT(8)
220 # define ARBIT_GO BIT(0)
221 # define ARBIT_CLEAR BIT(1)
225 # define ARBIT_WIN BIT(1)
226 # define ARBIT_FAIL BIT(2)
227 # define AUTO_PARAMETER_VALID BIT(3)
228 # define SGT_VALID BIT(4)
240 # define SCAM_MSG BIT(0)
241 # define SCAM_IO BIT(1)
242 # define SCAM_CD BIT(2)
243 # define SCAM_BSY BIT(3)
244 # define SCAM_SEL BIT(4)
245 # define SCAM_XFEROK BIT(5)
248 # define SD0 BIT(0)
249 # define SD1 BIT(1)
250 # define SD2 BIT(2)
251 # define SD3 BIT(3)
252 # define SD4 BIT(4)
253 # define SD5 BIT(5)
254 # define SD6 BIT(6)
255 # define SD7 BIT(7)
266 # define SGTEND BIT(31) /* Last SGT marker */
272 # define COMMAND_PHASE BIT(0)
273 # define DATA_IN_PHASE BIT(1)
274 # define DATA_OUT_PHASE BIT(2)
275 # define MSGOUT_PHASE BIT(3)
276 # define STATUS_PHASE BIT(4)
277 # define ILLEGAL_PHASE BIT(5)
278 # define BUS_FREE_OCCUER BIT(6)
279 # define MSG_IN_OCCUER BIT(7)
280 # define MSG_OUT_OCCUER BIT(8)
281 # define SELECTION_TIMEOUT BIT(9)
282 # define MSGIN_00_VALID BIT(10)
283 # define MSGIN_02_VALID BIT(11)
284 # define MSGIN_03_VALID BIT(12)
285 # define MSGIN_04_VALID BIT(13)
286 # define AUTOSCSI_BUSY BIT(15)
291 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
292 # define MV_VALID BIT(7)
308 # define CLOCK_2 BIT(0) /* MCLK/2 */
309 # define CLOCK_4 BIT(1) /* MCLK/4 */
310 # define PCICLK BIT(7) /* PCICLK (33MHz) */
313 # define BPWR BIT(0)
314 # define SENSE BIT(1) /* Read Only */
319 # define LED_OFF BIT(0)
322 # define IRQSELECT_RESELECT_IRQ BIT(0)
323 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
324 # define IRQSELECT_SCSIRESET_IRQ BIT(2)
325 # define IRQSELECT_TIMER_IRQ BIT(3)
326 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
327 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
328 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
329 # define IRQSELECT_SERR_IRQ BIT(7)
330 # define IRQSELECT_PERR_IRQ BIT(8)
331 # define IRQSELECT_BMCNTERR_IRQ BIT(9)
332 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
335 # define OLD_MSG BIT(0)
336 # define OLD_IO BIT(1)
337 # define OLD_CD BIT(2)
338 # define OLD_BUSY BIT(3)
344 # define ROM_WRITE_ENB BIT(0)
345 # define IO_ACCESS_ENB BIT(1)
346 # define ROM_ADR_CLEAR BIT(2)
353 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
354 # define OEM1 BIT(2) /* OEM select */
355 # define OPTB BIT(3) /* KME mode select */
356 # define OPTC BIT(4) /* KME mode select */
357 # define OPTD BIT(5) /* KME mode select */
358 # define OPTE BIT(6) /* KME mode select */
359 # define OPTF BIT(7) /* Power management */
363 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
364 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
365 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
366 # define DELAYED_BMSTART BIT(3)
367 # define MASTER_TERMINATION_SELECT BIT(4)
368 # define BMREQ_NEGATE_TIMING_SEL BIT(5)
369 # define AUTOSEL_TIMING_SEL BIT(6)
370 # define MISC_MABORT_MASK BIT(7)
371 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
374 # define BM_CYCLE0 BIT(0)
375 # define BM_CYCLE1 BIT(1)
376 # define BM_FRAME_ASSERT_TIMING BIT(2)
377 # define BM_IRDY_ASSERT_TIMING BIT(3)
378 # define BM_SINGLE_BUS_MASTER BIT(4)
379 # define MEMRD_CMD0 BIT(5)
380 # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
381 # define MEMRD_CMD1 BIT(7)
385 # define SREQ_EDGH_SELECT BIT(0)
388 # define REQCNT_UP BIT(0)
389 # define ACKCNT_UP BIT(1)
390 # define BMADR_UP BIT(4)
391 # define BMCNT_UP BIT(5)
392 # define SGT_CNT_UP BIT(7)
401 # define SCL BIT(0)
402 # define ENA BIT(1)
403 # define SDA BIT(2)
482 #define NSP32_TRANSFER_BUSMASTER BIT(0)
483 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
484 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
493 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
494 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
528 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
529 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
530 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */