Lines Matching refs:TCR
395 #define TCR 0x82 /* tx control */ macro
1408 value = rd_reg16(info, TCR); in set_break()
1413 wr_reg16(info, TCR, value); in set_break()
2292 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2293 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2294 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2877 val = rd_reg16(info, TCR); in set_interface()
2882 wr_reg16(info, TCR, val); in set_interface()
4034 wr_reg16(info, TCR, in tx_start()
4035 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4078 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4079 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4165 wr_reg16(info, TCR, val); in async_mode()
4327 wr_reg16(info, TCR, val); in sync_mode()
4489 tcr = rd_reg16(info, TCR); in tx_set_idle()
4499 wr_reg16(info, TCR, tcr); in tx_set_idle()
4988 wr_reg16(info, TCR, in irq_test()
4989 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()