89 	readl(par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
90 	writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
92 	gcfg = readl(par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
93 	tcfg = readl(par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
97 	writel(tcfg, par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
104 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
108 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
114 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
135 	writel(0, par->dc_regs + DC_FB_ST_OFFSET);  in gx1_set_mode()
138 	writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);  in gx1_set_mode()
140 	       par->dc_regs + DC_BUF_SIZE);  in gx1_set_mode()
166 	writel(val, par->dc_regs + DC_H_TIMING_1);  in gx1_set_mode()
168 	writel(val, par->dc_regs + DC_H_TIMING_2);  in gx1_set_mode()
170 	writel(val, par->dc_regs + DC_H_TIMING_3);  in gx1_set_mode()
171 	writel(val, par->dc_regs + DC_FP_H_TIMING);  in gx1_set_mode()
173 	writel(val, par->dc_regs + DC_V_TIMING_1);  in gx1_set_mode()
175 	writel(val, par->dc_regs + DC_V_TIMING_2);  in gx1_set_mode()
177 	writel(val, par->dc_regs + DC_V_TIMING_3);  in gx1_set_mode()
179 	writel(val, par->dc_regs + DC_FP_V_TIMING);  in gx1_set_mode()
182 	writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);  in gx1_set_mode()
183 	writel(tcfg, par->dc_regs + DC_TIMING_CFG);  in gx1_set_mode()
185 	writel(gcfg, par->dc_regs + DC_GENERAL_CFG);  in gx1_set_mode()
190 	writel(0, par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
207 	writel(regno, par->dc_regs + DC_PAL_ADDRESS);  in gx1_set_hw_palette_reg()
208 	writel(val, par->dc_regs + DC_PAL_DATA);  in gx1_set_hw_palette_reg()