Lines Matching refs:tbl
1344 #define LOAD_FIXED_STATE(tbl,dev) \
1345 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1346 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1347 #define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1348 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1349 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1350 #define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1351 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1352 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1353 #define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1354 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1355 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1356 #define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1357 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1358 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1361 #define LOAD_FIXED_STATE(tbl,dev) \ argument
1362 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1363 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1364 #define LOAD_FIXED_STATE_8BPP(tbl,dev) \ argument
1365 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1366 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1367 #define LOAD_FIXED_STATE_15BPP(tbl,dev) \ argument
1368 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1369 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1370 #define LOAD_FIXED_STATE_16BPP(tbl,dev) \ argument
1371 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1372 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1373 #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ argument
1374 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1375 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])