Lines Matching refs:bridge
59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_DMA_irqhandler() argument
61 wake_up(&bridge->dma_queue); in ca91cx42_DMA_irqhandler()
66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) in ca91cx42_LM_irqhandler() argument
74 bridge->lm_callback[i](bridge->lm_data[i]); in ca91cx42_LM_irqhandler()
83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) in ca91cx42_MB_irqhandler() argument
85 wake_up(&bridge->mbox_queue); in ca91cx42_MB_irqhandler()
90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) in ca91cx42_IACK_irqhandler() argument
92 wake_up(&bridge->iack_queue); in ca91cx42_IACK_irqhandler()
100 struct ca91cx42_driver *bridge; in ca91cx42_VERR_irqhandler() local
102 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VERR_irqhandler()
104 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()
117 struct ca91cx42_driver *bridge; in ca91cx42_LERR_irqhandler() local
119 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_LERR_irqhandler()
121 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()
135 struct ca91cx42_driver *bridge; in ca91cx42_VIRQ_irqhandler() local
137 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_VIRQ_irqhandler()
142 vec = ioread32(bridge->base + in ca91cx42_VIRQ_irqhandler()
158 struct ca91cx42_driver *bridge; in ca91cx42_irqhandler() local
162 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irqhandler()
164 enable = ioread32(bridge->base + LINT_EN); in ca91cx42_irqhandler()
165 stat = ioread32(bridge->base + LINT_STAT); in ca91cx42_irqhandler()
174 serviced |= ca91cx42_DMA_irqhandler(bridge); in ca91cx42_irqhandler()
177 serviced |= ca91cx42_LM_irqhandler(bridge, stat); in ca91cx42_irqhandler()
179 serviced |= ca91cx42_MB_irqhandler(bridge, stat); in ca91cx42_irqhandler()
181 serviced |= ca91cx42_IACK_irqhandler(bridge); in ca91cx42_irqhandler()
193 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
202 struct ca91cx42_driver *bridge; in ca91cx42_irq_init() local
204 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_init()
210 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
213 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
215 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
226 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
227 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
228 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
235 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
240 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, in ca91cx42_irq_exit() argument
246 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
249 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
251 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
253 ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge, in ca91cx42_irq_exit()
258 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level) in ca91cx42_iack_received() argument
262 tmp = ioread32(bridge->base + LINT_STAT); in ca91cx42_iack_received()
279 struct ca91cx42_driver *bridge; in ca91cx42_irq_set() local
281 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_set()
284 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_irq_set()
291 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
304 struct ca91cx42_driver *bridge; in ca91cx42_irq_generate() local
306 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_irq_generate()
312 mutex_lock(&bridge->vme_int); in ca91cx42_irq_generate()
314 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
317 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
321 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
324 wait_event_interruptible(bridge->iack_queue, in ca91cx42_irq_generate()
325 ca91cx42_iack_received(bridge, level)); in ca91cx42_irq_generate()
328 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
330 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
332 mutex_unlock(&bridge->vme_int); in ca91cx42_irq_generate()
345 struct ca91cx42_driver *bridge; in ca91cx42_slave_set() local
349 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slave_set()
408 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
410 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
413 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
414 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
415 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
433 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
438 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
449 struct ca91cx42_driver *bridge; in ca91cx42_slave_get() local
451 bridge = image->parent->driver_priv; in ca91cx42_slave_get()
461 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
463 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_get()
464 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_get()
465 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_get()
604 struct ca91cx42_driver *bridge; in ca91cx42_master_set() local
608 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_master_set()
656 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
658 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
729 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
730 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
731 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
734 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
739 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
758 struct ca91cx42_driver *bridge; in __ca91cx42_master_get() local
760 bridge = image->parent->driver_priv; in __ca91cx42_master_get()
764 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
766 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); in __ca91cx42_master_get()
767 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); in __ca91cx42_master_get()
768 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); in __ca91cx42_master_get()
976 struct ca91cx42_driver *bridge; in ca91cx42_master_rmw() local
979 bridge = image->parent->driver_priv; in ca91cx42_master_rmw()
986 mutex_lock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1001 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1004 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
1005 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
1006 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
1007 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1010 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1016 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1021 mutex_unlock(&bridge->vme_rmw); in ca91cx42_master_rmw()
1175 struct ca91cx42_driver *bridge; in ca91cx42_dma_busy() local
1177 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_dma_busy()
1179 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()
1195 struct ca91cx42_driver *bridge; in ca91cx42_dma_list_exec() local
1199 bridge = ctrlr->parent->driver_priv; in ca91cx42_dma_list_exec()
1225 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1226 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1229 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1238 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1242 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1244 retval = wait_event_interruptible(bridge->dma_queue, in ca91cx42_dma_list_exec()
1248 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1249 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1251 wait_event(bridge->dma_queue, in ca91cx42_dma_list_exec()
1261 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1267 val = ioread32(bridge->base + DCTL); in ca91cx42_dma_list_exec()
1308 struct ca91cx42_driver *bridge; in ca91cx42_lm_set() local
1311 bridge = lm->parent->driver_priv; in ca91cx42_lm_set()
1326 if (bridge->lm_callback[i] != NULL) { in ca91cx42_lm_set()
1360 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1361 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1375 struct ca91cx42_driver *bridge; in ca91cx42_lm_get() local
1377 bridge = lm->parent->driver_priv; in ca91cx42_lm_get()
1381 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); in ca91cx42_lm_get()
1382 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_get()
1418 struct ca91cx42_driver *bridge; in ca91cx42_lm_attach() local
1421 bridge = lm->parent->driver_priv; in ca91cx42_lm_attach()
1427 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_attach()
1435 if (bridge->lm_callback[monitor] != NULL) { in ca91cx42_lm_attach()
1442 bridge->lm_callback[monitor] = callback; in ca91cx42_lm_attach()
1443 bridge->lm_data[monitor] = data; in ca91cx42_lm_attach()
1446 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_attach()
1448 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1453 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1467 struct ca91cx42_driver *bridge; in ca91cx42_lm_detach() local
1469 bridge = lm->parent->driver_priv; in ca91cx42_lm_detach()
1474 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_detach()
1476 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1479 bridge->base + LINT_STAT); in ca91cx42_lm_detach()
1482 bridge->lm_callback[monitor] = NULL; in ca91cx42_lm_detach()
1483 bridge->lm_data[monitor] = NULL; in ca91cx42_lm_detach()
1488 tmp = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_detach()
1490 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1501 struct ca91cx42_driver *bridge; in ca91cx42_slot_get() local
1503 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_slot_get()
1506 slot = ioread32(bridge->base + VCSR_BS); in ca91cx42_slot_get()
1550 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_init() local
1552 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_init()
1558 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1568 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, in ca91cx42_crcsr_init()
1569 &bridge->crcsr_bus); in ca91cx42_crcsr_init()
1570 if (bridge->crcsr_kernel == NULL) { in ca91cx42_crcsr_init()
1577 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1579 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1581 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1590 struct ca91cx42_driver *bridge; in ca91cx42_crcsr_exit() local
1592 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_crcsr_exit()
1595 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1597 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1600 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1602 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, in ca91cx42_crcsr_exit()
1603 bridge->crcsr_bus); in ca91cx42_crcsr_exit()
1877 struct ca91cx42_driver *bridge; in ca91cx42_remove() local
1880 bridge = ca91cx42_bridge->driver_priv; in ca91cx42_remove()
1884 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1887 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1888 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1889 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1890 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1891 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1892 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1893 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1894 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1895 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1896 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1897 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1898 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1899 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1900 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1901 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1902 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()
1937 ca91cx42_irq_exit(bridge, pdev); in ca91cx42_remove()
1939 iounmap(bridge->base); in ca91cx42_remove()