53 	u32 cycle;  member
61 	u32 cycle;  member
160 		dma_addr_t buf_base, u32 aspace, u32 cycle)  in fake_slave_set()  argument
217 	bridge->slaves[i].cycle = cycle;  in fake_slave_set()
229 		dma_addr_t *buf_base, u32 *aspace, u32 *cycle)  in fake_slave_get()  argument
245 	*cycle = bridge->slaves[i].cycle;  in fake_slave_get()
257 		u32 aspace, u32 cycle, u32 dwidth)  in fake_master_set()  argument
325 	bridge->masters[i].cycle = cycle;  in fake_master_set()
344 		u32 *aspace, u32 *cycle, u32 *dwidth)  in __fake_master_get()  argument
357 	*cycle = bridge->masters[i].cycle;  in __fake_master_get()
366 		u32 *aspace, u32 *cycle, u32 *dwidth)  in fake_master_get()  argument
373 			cycle, dwidth);  in fake_master_get()
382 			  u32 aspace, u32 cycle)  in fake_lm_check()  argument
407 		if ((lm_aspace == aspace) && (lm_cycle == cycle)) {  in fake_lm_check()
422 		u32 aspace, u32 cycle)  in fake_vmeread8()  argument
436 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread8()
448 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread8()
454 		u32 aspace, u32 cycle)  in fake_vmeread16()  argument
465 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread16()
480 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread16()
486 		u32 aspace, u32 cycle)  in fake_vmeread32()  argument
497 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread32()
512 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread32()
521 	u32 aspace, cycle, dwidth;  in fake_master_read()  local
537 	cycle = priv->masters[i].cycle;  in fake_master_read()
551 		*(u8 *)buf = fake_vmeread8(priv, addr, aspace, cycle);  in fake_master_read()
560 						addr + done, aspace, cycle);  in fake_master_read()
565 						addr + done, aspace, cycle);  in fake_master_read()
575 					aspace, cycle);  in fake_master_read()
582 					aspace, cycle);  in fake_master_read()
589 					aspace, cycle);  in fake_master_read()
598 					aspace, cycle);  in fake_master_read()
604 				cycle);  in fake_master_read()
617 			   unsigned long long addr, u32 aspace, u32 cycle)  in fake_vmewrite8()  argument
627 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite8()
642 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite8()
647 			    unsigned long long addr, u32 aspace, u32 cycle)  in fake_vmewrite16()  argument
657 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite16()
672 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite16()
677 			    unsigned long long addr, u32 aspace, u32 cycle)  in fake_vmewrite32()  argument
687 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite32()
702 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite32()
710 	u32 aspace, cycle, dwidth;  in fake_master_write()  local
727 	cycle = bridge->masters[i].cycle;  in fake_master_write()
736 		fake_vmewrite8(bridge, (u8 *)buf, addr, aspace, cycle);  in fake_master_write()
746 						addr + done, aspace, cycle);  in fake_master_write()
751 						addr + done, aspace, cycle);  in fake_master_write()
761 					addr + done, aspace, cycle);  in fake_master_write()
768 					addr + done, aspace, cycle);  in fake_master_write()
775 					aspace, cycle);  in fake_master_write()
784 					addr + done, aspace, cycle);  in fake_master_write()
791 				cycle);  in fake_master_write()
813 	u32 aspace, cycle;  in fake_master_rmw()  local
824 	cycle = bridge->masters[i].cycle;  in fake_master_rmw()
830 	tmp = fake_vmeread32(bridge, base + offset, aspace, cycle);  in fake_master_rmw()
838 		fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle);  in fake_master_rmw()
855 		u32 aspace, u32 cycle)  in fake_lm_set()  argument
890 	bridge->lm_cycle = cycle;  in fake_lm_set()
901 		unsigned long long *lm_base, u32 *aspace, u32 *cycle)  in fake_lm_get()  argument
911 	*cycle = bridge->lm_cycle;  in fake_lm_get()