69 	struct fake_master_window masters[FAKE_MAX_MASTER];  member
321 	bridge->masters[i].enabled = enabled;  in fake_master_set()
322 	bridge->masters[i].vme_base = vme_base;  in fake_master_set()
323 	bridge->masters[i].size = size;  in fake_master_set()
324 	bridge->masters[i].aspace = aspace;  in fake_master_set()
325 	bridge->masters[i].cycle = cycle;  in fake_master_set()
326 	bridge->masters[i].dwidth = dwidth;  in fake_master_set()
353 	*enabled = bridge->masters[i].enabled;  in __fake_master_get()
354 	*vme_base = bridge->masters[i].vme_base;  in __fake_master_get()
355 	*size = bridge->masters[i].size;  in __fake_master_get()
356 	*aspace = bridge->masters[i].aspace;  in __fake_master_get()
357 	*cycle = bridge->masters[i].cycle;  in __fake_master_get()
358 	*dwidth = bridge->masters[i].dwidth;  in __fake_master_get()
535 	addr = (unsigned long long)priv->masters[i].vme_base + offset;  in fake_master_read()
536 	aspace = priv->masters[i].aspace;  in fake_master_read()
537 	cycle = priv->masters[i].cycle;  in fake_master_read()
538 	dwidth = priv->masters[i].dwidth;  in fake_master_read()
725 	addr = bridge->masters[i].vme_base + offset;  in fake_master_write()
726 	aspace = bridge->masters[i].aspace;  in fake_master_write()
727 	cycle = bridge->masters[i].cycle;  in fake_master_write()
728 	dwidth = bridge->masters[i].dwidth;  in fake_master_write()
822 	base = bridge->masters[i].vme_base;  in fake_master_rmw()
823 	aspace = bridge->masters[i].aspace;  in fake_master_rmw()
824 	cycle = bridge->masters[i].cycle;  in fake_master_rmw()
1263 		bridge->masters[i].enabled = 0;  in fake_exit()