Lines Matching refs:bridge
79 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, in tsi148_DMA_irqhandler() argument
85 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
89 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
99 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) in tsi148_LM_irqhandler() argument
107 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
125 struct tsi148_driver *bridge; in tsi148_MB_irqhandler() local
127 bridge = tsi148_bridge->driver_priv; in tsi148_MB_irqhandler()
131 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
146 struct tsi148_driver *bridge; in tsi148_PERR_irqhandler() local
148 bridge = tsi148_bridge->driver_priv; in tsi148_PERR_irqhandler()
152 ioread32be(bridge->base + TSI148_LCSR_EDPAU), in tsi148_PERR_irqhandler()
153 ioread32be(bridge->base + TSI148_LCSR_EDPAL), in tsi148_PERR_irqhandler()
154 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); in tsi148_PERR_irqhandler()
158 ioread32be(bridge->base + TSI148_LCSR_EDPXA), in tsi148_PERR_irqhandler()
159 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); in tsi148_PERR_irqhandler()
161 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); in tsi148_PERR_irqhandler()
175 struct tsi148_driver *bridge; in tsi148_VERR_irqhandler() local
177 bridge = tsi148_bridge->driver_priv; in tsi148_VERR_irqhandler()
179 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); in tsi148_VERR_irqhandler()
180 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); in tsi148_VERR_irqhandler()
181 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); in tsi148_VERR_irqhandler()
200 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); in tsi148_VERR_irqhandler()
208 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) in tsi148_IACK_irqhandler() argument
210 wake_up(&bridge->iack_queue); in tsi148_IACK_irqhandler()
222 struct tsi148_driver *bridge; in tsi148_VIRQ_irqhandler() local
224 bridge = tsi148_bridge->driver_priv; in tsi148_VIRQ_irqhandler()
233 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); in tsi148_VIRQ_irqhandler()
252 struct tsi148_driver *bridge; in tsi148_irqhandler() local
256 bridge = tsi148_bridge->driver_priv; in tsi148_irqhandler()
259 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irqhandler()
260 stat = ioread32be(bridge->base + TSI148_LCSR_INTS); in tsi148_irqhandler()
271 serviced |= tsi148_DMA_irqhandler(bridge, stat); in tsi148_irqhandler()
276 serviced |= tsi148_LM_irqhandler(bridge, stat); in tsi148_irqhandler()
293 serviced |= tsi148_IACK_irqhandler(bridge); in tsi148_irqhandler()
303 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); in tsi148_irqhandler()
313 struct tsi148_driver *bridge; in tsi148_irq_init() local
317 bridge = tsi148_bridge->driver_priv; in tsi148_irq_init()
363 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_init()
364 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_init()
372 struct tsi148_driver *bridge = tsi148_bridge->driver_priv; in tsi148_irq_exit() local
375 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_exit()
376 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_exit()
379 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); in tsi148_irq_exit()
388 static int tsi148_iack_received(struct tsi148_driver *bridge) in tsi148_iack_received() argument
392 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_iack_received()
408 struct tsi148_driver *bridge; in tsi148_irq_set() local
410 bridge = tsi148_bridge->driver_priv; in tsi148_irq_set()
414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
418 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
420 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_irq_set()
431 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
433 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_irq_set()
445 struct tsi148_driver *bridge; in tsi148_irq_generate() local
447 bridge = tsi148_bridge->driver_priv; in tsi148_irq_generate()
449 mutex_lock(&bridge->vme_int); in tsi148_irq_generate()
452 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
457 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
461 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); in tsi148_irq_generate()
464 wait_event_interruptible(bridge->iack_queue, in tsi148_irq_generate()
465 tsi148_iack_received(bridge)); in tsi148_irq_generate()
467 mutex_unlock(&bridge->vme_int); in tsi148_irq_generate()
486 struct tsi148_driver *bridge; in tsi148_slave_set() local
489 bridge = tsi148_bridge->driver_priv; in tsi148_slave_set()
543 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
546 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
550 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
552 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
554 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
556 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
558 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
560 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
605 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
611 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()
629 struct tsi148_driver *bridge; in tsi148_slave_get() local
631 bridge = image->parent->driver_priv; in tsi148_slave_get()
636 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
639 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
641 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
643 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
645 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
647 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
649 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_get()
825 struct tsi148_driver *bridge; in tsi148_master_set() local
831 bridge = tsi148_bridge->driver_priv; in tsi148_master_set()
909 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
912 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1014 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1016 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1018 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1020 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1022 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1024 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1028 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1034 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_set()
1065 struct tsi148_driver *bridge; in __tsi148_master_get() local
1067 bridge = image->parent->driver_priv; in __tsi148_master_get()
1071 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1074 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1076 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1078 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1080 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1082 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1084 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in __tsi148_master_get()
1279 struct tsi148_driver *bridge; in tsi148_master_write() local
1283 bridge = tsi148_bridge->driver_priv; in tsi148_master_write()
1348 ioread16(bridge->flush_image->kern_base + 0x7F000); in tsi148_master_write()
1377 struct tsi148_driver *bridge; in tsi148_master_rmw() local
1379 bridge = image->parent->driver_priv; in tsi148_master_rmw()
1385 mutex_lock(&bridge->vme_rmw); in tsi148_master_rmw()
1390 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1392 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + in tsi148_master_rmw()
1399 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); in tsi148_master_rmw()
1400 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); in tsi148_master_rmw()
1401 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); in tsi148_master_rmw()
1402 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); in tsi148_master_rmw()
1403 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); in tsi148_master_rmw()
1406 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1408 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1414 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1416 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); in tsi148_master_rmw()
1420 mutex_unlock(&bridge->vme_rmw); in tsi148_master_rmw()
1795 struct tsi148_driver *bridge; in tsi148_dma_busy() local
1797 bridge = tsi148_bridge->driver_priv; in tsi148_dma_busy()
1799 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_busy()
1822 struct tsi148_driver *bridge; in tsi148_dma_list_exec() local
1828 bridge = tsi148_bridge->driver_priv; in tsi148_dma_list_exec()
1855 iowrite32be(bus_addr_high, bridge->base + in tsi148_dma_list_exec()
1857 iowrite32be(bus_addr_low, bridge->base + in tsi148_dma_list_exec()
1860 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1864 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + in tsi148_dma_list_exec()
1867 retval = wait_event_interruptible(bridge->dma_queue[channel], in tsi148_dma_list_exec()
1871 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base + in tsi148_dma_list_exec()
1874 wait_event(bridge->dma_queue[channel], in tsi148_dma_list_exec()
1884 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + in tsi148_dma_list_exec()
1939 struct tsi148_driver *bridge; in tsi148_lm_set() local
1943 bridge = tsi148_bridge->driver_priv; in tsi148_lm_set()
1949 if (bridge->lm_callback[i] != NULL) { in tsi148_lm_set()
1988 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); in tsi148_lm_set()
1989 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); in tsi148_lm_set()
1990 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_set()
2004 struct tsi148_driver *bridge; in tsi148_lm_get() local
2006 bridge = lm->parent->driver_priv; in tsi148_lm_get()
2010 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); in tsi148_lm_get()
2011 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); in tsi148_lm_get()
2012 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_get()
2056 struct tsi148_driver *bridge; in tsi148_lm_attach() local
2060 bridge = tsi148_bridge->driver_priv; in tsi148_lm_attach()
2065 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_attach()
2074 if (bridge->lm_callback[monitor] != NULL) { in tsi148_lm_attach()
2081 bridge->lm_callback[monitor] = callback; in tsi148_lm_attach()
2082 bridge->lm_data[monitor] = data; in tsi148_lm_attach()
2085 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_attach()
2087 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_attach()
2089 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_attach()
2091 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_attach()
2096 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_attach()
2110 struct tsi148_driver *bridge; in tsi148_lm_detach() local
2112 bridge = lm->parent->driver_priv; in tsi148_lm_detach()
2117 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_detach()
2119 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); in tsi148_lm_detach()
2121 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_detach()
2123 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); in tsi148_lm_detach()
2126 bridge->base + TSI148_LCSR_INTC); in tsi148_lm_detach()
2129 bridge->lm_callback[monitor] = NULL; in tsi148_lm_detach()
2130 bridge->lm_data[monitor] = NULL; in tsi148_lm_detach()
2135 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_detach()
2137 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); in tsi148_lm_detach()
2151 struct tsi148_driver *bridge; in tsi148_slot_get() local
2153 bridge = tsi148_bridge->driver_priv; in tsi148_slot_get()
2156 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); in tsi148_slot_get()
2204 struct tsi148_driver *bridge; in tsi148_crcsr_init() local
2206 bridge = tsi148_bridge->driver_priv; in tsi148_crcsr_init()
2209 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, in tsi148_crcsr_init()
2210 &bridge->crcsr_bus); in tsi148_crcsr_init()
2211 if (bridge->crcsr_kernel == NULL) { in tsi148_crcsr_init()
2217 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); in tsi148_crcsr_init()
2219 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); in tsi148_crcsr_init()
2220 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); in tsi148_crcsr_init()
2223 cbar = ioread32be(bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2231 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); in tsi148_crcsr_init()
2235 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_init()
2241 bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_init()
2249 retval = tsi148_master_set(bridge->flush_image, 1, in tsi148_crcsr_init()
2265 struct tsi148_driver *bridge; in tsi148_crcsr_exit() local
2267 bridge = tsi148_bridge->driver_priv; in tsi148_crcsr_exit()
2270 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_exit()
2272 bridge->base + TSI148_LCSR_CRAT); in tsi148_crcsr_exit()
2275 iowrite32be(0, bridge->base + TSI148_LCSR_CROU); in tsi148_crcsr_exit()
2276 iowrite32be(0, bridge->base + TSI148_LCSR_CROL); in tsi148_crcsr_exit()
2278 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, in tsi148_crcsr_exit()
2279 bridge->crcsr_bus); in tsi148_crcsr_exit()
2595 struct tsi148_driver *bridge; in tsi148_remove() local
2598 bridge = tsi148_bridge->driver_priv; in tsi148_remove()
2607 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + in tsi148_remove()
2609 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + in tsi148_remove()
2616 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); in tsi148_remove()
2621 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); in tsi148_remove()
2626 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); in tsi148_remove()
2627 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); in tsi148_remove()
2628 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); in tsi148_remove()
2633 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) in tsi148_remove()
2634 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); in tsi148_remove()
2639 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); in tsi148_remove()
2640 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); in tsi148_remove()
2670 iounmap(bridge->base); in tsi148_remove()