1 /*******************************************************************************
2 *
3 * "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
4 *
5 * Copyright (C) 2001 Broadcom Corporation.
6 * Copyright (C) 2000,2001 Cirrus Logic Corp.
7 * -- adapted from drivers by Thomas Sailer,
8 * -- but don't bug him; Problems should go to:
9 * -- tom woller (twoller@crystal.cirrus.com) or
10 * (audio@crystal.cirrus.com).
11 * -- adapted from cs4281 PCI driver for cs4297a on
12 * BCM1250 Synchronous Serial interface
13 * (Kip Walker, Broadcom Corp.)
14 * Copyright (C) 2004 Maciej W. Rozycki
15 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Module command line parameters:
32 * none
33 *
34 * Supported devices:
35 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
36 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
37 * /dev/midi simple MIDI UART interface, no ioctl
38 *
39 * Modification History
40 * 08/20/00 trw - silence and no stopping DAC until release
41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
42 * 09/18/00 trw - added 16bit only record with conversion
43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
44 * capture/playback rates)
45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
46 * libOSSm.so)
47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
53 * 12/08/00 trw - added PM support.
54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
55 * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
58 * defaultorder-100 as power of 2 for the buffer size. example:
59 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
60 *
61 *******************************************************************************/
62
63 #include <linux/list.h>
64 #include <linux/module.h>
65 #include <linux/string.h>
66 #include <linux/ioport.h>
67 #include <linux/sched.h>
68 #include <linux/delay.h>
69 #include <linux/sound.h>
70 #include <linux/slab.h>
71 #include <linux/soundcard.h>
72 #include <linux/pci.h>
73 #include <linux/bitops.h>
74 #include <linux/interrupt.h>
75 #include <linux/init.h>
76 #include <linux/poll.h>
77 #include <linux/mutex.h>
78 #include <linux/kernel.h>
79
80 #include <asm/byteorder.h>
81 #include <asm/dma.h>
82 #include <asm/io.h>
83 #include <asm/uaccess.h>
84
85 #include <asm/sibyte/sb1250_regs.h>
86 #include <asm/sibyte/sb1250_int.h>
87 #include <asm/sibyte/sb1250_dma.h>
88 #include <asm/sibyte/sb1250_scd.h>
89 #include <asm/sibyte/sb1250_syncser.h>
90 #include <asm/sibyte/sb1250_mac.h>
91 #include <asm/sibyte/sb1250.h>
92
93 #include "sleep.h"
94
95 struct cs4297a_state;
96
97 static DEFINE_MUTEX(swarm_cs4297a_mutex);
98 static void stop_dac(struct cs4297a_state *s);
99 static void stop_adc(struct cs4297a_state *s);
100 static void start_dac(struct cs4297a_state *s);
101 static void start_adc(struct cs4297a_state *s);
102 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
103
104 // ---------------------------------------------------------------------
105
106 #define CS4297a_MAGIC 0xf00beef1
107
108 // buffer order determines the size of the dma buffer for the driver.
109 // under Linux, a smaller buffer allows more responsiveness from many of the
110 // applications (e.g. games). A larger buffer allows some of the apps (esound)
111 // to not underrun the dma buffer as easily. As default, use 32k (order=3)
112 // rather than 64k as some of the games work more responsively.
113 // log base 2( buff sz = 32k).
114
115 //
116 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
117 //
118 #define CSDEBUG 0
119 #if CSDEBUG
120 #define CSDEBUG_INTERFACE 1
121 #else
122 #undef CSDEBUG_INTERFACE
123 #endif
124 //
125 // cs_debugmask areas
126 //
127 #define CS_INIT 0x00000001 // initialization and probe functions
128 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
129 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
130 #define CS_FUNCTION 0x00000008 // enter/leave functions
131 #define CS_WAVE_WRITE 0x00000010 // write information for wave
132 #define CS_WAVE_READ 0x00000020 // read information for wave
133 #define CS_AC97 0x00000040 // AC97 register access
134 #define CS_DESCR 0x00000080 // descriptor management
135 #define CS_OPEN 0x00000400 // all open functions in the driver
136 #define CS_RELEASE 0x00000800 // all release functions in the driver
137 #define CS_PARMS 0x00001000 // functional and operational parameters
138 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
139 #define CS_TMP 0x10000000 // tmp debug mask bit
140
141 //
142 // CSDEBUG is usual mode is set to 1, then use the
143 // cs_debuglevel and cs_debugmask to turn on or off debugging.
144 // Debug level of 1 has been defined to be kernel errors and info
145 // that should be printed on any released driver.
146 //
147 #if CSDEBUG
148 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
149 #else
150 #define CS_DBGOUT(mask,level,x)
151 #endif
152
153 #if CSDEBUG
154 static unsigned long cs_debuglevel = 4; // levels range from 1-9
155 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
156 module_param(cs_debuglevel, int, 0);
157 module_param(cs_debugmask, int, 0);
158 #endif
159 #define CS_TRUE 1
160 #define CS_FALSE 0
161
162 #define CS_TYPE_ADC 0
163 #define CS_TYPE_DAC 1
164
165 #define SER_BASE (A_SER_BASE_1 + KSEG1)
166 #define SS_CSR(t) (SER_BASE+t)
167 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
168 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
169
170 #define FRAME_BYTES 32
171 #define FRAME_SAMPLE_BYTES 4
172
173 /* Should this be variable? */
174 #define SAMPLE_BUF_SIZE (16*1024)
175 #define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
176 /* The driver can explode/shrink the frames to/from a smaller sample
177 buffer */
178 #define DMA_BLOAT_FACTOR 1
179 #define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
180 #define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
181
182 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
183 #define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
184
185 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
186 #define REG_LATENCY 150
187
188 #define FRAME_TX_US 20
189
190 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
191
192 static const char invalid_magic[] =
193 KERN_CRIT "cs4297a: invalid magic value\n";
194
195 #define VALIDATE_STATE(s) \
196 ({ \
197 if (!(s) || (s)->magic != CS4297a_MAGIC) { \
198 printk(invalid_magic); \
199 return -ENXIO; \
200 } \
201 })
202
203 /* AC97 registers */
204 #define AC97_MASTER_VOL_STEREO 0x0002 /* Line Out */
205 #define AC97_PCBEEP_VOL 0x000a /* none */
206 #define AC97_PHONE_VOL 0x000c /* TAD Input (mono) */
207 #define AC97_MIC_VOL 0x000e /* MIC Input (mono) */
208 #define AC97_LINEIN_VOL 0x0010 /* Line Input (stereo) */
209 #define AC97_CD_VOL 0x0012 /* CD Input (stereo) */
210 #define AC97_AUX_VOL 0x0016 /* Aux Input (stereo) */
211 #define AC97_PCMOUT_VOL 0x0018 /* Wave Output (stereo) */
212 #define AC97_RECORD_SELECT 0x001a /* */
213 #define AC97_RECORD_GAIN 0x001c
214 #define AC97_GENERAL_PURPOSE 0x0020
215 #define AC97_3D_CONTROL 0x0022
216 #define AC97_POWER_CONTROL 0x0026
217 #define AC97_VENDOR_ID1 0x007c
218
219 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
220
221 typedef struct serdma_descr_s {
222 u64 descr_a;
223 u64 descr_b;
224 } serdma_descr_t;
225
226 typedef unsigned long paddr_t;
227
228 typedef struct serdma_s {
229 unsigned ringsz;
230 serdma_descr_t *descrtab;
231 serdma_descr_t *descrtab_end;
232 paddr_t descrtab_phys;
233
234 serdma_descr_t *descr_add;
235 serdma_descr_t *descr_rem;
236
237 u64 *dma_buf; // buffer for DMA contents (frames)
238 paddr_t dma_buf_phys;
239 u16 *sample_buf; // tmp buffer for sample conversions
240 u16 *sb_swptr;
241 u16 *sb_hwptr;
242 u16 *sb_end;
243
244 dma_addr_t dmaaddr;
245 // unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
246 unsigned numfrag; // # of 'fragments' in the buffer.
247 unsigned fragshift; // Log base 2 of fragment size.
248 unsigned hwptr, swptr;
249 unsigned total_bytes; // # bytes process since open.
250 unsigned blocks; // last returned blocks value GETOPTR
251 unsigned wakeup; // interrupt occurred on block
252 int count;
253 unsigned underrun; // underrun flag
254 unsigned error; // over/underrun
255 wait_queue_head_t wait;
256 wait_queue_head_t reg_wait;
257 // redundant, but makes calculations easier
258 unsigned fragsize; // 2**fragshift..
259 unsigned sbufsz; // 2**buforder.
260 unsigned fragsamples;
261 // OSS stuff
262 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
263 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
264 unsigned endcleared:1;
265 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
266 unsigned ossfragshift;
267 int ossmaxfrags;
268 unsigned subdivision;
269 } serdma_t;
270
271 struct cs4297a_state {
272 // magic
273 unsigned int magic;
274
275 struct list_head list;
276
277 // soundcore stuff
278 int dev_audio;
279 int dev_mixer;
280
281 // hardware resources
282 unsigned int irq;
283
284 struct {
285 unsigned int rx_ovrrn; /* FIFO */
286 unsigned int rx_overflow; /* staging buffer */
287 unsigned int tx_underrun;
288 unsigned int rx_bad;
289 unsigned int rx_good;
290 } stats;
291
292 // mixer registers
293 struct {
294 unsigned short vol[10];
295 unsigned int recsrc;
296 unsigned int modcnt;
297 unsigned short micpreamp;
298 } mix;
299
300 // wave stuff
301 struct properties {
302 unsigned fmt;
303 unsigned fmt_original; // original requested format
304 unsigned channels;
305 unsigned rate;
306 } prop_dac, prop_adc;
307 unsigned conversion:1; // conversion from 16 to 8 bit in progress
308 unsigned ena;
309 spinlock_t lock;
310 struct mutex open_mutex;
311 struct mutex open_sem_adc;
312 struct mutex open_sem_dac;
313 fmode_t open_mode;
314 wait_queue_head_t open_wait;
315 wait_queue_head_t open_wait_adc;
316 wait_queue_head_t open_wait_dac;
317
318 dma_addr_t dmaaddr_sample_buf;
319 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
320
321 serdma_t dma_dac, dma_adc;
322
323 volatile u16 read_value;
324 volatile u16 read_reg;
325 volatile u64 reg_request;
326 };
327
328 #if 1
329 #define prog_codec(a,b)
330 #define dealloc_dmabuf(a,b);
331 #endif
332
prog_dmabuf_adc(struct cs4297a_state * s)333 static int prog_dmabuf_adc(struct cs4297a_state *s)
334 {
335 s->dma_adc.ready = 1;
336 return 0;
337 }
338
339
prog_dmabuf_dac(struct cs4297a_state * s)340 static int prog_dmabuf_dac(struct cs4297a_state *s)
341 {
342 s->dma_dac.ready = 1;
343 return 0;
344 }
345
clear_advance(void * buf,unsigned bsize,unsigned bptr,unsigned len,unsigned char c)346 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
347 unsigned len, unsigned char c)
348 {
349 if (bptr + len > bsize) {
350 unsigned x = bsize - bptr;
351 memset(((char *) buf) + bptr, c, x);
352 bptr = 0;
353 len -= x;
354 }
355 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
356 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
357 (unsigned)c, (unsigned)((char *) buf) + bptr, len));
358 memset(((char *) buf) + bptr, c, len);
359 }
360
361 #if CSDEBUG
362
363 // DEBUG ROUTINES
364
365 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
366 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
367 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
368 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
369
cs_printioctl(unsigned int x)370 static void cs_printioctl(unsigned int x)
371 {
372 unsigned int i;
373 unsigned char vidx;
374 // Index of mixtable1[] member is Device ID
375 // and must be <= SOUND_MIXER_NRDEVICES.
376 // Value of array member is index into s->mix.vol[]
377 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
378 [SOUND_MIXER_PCM] = 1, // voice
379 [SOUND_MIXER_LINE1] = 2, // AUX
380 [SOUND_MIXER_CD] = 3, // CD
381 [SOUND_MIXER_LINE] = 4, // Line
382 [SOUND_MIXER_SYNTH] = 5, // FM
383 [SOUND_MIXER_MIC] = 6, // Mic
384 [SOUND_MIXER_SPEAKER] = 7, // Speaker
385 [SOUND_MIXER_RECLEV] = 8, // Recording level
386 [SOUND_MIXER_VOLUME] = 9 // Master Volume
387 };
388
389 switch (x) {
390 case SOUND_MIXER_CS_GETDBGMASK:
391 CS_DBGOUT(CS_IOCTL, 4,
392 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
393 break;
394 case SOUND_MIXER_CS_GETDBGLEVEL:
395 CS_DBGOUT(CS_IOCTL, 4,
396 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
397 break;
398 case SOUND_MIXER_CS_SETDBGMASK:
399 CS_DBGOUT(CS_IOCTL, 4,
400 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
401 break;
402 case SOUND_MIXER_CS_SETDBGLEVEL:
403 CS_DBGOUT(CS_IOCTL, 4,
404 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
405 break;
406 case OSS_GETVERSION:
407 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
408 break;
409 case SNDCTL_DSP_SYNC:
410 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
411 break;
412 case SNDCTL_DSP_SETDUPLEX:
413 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
414 break;
415 case SNDCTL_DSP_GETCAPS:
416 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
417 break;
418 case SNDCTL_DSP_RESET:
419 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
420 break;
421 case SNDCTL_DSP_SPEED:
422 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
423 break;
424 case SNDCTL_DSP_STEREO:
425 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
426 break;
427 case SNDCTL_DSP_CHANNELS:
428 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
429 break;
430 case SNDCTL_DSP_GETFMTS:
431 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
432 break;
433 case SNDCTL_DSP_SETFMT:
434 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
435 break;
436 case SNDCTL_DSP_POST:
437 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
438 break;
439 case SNDCTL_DSP_GETTRIGGER:
440 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
441 break;
442 case SNDCTL_DSP_SETTRIGGER:
443 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
444 break;
445 case SNDCTL_DSP_GETOSPACE:
446 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
447 break;
448 case SNDCTL_DSP_GETISPACE:
449 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
450 break;
451 case SNDCTL_DSP_NONBLOCK:
452 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
453 break;
454 case SNDCTL_DSP_GETODELAY:
455 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
456 break;
457 case SNDCTL_DSP_GETIPTR:
458 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
459 break;
460 case SNDCTL_DSP_GETOPTR:
461 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
462 break;
463 case SNDCTL_DSP_GETBLKSIZE:
464 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
465 break;
466 case SNDCTL_DSP_SETFRAGMENT:
467 CS_DBGOUT(CS_IOCTL, 4,
468 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
469 break;
470 case SNDCTL_DSP_SUBDIVIDE:
471 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
472 break;
473 case SOUND_PCM_READ_RATE:
474 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
475 break;
476 case SOUND_PCM_READ_CHANNELS:
477 CS_DBGOUT(CS_IOCTL, 4,
478 printk("SOUND_PCM_READ_CHANNELS:\n"));
479 break;
480 case SOUND_PCM_READ_BITS:
481 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
482 break;
483 case SOUND_PCM_WRITE_FILTER:
484 CS_DBGOUT(CS_IOCTL, 4,
485 printk("SOUND_PCM_WRITE_FILTER:\n"));
486 break;
487 case SNDCTL_DSP_SETSYNCRO:
488 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
489 break;
490 case SOUND_PCM_READ_FILTER:
491 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
492 break;
493 case SOUND_MIXER_PRIVATE1:
494 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
495 break;
496 case SOUND_MIXER_PRIVATE2:
497 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
498 break;
499 case SOUND_MIXER_PRIVATE3:
500 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
501 break;
502 case SOUND_MIXER_PRIVATE4:
503 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
504 break;
505 case SOUND_MIXER_PRIVATE5:
506 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
507 break;
508 case SOUND_MIXER_INFO:
509 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
510 break;
511 case SOUND_OLD_MIXER_INFO:
512 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
513 break;
514
515 default:
516 switch (_IOC_NR(x)) {
517 case SOUND_MIXER_VOLUME:
518 CS_DBGOUT(CS_IOCTL, 4,
519 printk("SOUND_MIXER_VOLUME:\n"));
520 break;
521 case SOUND_MIXER_SPEAKER:
522 CS_DBGOUT(CS_IOCTL, 4,
523 printk("SOUND_MIXER_SPEAKER:\n"));
524 break;
525 case SOUND_MIXER_RECLEV:
526 CS_DBGOUT(CS_IOCTL, 4,
527 printk("SOUND_MIXER_RECLEV:\n"));
528 break;
529 case SOUND_MIXER_MIC:
530 CS_DBGOUT(CS_IOCTL, 4,
531 printk("SOUND_MIXER_MIC:\n"));
532 break;
533 case SOUND_MIXER_SYNTH:
534 CS_DBGOUT(CS_IOCTL, 4,
535 printk("SOUND_MIXER_SYNTH:\n"));
536 break;
537 case SOUND_MIXER_RECSRC:
538 CS_DBGOUT(CS_IOCTL, 4,
539 printk("SOUND_MIXER_RECSRC:\n"));
540 break;
541 case SOUND_MIXER_DEVMASK:
542 CS_DBGOUT(CS_IOCTL, 4,
543 printk("SOUND_MIXER_DEVMASK:\n"));
544 break;
545 case SOUND_MIXER_RECMASK:
546 CS_DBGOUT(CS_IOCTL, 4,
547 printk("SOUND_MIXER_RECMASK:\n"));
548 break;
549 case SOUND_MIXER_STEREODEVS:
550 CS_DBGOUT(CS_IOCTL, 4,
551 printk("SOUND_MIXER_STEREODEVS:\n"));
552 break;
553 case SOUND_MIXER_CAPS:
554 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
555 break;
556 default:
557 i = _IOC_NR(x);
558 if (i >= SOUND_MIXER_NRDEVICES
559 || !(vidx = mixtable1[i])) {
560 CS_DBGOUT(CS_IOCTL, 4, printk
561 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
562 x, i));
563 } else {
564 CS_DBGOUT(CS_IOCTL, 4, printk
565 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
566 x, i));
567 }
568 break;
569 }
570 }
571 }
572 #endif
573
574
ser_init(struct cs4297a_state * s)575 static int ser_init(struct cs4297a_state *s)
576 {
577 int i;
578
579 CS_DBGOUT(CS_INIT, 2,
580 printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
581
582 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
583
584 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
585 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
586 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
587
588 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
589 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
590 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
591
592 /* This looks good from experimentation */
593 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
594 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
595 SS_CSR(R_SER_LINE_MODE));
596
597 /* This looks good from experimentation */
598 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
599 SS_TXTBL(0));
600 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
601 SS_TXTBL(1));
602 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
603 SS_TXTBL(2));
604 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
605 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
606
607 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
608 SS_RXTBL(0));
609 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
610 SS_RXTBL(1));
611 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
612 SS_RXTBL(2));
613 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
614 M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
615
616 for (i=4; i<16; i++) {
617 /* Just in case... */
618 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
619 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
620 }
621
622 return 0;
623 }
624
init_serdma(serdma_t * dma)625 static int init_serdma(serdma_t *dma)
626 {
627 CS_DBGOUT(CS_INIT, 2,
628 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
629 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
630
631 /* Descriptors */
632 dma->ringsz = DMA_DESCR;
633 dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
634 if (!dma->descrtab) {
635 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
636 return -1;
637 }
638 dma->descrtab_end = dma->descrtab + dma->ringsz;
639 /* XXX bloddy mess, use proper DMA API here ... */
640 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
641 dma->descr_add = dma->descr_rem = dma->descrtab;
642
643 /* Frame buffer area */
644 dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
645 if (!dma->dma_buf) {
646 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
647 kfree(dma->descrtab);
648 return -1;
649 }
650 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
651
652 /* Samples buffer area */
653 dma->sbufsz = SAMPLE_BUF_SIZE;
654 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
655 if (!dma->sample_buf) {
656 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
657 kfree(dma->descrtab);
658 kfree(dma->dma_buf);
659 return -1;
660 }
661 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
662 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
663 dma->fragsize = dma->sbufsz >> 1;
664
665 CS_DBGOUT(CS_INIT, 4,
666 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
667 (int)dma->descrtab, (int)dma->dma_buf,
668 (int)dma->sample_buf));
669
670 return 0;
671 }
672
dma_init(struct cs4297a_state * s)673 static int dma_init(struct cs4297a_state *s)
674 {
675 int i;
676
677 CS_DBGOUT(CS_INIT, 2,
678 printk(KERN_INFO "cs4297a: Setting up DMA\n"));
679
680 if (init_serdma(&s->dma_adc) ||
681 init_serdma(&s->dma_dac))
682 return -1;
683
684 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
685 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
686 panic("DMA state corrupted?!");
687 }
688
689 /* Initialize now - the descr/buffer pairings will never
690 change... */
691 for (i=0; i<DMA_DESCR; i++) {
692 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
693 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
694 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
695 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
696 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
697 s->dma_adc.descrtab[i].descr_b = 0;
698 }
699
700 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
701 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
702 SS_CSR(R_SER_DMA_CONFIG0_RX));
703 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
704 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
705
706 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
707 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
708 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
709
710 /* Prep the receive DMA descriptor ring */
711 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
712
713 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
714
715 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
716 SS_CSR(R_SER_INT_MASK));
717
718 /* Enable the rx/tx; let the codec warm up to the sync and
719 start sending good frames before the receive FIFO is
720 enabled */
721 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
722 udelay(1000);
723 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
724
725 /* XXXKW is this magic? (the "1" part) */
726 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
727 ;
728
729 CS_DBGOUT(CS_INIT, 4,
730 printk(KERN_INFO "cs4297a: status: %08x\n",
731 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
732
733 return 0;
734 }
735
serdma_reg_access(struct cs4297a_state * s,u64 data)736 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
737 {
738 serdma_t *d = &s->dma_dac;
739 u64 *data_p;
740 unsigned swptr;
741 unsigned long flags;
742 serdma_descr_t *descr;
743
744 if (s->reg_request) {
745 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
746 return -1;
747 }
748
749 if (s->ena & FMODE_WRITE) {
750 /* Since a writer has the DSP open, we have to mux the
751 request in */
752 s->reg_request = data;
753 oss_broken_sleep_on(&s->dma_dac.reg_wait, MAX_SCHEDULE_TIMEOUT);
754 /* XXXKW how can I deal with the starvation case where
755 the opener isn't writing? */
756 } else {
757 /* Be safe when changing ring pointers */
758 spin_lock_irqsave(&s->lock, flags);
759 if (d->hwptr != d->swptr) {
760 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
761 d->hwptr, d->swptr);
762 spin_unlock_irqrestore(&s->lock, flags);
763 return -1;
764 }
765 swptr = d->swptr;
766 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
767 spin_unlock_irqrestore(&s->lock, flags);
768
769 descr = &d->descrtab[swptr];
770 data_p = &d->dma_buf[swptr * 4];
771 *data_p = cpu_to_be64(data);
772 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
773 CS_DBGOUT(CS_DESCR, 4,
774 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
775 data_p, swptr, d->hwptr));
776 }
777
778 CS_DBGOUT(CS_FUNCTION, 6,
779 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
780
781 return 0;
782 }
783
784 //****************************************************************************
785 // "cs4297a_read_ac97" -- Reads an AC97 register
786 //****************************************************************************
cs4297a_read_ac97(struct cs4297a_state * s,u32 offset,u32 * value)787 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
788 u32 * value)
789 {
790 CS_DBGOUT(CS_AC97, 1,
791 printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
792 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
793 return -1;
794
795 oss_broken_sleep_on(&s->dma_adc.reg_wait, MAX_SCHEDULE_TIMEOUT);
796 *value = s->read_value;
797 CS_DBGOUT(CS_AC97, 2,
798 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
799
800 return 0;
801 }
802
803
804 //****************************************************************************
805 // "cs4297a_write_ac97()"-- writes an AC97 register
806 //****************************************************************************
cs4297a_write_ac97(struct cs4297a_state * s,u32 offset,u32 value)807 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
808 u32 value)
809 {
810 CS_DBGOUT(CS_AC97, 1,
811 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
812 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
813 }
814
stop_dac(struct cs4297a_state * s)815 static void stop_dac(struct cs4297a_state *s)
816 {
817 unsigned long flags;
818
819 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
820 spin_lock_irqsave(&s->lock, flags);
821 s->ena &= ~FMODE_WRITE;
822 #if 0
823 /* XXXKW what do I really want here? My theory for now is
824 that I just flip the "ena" bit, and the interrupt handler
825 will stop processing the xmit channel */
826 __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
827 SS_CSR(R_SER_DMA_ENABLE));
828 #endif
829
830 spin_unlock_irqrestore(&s->lock, flags);
831 }
832
833
start_dac(struct cs4297a_state * s)834 static void start_dac(struct cs4297a_state *s)
835 {
836 unsigned long flags;
837
838 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
839 spin_lock_irqsave(&s->lock, flags);
840 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
841 (s->dma_dac.count > 0
842 && s->dma_dac.ready))) {
843 s->ena |= FMODE_WRITE;
844 /* XXXKW what do I really want here? My theory for
845 now is that I just flip the "ena" bit, and the
846 interrupt handler will start processing the xmit
847 channel */
848
849 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
850 "cs4297a: start_dac(): start dma\n"));
851
852 }
853 spin_unlock_irqrestore(&s->lock, flags);
854 CS_DBGOUT(CS_FUNCTION, 3,
855 printk(KERN_INFO "cs4297a: start_dac()-\n"));
856 }
857
858
stop_adc(struct cs4297a_state * s)859 static void stop_adc(struct cs4297a_state *s)
860 {
861 unsigned long flags;
862
863 CS_DBGOUT(CS_FUNCTION, 3,
864 printk(KERN_INFO "cs4297a: stop_adc()+\n"));
865
866 spin_lock_irqsave(&s->lock, flags);
867 s->ena &= ~FMODE_READ;
868
869 if (s->conversion == 1) {
870 s->conversion = 0;
871 s->prop_adc.fmt = s->prop_adc.fmt_original;
872 }
873 /* Nothing to do really, I need to keep the DMA going
874 XXXKW when do I get here, and is there more I should do? */
875 spin_unlock_irqrestore(&s->lock, flags);
876 CS_DBGOUT(CS_FUNCTION, 3,
877 printk(KERN_INFO "cs4297a: stop_adc()-\n"));
878 }
879
880
start_adc(struct cs4297a_state * s)881 static void start_adc(struct cs4297a_state *s)
882 {
883 unsigned long flags;
884
885 CS_DBGOUT(CS_FUNCTION, 2,
886 printk(KERN_INFO "cs4297a: start_adc()+\n"));
887
888 if (!(s->ena & FMODE_READ) &&
889 (s->dma_adc.mapped || s->dma_adc.count <=
890 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
891 && s->dma_adc.ready) {
892 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
893 //
894 // now only use 16 bit capture, due to truncation issue
895 // in the chip, noticeable distortion occurs.
896 // allocate buffer and then convert from 16 bit to
897 // 8 bit for the user buffer.
898 //
899 s->prop_adc.fmt_original = s->prop_adc.fmt;
900 if (s->prop_adc.fmt & AFMT_S8) {
901 s->prop_adc.fmt &= ~AFMT_S8;
902 s->prop_adc.fmt |= AFMT_S16_LE;
903 }
904 if (s->prop_adc.fmt & AFMT_U8) {
905 s->prop_adc.fmt &= ~AFMT_U8;
906 s->prop_adc.fmt |= AFMT_U16_LE;
907 }
908 //
909 // prog_dmabuf_adc performs a stop_adc() but that is
910 // ok since we really haven't started the DMA yet.
911 //
912 prog_codec(s, CS_TYPE_ADC);
913
914 prog_dmabuf_adc(s);
915 s->conversion = 1;
916 }
917 spin_lock_irqsave(&s->lock, flags);
918 s->ena |= FMODE_READ;
919 /* Nothing to do really, I am probably already
920 DMAing... XXXKW when do I get here, and is there
921 more I should do? */
922 spin_unlock_irqrestore(&s->lock, flags);
923
924 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
925 "cs4297a: start_adc(): start adc\n"));
926 }
927 CS_DBGOUT(CS_FUNCTION, 2,
928 printk(KERN_INFO "cs4297a: start_adc()-\n"));
929
930 }
931
932
933 // call with spinlock held!
cs4297a_update_ptr(struct cs4297a_state * s,int intflag)934 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
935 {
936 int good_diff, diff, diff2;
937 u64 *data_p, data;
938 u32 *s_ptr;
939 unsigned hwptr;
940 u32 status;
941 serdma_t *d;
942 serdma_descr_t *descr;
943
944 // update ADC pointer
945 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
946
947 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
948 d = &s->dma_adc;
949 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
950 d->descrtab_phys) / sizeof(serdma_descr_t));
951
952 if (s->ena & FMODE_READ) {
953 CS_DBGOUT(CS_FUNCTION, 2,
954 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
955 d->swptr, d->hwptr, hwptr, intflag));
956 /* Number of DMA buffers available for software: */
957 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
958 d->hwptr = hwptr;
959 good_diff = 0;
960 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
961 descr = &d->descrtab[d->swptr];
962 while (diff2--) {
963 u64 data = be64_to_cpu(*(u64 *)s_ptr);
964 u64 descr_a;
965 u16 left, right;
966 descr_a = descr->descr_a;
967 descr->descr_a &= ~M_DMA_SERRX_SOP;
968 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
969 printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
970 }
971 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
972 (!(descr_a & M_DMA_SERRX_SOP)) ||
973 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
974 s->stats.rx_bad++;
975 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
976 continue;
977 }
978 s->stats.rx_good++;
979 if ((data >> 61) == 7) {
980 s->read_value = (data >> 12) & 0xffff;
981 s->read_reg = (data >> 40) & 0x7f;
982 wake_up(&d->reg_wait);
983 }
984 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
985 s->stats.rx_overflow++;
986 printk(KERN_DEBUG "cs4297a: RX overflow\n");
987 continue;
988 }
989 good_diff++;
990 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
991 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
992 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
993 *d->sb_hwptr++ = cpu_to_be16(left);
994 *d->sb_hwptr++ = cpu_to_be16(right);
995 if (d->sb_hwptr == d->sb_end)
996 d->sb_hwptr = d->sample_buf;
997 descr++;
998 if (descr == d->descrtab_end) {
999 descr = d->descrtab;
1000 s_ptr = (u32 *)s->dma_adc.dma_buf;
1001 } else {
1002 s_ptr += 8;
1003 }
1004 }
1005 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
1006 d->count += good_diff * FRAME_SAMPLE_BYTES;
1007 if (d->count > d->sbufsz) {
1008 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
1009 }
1010 d->swptr = (d->swptr + diff) % d->ringsz;
1011 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1012 if (d->mapped) {
1013 if (d->count >= (signed) d->fragsize)
1014 wake_up(&d->wait);
1015 } else {
1016 if (d->count > 0) {
1017 CS_DBGOUT(CS_WAVE_READ, 4,
1018 printk(KERN_INFO
1019 "cs4297a: update count -> %d\n", d->count));
1020 wake_up(&d->wait);
1021 }
1022 }
1023 } else {
1024 /* Receive is going even if no one is
1025 listening (for register accesses and to
1026 avoid FIFO overrun) */
1027 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1028 if (!diff) {
1029 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1030 }
1031
1032 descr = &d->descrtab[d->swptr];
1033 data_p = &d->dma_buf[d->swptr*4];
1034
1035 /* Force this to happen at least once; I got
1036 here because of an interrupt, so there must
1037 be a buffer to process. */
1038 do {
1039 data = be64_to_cpu(*data_p);
1040 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1041 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1042 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1043 (long)CPHYSADDR((long)data_p));
1044 }
1045 if (!(data & (1LL << 63)) ||
1046 !(descr->descr_a & M_DMA_SERRX_SOP) ||
1047 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1048 s->stats.rx_bad++;
1049 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1050 } else {
1051 s->stats.rx_good++;
1052 if ((data >> 61) == 7) {
1053 s->read_value = (data >> 12) & 0xffff;
1054 s->read_reg = (data >> 40) & 0x7f;
1055 wake_up(&d->reg_wait);
1056 }
1057 }
1058 descr->descr_a &= ~M_DMA_SERRX_SOP;
1059 descr++;
1060 d->swptr++;
1061 data_p += 4;
1062 if (descr == d->descrtab_end) {
1063 descr = d->descrtab;
1064 d->swptr = 0;
1065 data_p = d->dma_buf;
1066 }
1067 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1068 } while (--diff);
1069 d->hwptr = hwptr;
1070
1071 CS_DBGOUT(CS_DESCR, 6,
1072 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1073 }
1074
1075 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1076 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1077 (unsigned)s, d->hwptr,
1078 d->total_bytes, d->count));
1079 }
1080
1081 /* XXXKW worry about s->reg_request -- there is a starvation
1082 case if s->ena has FMODE_WRITE on, but the client isn't
1083 doing writes */
1084
1085 // update DAC pointer
1086 //
1087 // check for end of buffer, means that we are going to wait for another interrupt
1088 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1089 //
1090 if (s->ena & FMODE_WRITE) {
1091 serdma_t *d = &s->dma_dac;
1092 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1093 d->descrtab_phys) / sizeof(serdma_descr_t));
1094 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1095 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1096 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1097 d->hwptr, hwptr, d->swptr, diff, d->count));
1098 d->hwptr = hwptr;
1099 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1100 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1101 if (d->mapped) {
1102 d->count += diff * FRAME_SAMPLE_BYTES;
1103 if (d->count >= d->fragsize) {
1104 d->wakeup = 1;
1105 wake_up(&d->wait);
1106 if (d->count > d->sbufsz)
1107 d->count &= d->sbufsz - 1;
1108 }
1109 } else {
1110 d->count -= diff * FRAME_SAMPLE_BYTES;
1111 if (d->count <= 0) {
1112 //
1113 // fill with silence, and do not shut down the DAC.
1114 // Continue to play silence until the _release.
1115 //
1116 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1117 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1118 (unsigned)(s->prop_dac.fmt &
1119 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1120 (unsigned)d->dma_buf,
1121 d->ringsz));
1122 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1123 if (d->count < 0) {
1124 d->underrun = 1;
1125 s->stats.tx_underrun++;
1126 d->count = 0;
1127 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1128 "cs4297a: cs4297a_update_ptr(): underrun\n"));
1129 }
1130 } else if (d->count <=
1131 (signed) d->fragsize
1132 && !d->endcleared) {
1133 /* XXXKW what is this for? */
1134 clear_advance(d->dma_buf,
1135 d->sbufsz,
1136 d->swptr,
1137 d->fragsize,
1138 0);
1139 d->endcleared = 1;
1140 }
1141 if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1142 {
1143 CS_DBGOUT(CS_WAVE_WRITE, 4,
1144 printk(KERN_INFO
1145 "cs4297a: update count -> %d\n", d->count));
1146 wake_up(&d->wait);
1147 }
1148 }
1149 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1150 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1151 (unsigned) s, d->hwptr,
1152 d->total_bytes, d->count));
1153 }
1154 }
1155
mixer_ioctl(struct cs4297a_state * s,unsigned int cmd,unsigned long arg)1156 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1157 unsigned long arg)
1158 {
1159 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1160 // Value of array member is recording source Device ID Mask.
1161 static const unsigned int mixer_src[8] = {
1162 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1163 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1164 };
1165
1166 // Index of mixtable1[] member is Device ID
1167 // and must be <= SOUND_MIXER_NRDEVICES.
1168 // Value of array member is index into s->mix.vol[]
1169 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1170 [SOUND_MIXER_PCM] = 1, // voice
1171 [SOUND_MIXER_LINE1] = 2, // AUX
1172 [SOUND_MIXER_CD] = 3, // CD
1173 [SOUND_MIXER_LINE] = 4, // Line
1174 [SOUND_MIXER_SYNTH] = 5, // FM
1175 [SOUND_MIXER_MIC] = 6, // Mic
1176 [SOUND_MIXER_SPEAKER] = 7, // Speaker
1177 [SOUND_MIXER_RECLEV] = 8, // Recording level
1178 [SOUND_MIXER_VOLUME] = 9 // Master Volume
1179 };
1180
1181 static const unsigned mixreg[] = {
1182 AC97_PCMOUT_VOL,
1183 AC97_AUX_VOL,
1184 AC97_CD_VOL,
1185 AC97_LINEIN_VOL
1186 };
1187 unsigned char l, r, rl, rr, vidx;
1188 unsigned char attentbl[11] =
1189 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1190 unsigned temp1;
1191 int i, val;
1192
1193 VALIDATE_STATE(s);
1194 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1195 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1196 (unsigned) s, cmd));
1197 #if CSDEBUG
1198 cs_printioctl(cmd);
1199 #endif
1200 #if CSDEBUG_INTERFACE
1201
1202 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1203 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1204 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1205 (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1206 {
1207 switch (cmd) {
1208
1209 case SOUND_MIXER_CS_GETDBGMASK:
1210 return put_user(cs_debugmask,
1211 (unsigned long *) arg);
1212
1213 case SOUND_MIXER_CS_GETDBGLEVEL:
1214 return put_user(cs_debuglevel,
1215 (unsigned long *) arg);
1216
1217 case SOUND_MIXER_CS_SETDBGMASK:
1218 if (get_user(val, (unsigned long *) arg))
1219 return -EFAULT;
1220 cs_debugmask = val;
1221 return 0;
1222
1223 case SOUND_MIXER_CS_SETDBGLEVEL:
1224 if (get_user(val, (unsigned long *) arg))
1225 return -EFAULT;
1226 cs_debuglevel = val;
1227 return 0;
1228 default:
1229 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1230 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1231 return 0;
1232 }
1233 }
1234 #endif
1235
1236 if (cmd == SOUND_MIXER_PRIVATE1) {
1237 return -EINVAL;
1238 }
1239 if (cmd == SOUND_MIXER_PRIVATE2) {
1240 // enable/disable/query spatializer
1241 if (get_user(val, (int *) arg))
1242 return -EFAULT;
1243 if (val != -1) {
1244 temp1 = (val & 0x3f) >> 2;
1245 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1246 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1247 &temp1);
1248 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1249 temp1 | 0x2000);
1250 }
1251 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1252 return put_user((temp1 << 2) | 3, (int *) arg);
1253 }
1254 if (cmd == SOUND_MIXER_INFO) {
1255 mixer_info info;
1256 memset(&info, 0, sizeof(info));
1257 strlcpy(info.id, "CS4297a", sizeof(info.id));
1258 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1259 info.modify_counter = s->mix.modcnt;
1260 if (copy_to_user((void *) arg, &info, sizeof(info)))
1261 return -EFAULT;
1262 return 0;
1263 }
1264 if (cmd == SOUND_OLD_MIXER_INFO) {
1265 _old_mixer_info info;
1266 memset(&info, 0, sizeof(info));
1267 strlcpy(info.id, "CS4297a", sizeof(info.id));
1268 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1269 if (copy_to_user((void *) arg, &info, sizeof(info)))
1270 return -EFAULT;
1271 return 0;
1272 }
1273 if (cmd == OSS_GETVERSION)
1274 return put_user(SOUND_VERSION, (int *) arg);
1275
1276 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1277 return -EINVAL;
1278
1279 // If ioctl has only the SIOC_READ bit(bit 31)
1280 // on, process the only-read commands.
1281 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1282 switch (_IOC_NR(cmd)) {
1283 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1284 cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1285 &temp1);
1286 return put_user(mixer_src[temp1 & 7], (int *) arg);
1287
1288 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
1289 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1290 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1291 (int *) arg);
1292
1293 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
1294 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1295 (int *) arg);
1296
1297 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
1298 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1299 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1300 (int *) arg);
1301
1302 case SOUND_MIXER_CAPS:
1303 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1304
1305 default:
1306 i = _IOC_NR(cmd);
1307 if (i >= SOUND_MIXER_NRDEVICES
1308 || !(vidx = mixtable1[i]))
1309 return -EINVAL;
1310 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1311 }
1312 }
1313 // If ioctl doesn't have both the SIOC_READ and
1314 // the SIOC_WRITE bit set, return invalid.
1315 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1316 return -EINVAL;
1317
1318 // Increment the count of volume writes.
1319 s->mix.modcnt++;
1320
1321 // Isolate the command; it must be a write.
1322 switch (_IOC_NR(cmd)) {
1323
1324 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1325 if (get_user(val, (int *) arg))
1326 return -EFAULT;
1327 i = hweight32(val); // i = # bits on in val.
1328 if (i != 1) // One & only 1 bit must be on.
1329 return 0;
1330 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1331 if (val == mixer_src[i]) {
1332 temp1 = (i << 8) | i;
1333 cs4297a_write_ac97(s,
1334 AC97_RECORD_SELECT,
1335 temp1);
1336 return 0;
1337 }
1338 }
1339 return 0;
1340
1341 case SOUND_MIXER_VOLUME:
1342 if (get_user(val, (int *) arg))
1343 return -EFAULT;
1344 l = val & 0xff;
1345 if (l > 100)
1346 l = 100; // Max soundcard.h vol is 100.
1347 if (l < 6) {
1348 rl = 63;
1349 l = 0;
1350 } else
1351 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
1352
1353 r = (val >> 8) & 0xff;
1354 if (r > 100)
1355 r = 100; // Max right volume is 100, too
1356 if (r < 6) {
1357 rr = 63;
1358 r = 0;
1359 } else
1360 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
1361
1362 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
1363 temp1 = 0x8000; // turn on the mute bit.
1364 else
1365 temp1 = 0;
1366
1367 temp1 |= (rl << 8) | rr;
1368
1369 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1370 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1371
1372 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1373 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1374 #else
1375 s->mix.vol[8] = val;
1376 #endif
1377 return put_user(s->mix.vol[8], (int *) arg);
1378
1379 case SOUND_MIXER_SPEAKER:
1380 if (get_user(val, (int *) arg))
1381 return -EFAULT;
1382 l = val & 0xff;
1383 if (l > 100)
1384 l = 100;
1385 if (l < 3) {
1386 rl = 0;
1387 l = 0;
1388 } else {
1389 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
1390 l = (rl * 13 + 5) / 2;
1391 }
1392
1393 if (rl < 3) {
1394 temp1 = 0x8000;
1395 rl = 0;
1396 } else
1397 temp1 = 0;
1398 rl = 15 - rl; // Convert volume to attenuation.
1399 temp1 |= rl << 1;
1400 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1401
1402 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1403 s->mix.vol[6] = l << 8;
1404 #else
1405 s->mix.vol[6] = val;
1406 #endif
1407 return put_user(s->mix.vol[6], (int *) arg);
1408
1409 case SOUND_MIXER_RECLEV:
1410 if (get_user(val, (int *) arg))
1411 return -EFAULT;
1412 l = val & 0xff;
1413 if (l > 100)
1414 l = 100;
1415 r = (val >> 8) & 0xff;
1416 if (r > 100)
1417 r = 100;
1418 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
1419 rr = (r * 2 - 5) / 13;
1420 if (rl < 3 && rr < 3)
1421 temp1 = 0x8000;
1422 else
1423 temp1 = 0;
1424
1425 temp1 = temp1 | (rl << 8) | rr;
1426 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1427
1428 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1429 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1430 #else
1431 s->mix.vol[7] = val;
1432 #endif
1433 return put_user(s->mix.vol[7], (int *) arg);
1434
1435 case SOUND_MIXER_MIC:
1436 if (get_user(val, (int *) arg))
1437 return -EFAULT;
1438 l = val & 0xff;
1439 if (l > 100)
1440 l = 100;
1441 if (l < 1) {
1442 l = 0;
1443 rl = 0;
1444 } else {
1445 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
1446 l = (rl * 16 + 4) / 5;
1447 }
1448 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1449 temp1 &= 0x40; // Isolate 20db gain bit.
1450 if (rl < 3) {
1451 temp1 |= 0x8000;
1452 rl = 0;
1453 }
1454 rl = 31 - rl; // Convert volume to attenuation.
1455 temp1 |= rl;
1456 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1457
1458 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1459 s->mix.vol[5] = val << 8;
1460 #else
1461 s->mix.vol[5] = val;
1462 #endif
1463 return put_user(s->mix.vol[5], (int *) arg);
1464
1465
1466 case SOUND_MIXER_SYNTH:
1467 if (get_user(val, (int *) arg))
1468 return -EFAULT;
1469 l = val & 0xff;
1470 if (l > 100)
1471 l = 100;
1472 if (get_user(val, (int *) arg))
1473 return -EFAULT;
1474 r = (val >> 8) & 0xff;
1475 if (r > 100)
1476 r = 100;
1477 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
1478 rr = (r * 2 - 11) / 3;
1479 if (rl < 3) // If l is low, turn on
1480 temp1 = 0x0080; // the mute bit.
1481 else
1482 temp1 = 0;
1483
1484 rl = 63 - rl; // Convert vol to attenuation.
1485 // writel(temp1 | rl, s->pBA0 + FMLVC);
1486 if (rr < 3) // If rr is low, turn on
1487 temp1 = 0x0080; // the mute bit.
1488 else
1489 temp1 = 0;
1490 rr = 63 - rr; // Convert vol to attenuation.
1491 // writel(temp1 | rr, s->pBA0 + FMRVC);
1492
1493 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1494 s->mix.vol[4] = (r << 8) | l;
1495 #else
1496 s->mix.vol[4] = val;
1497 #endif
1498 return put_user(s->mix.vol[4], (int *) arg);
1499
1500
1501 default:
1502 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1503 "cs4297a: mixer_ioctl(): default\n"));
1504
1505 i = _IOC_NR(cmd);
1506 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1507 return -EINVAL;
1508 if (get_user(val, (int *) arg))
1509 return -EFAULT;
1510 l = val & 0xff;
1511 if (l > 100)
1512 l = 100;
1513 if (l < 1) {
1514 l = 0;
1515 rl = 31;
1516 } else
1517 rl = (attentbl[(l * 10) / 100]) >> 1;
1518
1519 r = (val >> 8) & 0xff;
1520 if (r > 100)
1521 r = 100;
1522 if (r < 1) {
1523 r = 0;
1524 rr = 31;
1525 } else
1526 rr = (attentbl[(r * 10) / 100]) >> 1;
1527 if ((rl > 30) && (rr > 30))
1528 temp1 = 0x8000;
1529 else
1530 temp1 = 0;
1531 temp1 = temp1 | (rl << 8) | rr;
1532 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1533
1534 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1535 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1536 #else
1537 s->mix.vol[vidx - 1] = val;
1538 #endif
1539 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1540 }
1541 }
1542
1543
1544 // ---------------------------------------------------------------------
1545
cs4297a_open_mixdev(struct inode * inode,struct file * file)1546 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1547 {
1548 int minor = iminor(inode);
1549 struct cs4297a_state *s=NULL;
1550 struct list_head *entry;
1551
1552 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1553 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1554
1555 mutex_lock(&swarm_cs4297a_mutex);
1556 list_for_each(entry, &cs4297a_devs)
1557 {
1558 s = list_entry(entry, struct cs4297a_state, list);
1559 if(s->dev_mixer == minor)
1560 break;
1561 }
1562 if (!s)
1563 {
1564 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1565 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1566
1567 mutex_unlock(&swarm_cs4297a_mutex);
1568 return -ENODEV;
1569 }
1570 VALIDATE_STATE(s);
1571 file->private_data = s;
1572
1573 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1574 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1575 mutex_unlock(&swarm_cs4297a_mutex);
1576
1577 return nonseekable_open(inode, file);
1578 }
1579
1580
cs4297a_release_mixdev(struct inode * inode,struct file * file)1581 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1582 {
1583 struct cs4297a_state *s =
1584 (struct cs4297a_state *) file->private_data;
1585
1586 VALIDATE_STATE(s);
1587 return 0;
1588 }
1589
1590
cs4297a_ioctl_mixdev(struct file * file,unsigned int cmd,unsigned long arg)1591 static int cs4297a_ioctl_mixdev(struct file *file,
1592 unsigned int cmd, unsigned long arg)
1593 {
1594 int ret;
1595 mutex_lock(&swarm_cs4297a_mutex);
1596 ret = mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1597 arg);
1598 mutex_unlock(&swarm_cs4297a_mutex);
1599 return ret;
1600 }
1601
1602
1603 // ******************************************************************************************
1604 // Mixer file operations struct.
1605 // ******************************************************************************************
1606 static const struct file_operations cs4297a_mixer_fops = {
1607 .owner = THIS_MODULE,
1608 .llseek = no_llseek,
1609 .unlocked_ioctl = cs4297a_ioctl_mixdev,
1610 .open = cs4297a_open_mixdev,
1611 .release = cs4297a_release_mixdev,
1612 };
1613
1614 // ---------------------------------------------------------------------
1615
1616
drain_adc(struct cs4297a_state * s,int nonblock)1617 static int drain_adc(struct cs4297a_state *s, int nonblock)
1618 {
1619 /* This routine serves no purpose currently - any samples
1620 sitting in the receive queue will just be processed by the
1621 background consumer. This would be different if DMA
1622 actually stopped when there were no clients. */
1623 return 0;
1624 }
1625
drain_dac(struct cs4297a_state * s,int nonblock)1626 static int drain_dac(struct cs4297a_state *s, int nonblock)
1627 {
1628 DECLARE_WAITQUEUE(wait, current);
1629 unsigned long flags;
1630 unsigned hwptr;
1631 unsigned tmo;
1632 int count;
1633
1634 if (s->dma_dac.mapped)
1635 return 0;
1636 if (nonblock)
1637 return -EBUSY;
1638 add_wait_queue(&s->dma_dac.wait, &wait);
1639 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1640 (s->dma_dac.count > 0)) {
1641 if (!signal_pending(current)) {
1642 set_current_state(TASK_INTERRUPTIBLE);
1643 /* XXXKW is this calculation working? */
1644 tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1645 schedule_timeout(tmo + 1);
1646 } else {
1647 /* XXXKW do I care if there is a signal pending? */
1648 }
1649 }
1650 spin_lock_irqsave(&s->lock, flags);
1651 /* Reset the bookkeeping */
1652 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1653 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1654 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1655 spin_unlock_irqrestore(&s->lock, flags);
1656 remove_wait_queue(&s->dma_dac.wait, &wait);
1657 __set_current_state(TASK_RUNNING);
1658 return 0;
1659 }
1660
1661
1662 // ---------------------------------------------------------------------
1663
cs4297a_read(struct file * file,char * buffer,size_t count,loff_t * ppos)1664 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1665 loff_t * ppos)
1666 {
1667 struct cs4297a_state *s =
1668 (struct cs4297a_state *) file->private_data;
1669 ssize_t ret;
1670 unsigned long flags;
1671 int cnt, count_fr, cnt_by;
1672 unsigned copied = 0;
1673
1674 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1675 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1676
1677 VALIDATE_STATE(s);
1678 if (s->dma_adc.mapped)
1679 return -ENXIO;
1680 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1681 return ret;
1682 if (!access_ok(VERIFY_WRITE, buffer, count))
1683 return -EFAULT;
1684 ret = 0;
1685 //
1686 // "count" is the amount of bytes to read (from app), is decremented each loop
1687 // by the amount of bytes that have been returned to the user buffer.
1688 // "cnt" is the running total of each read from the buffer (changes each loop)
1689 // "buffer" points to the app's buffer
1690 // "ret" keeps a running total of the amount of bytes that have been copied
1691 // to the user buffer.
1692 // "copied" is the total bytes copied into the user buffer for each loop.
1693 //
1694 while (count > 0) {
1695 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1696 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1697 count, s->dma_adc.count,
1698 s->dma_adc.swptr, s->dma_adc.hwptr));
1699 spin_lock_irqsave(&s->lock, flags);
1700
1701 /* cnt will be the number of available samples (16-bit
1702 stereo); it starts out as the maxmimum consequetive
1703 samples */
1704 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1705 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1706
1707 // dma_adc.count is the current total bytes that have not been read.
1708 // if the amount of unread bytes from the current sw pointer to the
1709 // end of the buffer is greater than the current total bytes that
1710 // have not been read, then set the "cnt" (unread bytes) to the
1711 // amount of unread bytes.
1712
1713 if (count_fr < cnt)
1714 cnt = count_fr;
1715 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1716 spin_unlock_irqrestore(&s->lock, flags);
1717 //
1718 // if we are converting from 8/16 then we need to copy
1719 // twice the number of 16 bit bytes then 8 bit bytes.
1720 //
1721 if (s->conversion) {
1722 if (cnt_by > (count * 2)) {
1723 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1724 cnt_by = count * 2;
1725 }
1726 } else {
1727 if (cnt_by > count) {
1728 cnt = count / FRAME_SAMPLE_BYTES;
1729 cnt_by = count;
1730 }
1731 }
1732 //
1733 // "cnt" NOW is the smaller of the amount that will be read,
1734 // and the amount that is requested in this read (or partial).
1735 // if there are no bytes in the buffer to read, then start the
1736 // ADC and wait for the interrupt handler to wake us up.
1737 //
1738 if (cnt <= 0) {
1739
1740 // start up the dma engine and then continue back to the top of
1741 // the loop when wake up occurs.
1742 start_adc(s);
1743 if (file->f_flags & O_NONBLOCK)
1744 return ret ? ret : -EAGAIN;
1745 oss_broken_sleep_on(&s->dma_adc.wait, MAX_SCHEDULE_TIMEOUT);
1746 if (signal_pending(current))
1747 return ret ? ret : -ERESTARTSYS;
1748 continue;
1749 }
1750 // there are bytes in the buffer to read.
1751 // copy from the hw buffer over to the user buffer.
1752 // user buffer is designated by "buffer"
1753 // virtual address to copy from is dma_buf+swptr
1754 // the "cnt" is the number of bytes to read.
1755
1756 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1757 "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1758 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1759 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1760 s->dma_adc.sbufsz, s->dma_adc.count,
1761 (unsigned) buffer, ret));
1762
1763 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1764 return ret ? ret : -EFAULT;
1765 copied = cnt_by;
1766
1767 /* Return the descriptors */
1768 spin_lock_irqsave(&s->lock, flags);
1769 CS_DBGOUT(CS_FUNCTION, 2,
1770 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1771 s->dma_adc.count -= cnt_by;
1772 s->dma_adc.sb_swptr += cnt * 2;
1773 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1774 s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1775 spin_unlock_irqrestore(&s->lock, flags);
1776 count -= copied;
1777 buffer += copied;
1778 ret += copied;
1779 start_adc(s);
1780 }
1781 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1782 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1783 return ret;
1784 }
1785
1786
cs4297a_write(struct file * file,const char * buffer,size_t count,loff_t * ppos)1787 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1788 size_t count, loff_t * ppos)
1789 {
1790 struct cs4297a_state *s =
1791 (struct cs4297a_state *) file->private_data;
1792 ssize_t ret;
1793 unsigned long flags;
1794 unsigned swptr, hwptr;
1795 int cnt;
1796
1797 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1798 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1799 count));
1800 VALIDATE_STATE(s);
1801
1802 if (s->dma_dac.mapped)
1803 return -ENXIO;
1804 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1805 return ret;
1806 if (!access_ok(VERIFY_READ, buffer, count))
1807 return -EFAULT;
1808 ret = 0;
1809 while (count > 0) {
1810 serdma_t *d = &s->dma_dac;
1811 int copy_cnt;
1812 u32 *s_tmpl;
1813 u32 *t_tmpl;
1814 u32 left, right;
1815 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1816
1817 /* XXXXXX this is broken for BLOAT_FACTOR */
1818 spin_lock_irqsave(&s->lock, flags);
1819 if (d->count < 0) {
1820 d->count = 0;
1821 d->swptr = d->hwptr;
1822 }
1823 if (d->underrun) {
1824 d->underrun = 0;
1825 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1826 d->descrtab_phys) / sizeof(serdma_descr_t));
1827 d->swptr = d->hwptr = hwptr;
1828 }
1829 swptr = d->swptr;
1830 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1831 /* Will this write fill up the buffer? */
1832 if (d->count + cnt > d->sbufsz)
1833 cnt = d->sbufsz - d->count;
1834 spin_unlock_irqrestore(&s->lock, flags);
1835 if (cnt > count)
1836 cnt = count;
1837 if (cnt <= 0) {
1838 start_dac(s);
1839 if (file->f_flags & O_NONBLOCK)
1840 return ret ? ret : -EAGAIN;
1841 oss_broken_sleep_on(&d->wait, MAX_SCHEDULE_TIMEOUT);
1842 if (signal_pending(current))
1843 return ret ? ret : -ERESTARTSYS;
1844 continue;
1845 }
1846 if (copy_from_user(d->sample_buf, buffer, cnt))
1847 return ret ? ret : -EFAULT;
1848
1849 copy_cnt = cnt;
1850 s_tmpl = (u32 *)d->sample_buf;
1851 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1852
1853 /* XXXKW assuming 16-bit stereo! */
1854 do {
1855 u32 tmp;
1856
1857 t_tmpl[0] = cpu_to_be32(0x98000000);
1858
1859 tmp = be32_to_cpu(s_tmpl[0]);
1860 left = tmp & 0xffff;
1861 right = tmp >> 16;
1862 if (swap) {
1863 left = swab16(left);
1864 right = swab16(right);
1865 }
1866 t_tmpl[1] = cpu_to_be32(left >> 8);
1867 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1868 (right << 4));
1869
1870 s_tmpl++;
1871 t_tmpl += 8;
1872 copy_cnt -= 4;
1873 } while (copy_cnt);
1874
1875 /* Mux in any pending read/write accesses */
1876 if (s->reg_request) {
1877 *(u64 *)(d->dma_buf + (swptr * 4)) |=
1878 cpu_to_be64(s->reg_request);
1879 s->reg_request = 0;
1880 wake_up(&s->dma_dac.reg_wait);
1881 }
1882
1883 CS_DBGOUT(CS_WAVE_WRITE, 4,
1884 printk(KERN_INFO
1885 "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1886
1887 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1888 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1889 spin_lock_irqsave(&s->lock, flags);
1890 d->swptr = swptr;
1891 d->count += cnt;
1892 d->endcleared = 0;
1893 spin_unlock_irqrestore(&s->lock, flags);
1894 count -= cnt;
1895 buffer += cnt;
1896 ret += cnt;
1897 start_dac(s);
1898 }
1899 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1900 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1901 return ret;
1902 }
1903
1904
cs4297a_poll(struct file * file,struct poll_table_struct * wait)1905 static unsigned int cs4297a_poll(struct file *file,
1906 struct poll_table_struct *wait)
1907 {
1908 struct cs4297a_state *s =
1909 (struct cs4297a_state *) file->private_data;
1910 unsigned long flags;
1911 unsigned int mask = 0;
1912
1913 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1914 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1915 VALIDATE_STATE(s);
1916 if (file->f_mode & FMODE_WRITE) {
1917 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1918 printk(KERN_INFO
1919 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1920 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1921 return 0;
1922 poll_wait(file, &s->dma_dac.wait, wait);
1923 }
1924 if (file->f_mode & FMODE_READ) {
1925 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1926 printk(KERN_INFO
1927 "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1928 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1929 return 0;
1930 poll_wait(file, &s->dma_adc.wait, wait);
1931 }
1932 spin_lock_irqsave(&s->lock, flags);
1933 cs4297a_update_ptr(s,CS_FALSE);
1934 if (file->f_mode & FMODE_WRITE) {
1935 if (s->dma_dac.mapped) {
1936 if (s->dma_dac.count >=
1937 (signed) s->dma_dac.fragsize) {
1938 if (s->dma_dac.wakeup)
1939 mask |= POLLOUT | POLLWRNORM;
1940 else
1941 mask = 0;
1942 s->dma_dac.wakeup = 0;
1943 }
1944 } else {
1945 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1946 mask |= POLLOUT | POLLWRNORM;
1947 }
1948 } else if (file->f_mode & FMODE_READ) {
1949 if (s->dma_adc.mapped) {
1950 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1951 mask |= POLLIN | POLLRDNORM;
1952 } else {
1953 if (s->dma_adc.count > 0)
1954 mask |= POLLIN | POLLRDNORM;
1955 }
1956 }
1957 spin_unlock_irqrestore(&s->lock, flags);
1958 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1959 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1960 mask));
1961 return mask;
1962 }
1963
1964
cs4297a_mmap(struct file * file,struct vm_area_struct * vma)1965 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1966 {
1967 /* XXXKW currently no mmap support */
1968 return -EINVAL;
1969 return 0;
1970 }
1971
1972
cs4297a_ioctl(struct file * file,unsigned int cmd,unsigned long arg)1973 static int cs4297a_ioctl(struct file *file,
1974 unsigned int cmd, unsigned long arg)
1975 {
1976 struct cs4297a_state *s =
1977 (struct cs4297a_state *) file->private_data;
1978 unsigned long flags;
1979 audio_buf_info abinfo;
1980 count_info cinfo;
1981 int val, mapped, ret;
1982
1983 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1984 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1985 (unsigned) file, cmd));
1986 #if CSDEBUG
1987 cs_printioctl(cmd);
1988 #endif
1989 VALIDATE_STATE(s);
1990 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1991 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1992 switch (cmd) {
1993 case OSS_GETVERSION:
1994 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1995 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1996 SOUND_VERSION));
1997 return put_user(SOUND_VERSION, (int *) arg);
1998
1999 case SNDCTL_DSP_SYNC:
2000 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2001 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
2002 if (file->f_mode & FMODE_WRITE)
2003 return drain_dac(s,
2004 0 /*file->f_flags & O_NONBLOCK */
2005 );
2006 return 0;
2007
2008 case SNDCTL_DSP_SETDUPLEX:
2009 return 0;
2010
2011 case SNDCTL_DSP_GETCAPS:
2012 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2013 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2014 (int *) arg);
2015
2016 case SNDCTL_DSP_RESET:
2017 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2018 "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
2019 if (file->f_mode & FMODE_WRITE) {
2020 stop_dac(s);
2021 synchronize_irq(s->irq);
2022 s->dma_dac.count = s->dma_dac.total_bytes =
2023 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2024 s->dma_dac.swptr = s->dma_dac.hwptr =
2025 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2026 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2027 }
2028 if (file->f_mode & FMODE_READ) {
2029 stop_adc(s);
2030 synchronize_irq(s->irq);
2031 s->dma_adc.count = s->dma_adc.total_bytes =
2032 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2033 s->dma_adc.swptr = s->dma_adc.hwptr =
2034 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2035 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2036 }
2037 return 0;
2038
2039 case SNDCTL_DSP_SPEED:
2040 if (get_user(val, (int *) arg))
2041 return -EFAULT;
2042 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2043 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2044 val = 48000;
2045 return put_user(val, (int *) arg);
2046
2047 case SNDCTL_DSP_STEREO:
2048 if (get_user(val, (int *) arg))
2049 return -EFAULT;
2050 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2051 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2052 if (file->f_mode & FMODE_READ) {
2053 stop_adc(s);
2054 s->dma_adc.ready = 0;
2055 s->prop_adc.channels = val ? 2 : 1;
2056 }
2057 if (file->f_mode & FMODE_WRITE) {
2058 stop_dac(s);
2059 s->dma_dac.ready = 0;
2060 s->prop_dac.channels = val ? 2 : 1;
2061 }
2062 return 0;
2063
2064 case SNDCTL_DSP_CHANNELS:
2065 if (get_user(val, (int *) arg))
2066 return -EFAULT;
2067 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2068 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2069 val));
2070 if (val != 0) {
2071 if (file->f_mode & FMODE_READ) {
2072 stop_adc(s);
2073 s->dma_adc.ready = 0;
2074 if (val >= 2)
2075 s->prop_adc.channels = 2;
2076 else
2077 s->prop_adc.channels = 1;
2078 }
2079 if (file->f_mode & FMODE_WRITE) {
2080 stop_dac(s);
2081 s->dma_dac.ready = 0;
2082 if (val >= 2)
2083 s->prop_dac.channels = 2;
2084 else
2085 s->prop_dac.channels = 1;
2086 }
2087 }
2088
2089 if (file->f_mode & FMODE_WRITE)
2090 val = s->prop_dac.channels;
2091 else if (file->f_mode & FMODE_READ)
2092 val = s->prop_adc.channels;
2093
2094 return put_user(val, (int *) arg);
2095
2096 case SNDCTL_DSP_GETFMTS: // Returns a mask
2097 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2098 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2099 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2100 AFMT_U8));
2101 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2102 AFMT_U8, (int *) arg);
2103
2104 case SNDCTL_DSP_SETFMT:
2105 if (get_user(val, (int *) arg))
2106 return -EFAULT;
2107 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2108 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2109 val));
2110 if (val != AFMT_QUERY) {
2111 if (file->f_mode & FMODE_READ) {
2112 stop_adc(s);
2113 s->dma_adc.ready = 0;
2114 if (val != AFMT_S16_LE
2115 && val != AFMT_U16_LE && val != AFMT_S8
2116 && val != AFMT_U8)
2117 val = AFMT_U8;
2118 s->prop_adc.fmt = val;
2119 s->prop_adc.fmt_original = s->prop_adc.fmt;
2120 }
2121 if (file->f_mode & FMODE_WRITE) {
2122 stop_dac(s);
2123 s->dma_dac.ready = 0;
2124 if (val != AFMT_S16_LE
2125 && val != AFMT_U16_LE && val != AFMT_S8
2126 && val != AFMT_U8)
2127 val = AFMT_U8;
2128 s->prop_dac.fmt = val;
2129 s->prop_dac.fmt_original = s->prop_dac.fmt;
2130 }
2131 } else {
2132 if (file->f_mode & FMODE_WRITE)
2133 val = s->prop_dac.fmt_original;
2134 else if (file->f_mode & FMODE_READ)
2135 val = s->prop_adc.fmt_original;
2136 }
2137 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2138 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2139 val));
2140 return put_user(val, (int *) arg);
2141
2142 case SNDCTL_DSP_POST:
2143 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2144 "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2145 return 0;
2146
2147 case SNDCTL_DSP_GETTRIGGER:
2148 val = 0;
2149 if (file->f_mode & s->ena & FMODE_READ)
2150 val |= PCM_ENABLE_INPUT;
2151 if (file->f_mode & s->ena & FMODE_WRITE)
2152 val |= PCM_ENABLE_OUTPUT;
2153 return put_user(val, (int *) arg);
2154
2155 case SNDCTL_DSP_SETTRIGGER:
2156 if (get_user(val, (int *) arg))
2157 return -EFAULT;
2158 if (file->f_mode & FMODE_READ) {
2159 if (val & PCM_ENABLE_INPUT) {
2160 if (!s->dma_adc.ready
2161 && (ret = prog_dmabuf_adc(s)))
2162 return ret;
2163 start_adc(s);
2164 } else
2165 stop_adc(s);
2166 }
2167 if (file->f_mode & FMODE_WRITE) {
2168 if (val & PCM_ENABLE_OUTPUT) {
2169 if (!s->dma_dac.ready
2170 && (ret = prog_dmabuf_dac(s)))
2171 return ret;
2172 start_dac(s);
2173 } else
2174 stop_dac(s);
2175 }
2176 return 0;
2177
2178 case SNDCTL_DSP_GETOSPACE:
2179 if (!(file->f_mode & FMODE_WRITE))
2180 return -EINVAL;
2181 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2182 return val;
2183 spin_lock_irqsave(&s->lock, flags);
2184 cs4297a_update_ptr(s,CS_FALSE);
2185 abinfo.fragsize = s->dma_dac.fragsize;
2186 if (s->dma_dac.mapped)
2187 abinfo.bytes = s->dma_dac.sbufsz;
2188 else
2189 abinfo.bytes =
2190 s->dma_dac.sbufsz - s->dma_dac.count;
2191 abinfo.fragstotal = s->dma_dac.numfrag;
2192 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2193 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2194 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2195 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2196 abinfo.fragments));
2197 spin_unlock_irqrestore(&s->lock, flags);
2198 return copy_to_user((void *) arg, &abinfo,
2199 sizeof(abinfo)) ? -EFAULT : 0;
2200
2201 case SNDCTL_DSP_GETISPACE:
2202 if (!(file->f_mode & FMODE_READ))
2203 return -EINVAL;
2204 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2205 return val;
2206 spin_lock_irqsave(&s->lock, flags);
2207 cs4297a_update_ptr(s,CS_FALSE);
2208 if (s->conversion) {
2209 abinfo.fragsize = s->dma_adc.fragsize / 2;
2210 abinfo.bytes = s->dma_adc.count / 2;
2211 abinfo.fragstotal = s->dma_adc.numfrag;
2212 abinfo.fragments =
2213 abinfo.bytes >> (s->dma_adc.fragshift - 1);
2214 } else {
2215 abinfo.fragsize = s->dma_adc.fragsize;
2216 abinfo.bytes = s->dma_adc.count;
2217 abinfo.fragstotal = s->dma_adc.numfrag;
2218 abinfo.fragments =
2219 abinfo.bytes >> s->dma_adc.fragshift;
2220 }
2221 spin_unlock_irqrestore(&s->lock, flags);
2222 return copy_to_user((void *) arg, &abinfo,
2223 sizeof(abinfo)) ? -EFAULT : 0;
2224
2225 case SNDCTL_DSP_NONBLOCK:
2226 spin_lock(&file->f_lock);
2227 file->f_flags |= O_NONBLOCK;
2228 spin_unlock(&file->f_lock);
2229 return 0;
2230
2231 case SNDCTL_DSP_GETODELAY:
2232 if (!(file->f_mode & FMODE_WRITE))
2233 return -EINVAL;
2234 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2235 return 0;
2236 spin_lock_irqsave(&s->lock, flags);
2237 cs4297a_update_ptr(s,CS_FALSE);
2238 val = s->dma_dac.count;
2239 spin_unlock_irqrestore(&s->lock, flags);
2240 return put_user(val, (int *) arg);
2241
2242 case SNDCTL_DSP_GETIPTR:
2243 if (!(file->f_mode & FMODE_READ))
2244 return -EINVAL;
2245 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2246 return 0;
2247 spin_lock_irqsave(&s->lock, flags);
2248 cs4297a_update_ptr(s,CS_FALSE);
2249 cinfo.bytes = s->dma_adc.total_bytes;
2250 if (s->dma_adc.mapped) {
2251 cinfo.blocks =
2252 (cinfo.bytes >> s->dma_adc.fragshift) -
2253 s->dma_adc.blocks;
2254 s->dma_adc.blocks =
2255 cinfo.bytes >> s->dma_adc.fragshift;
2256 } else {
2257 if (s->conversion) {
2258 cinfo.blocks =
2259 s->dma_adc.count /
2260 2 >> (s->dma_adc.fragshift - 1);
2261 } else
2262 cinfo.blocks =
2263 s->dma_adc.count >> s->dma_adc.
2264 fragshift;
2265 }
2266 if (s->conversion)
2267 cinfo.ptr = s->dma_adc.hwptr / 2;
2268 else
2269 cinfo.ptr = s->dma_adc.hwptr;
2270 if (s->dma_adc.mapped)
2271 s->dma_adc.count &= s->dma_adc.fragsize - 1;
2272 spin_unlock_irqrestore(&s->lock, flags);
2273 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2274
2275 case SNDCTL_DSP_GETOPTR:
2276 if (!(file->f_mode & FMODE_WRITE))
2277 return -EINVAL;
2278 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2279 return 0;
2280 spin_lock_irqsave(&s->lock, flags);
2281 cs4297a_update_ptr(s,CS_FALSE);
2282 cinfo.bytes = s->dma_dac.total_bytes;
2283 if (s->dma_dac.mapped) {
2284 cinfo.blocks =
2285 (cinfo.bytes >> s->dma_dac.fragshift) -
2286 s->dma_dac.blocks;
2287 s->dma_dac.blocks =
2288 cinfo.bytes >> s->dma_dac.fragshift;
2289 } else {
2290 cinfo.blocks =
2291 s->dma_dac.count >> s->dma_dac.fragshift;
2292 }
2293 cinfo.ptr = s->dma_dac.hwptr;
2294 if (s->dma_dac.mapped)
2295 s->dma_dac.count &= s->dma_dac.fragsize - 1;
2296 spin_unlock_irqrestore(&s->lock, flags);
2297 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2298
2299 case SNDCTL_DSP_GETBLKSIZE:
2300 if (file->f_mode & FMODE_WRITE) {
2301 if ((val = prog_dmabuf_dac(s)))
2302 return val;
2303 return put_user(s->dma_dac.fragsize, (int *) arg);
2304 }
2305 if ((val = prog_dmabuf_adc(s)))
2306 return val;
2307 if (s->conversion)
2308 return put_user(s->dma_adc.fragsize / 2,
2309 (int *) arg);
2310 else
2311 return put_user(s->dma_adc.fragsize, (int *) arg);
2312
2313 case SNDCTL_DSP_SETFRAGMENT:
2314 if (get_user(val, (int *) arg))
2315 return -EFAULT;
2316 return 0; // Say OK, but do nothing.
2317
2318 case SNDCTL_DSP_SUBDIVIDE:
2319 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2320 || (file->f_mode & FMODE_WRITE
2321 && s->dma_dac.subdivision)) return -EINVAL;
2322 if (get_user(val, (int *) arg))
2323 return -EFAULT;
2324 if (val != 1 && val != 2 && val != 4)
2325 return -EINVAL;
2326 if (file->f_mode & FMODE_READ)
2327 s->dma_adc.subdivision = val;
2328 else if (file->f_mode & FMODE_WRITE)
2329 s->dma_dac.subdivision = val;
2330 return 0;
2331
2332 case SOUND_PCM_READ_RATE:
2333 if (file->f_mode & FMODE_READ)
2334 return put_user(s->prop_adc.rate, (int *) arg);
2335 else if (file->f_mode & FMODE_WRITE)
2336 return put_user(s->prop_dac.rate, (int *) arg);
2337
2338 case SOUND_PCM_READ_CHANNELS:
2339 if (file->f_mode & FMODE_READ)
2340 return put_user(s->prop_adc.channels, (int *) arg);
2341 else if (file->f_mode & FMODE_WRITE)
2342 return put_user(s->prop_dac.channels, (int *) arg);
2343
2344 case SOUND_PCM_READ_BITS:
2345 if (file->f_mode & FMODE_READ)
2346 return
2347 put_user(
2348 (s->prop_adc.
2349 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2350 (int *) arg);
2351 else if (file->f_mode & FMODE_WRITE)
2352 return
2353 put_user(
2354 (s->prop_dac.
2355 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2356 (int *) arg);
2357
2358 case SOUND_PCM_WRITE_FILTER:
2359 case SNDCTL_DSP_SETSYNCRO:
2360 case SOUND_PCM_READ_FILTER:
2361 return -EINVAL;
2362 }
2363 return mixer_ioctl(s, cmd, arg);
2364 }
2365
cs4297a_unlocked_ioctl(struct file * file,u_int cmd,u_long arg)2366 static long cs4297a_unlocked_ioctl(struct file *file, u_int cmd, u_long arg)
2367 {
2368 int ret;
2369
2370 mutex_lock(&swarm_cs4297a_mutex);
2371 ret = cs4297a_ioctl(file, cmd, arg);
2372 mutex_unlock(&swarm_cs4297a_mutex);
2373
2374 return ret;
2375 }
2376
cs4297a_release(struct inode * inode,struct file * file)2377 static int cs4297a_release(struct inode *inode, struct file *file)
2378 {
2379 struct cs4297a_state *s =
2380 (struct cs4297a_state *) file->private_data;
2381
2382 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2383 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2384 (unsigned) inode, (unsigned) file, file->f_mode));
2385 VALIDATE_STATE(s);
2386
2387 if (file->f_mode & FMODE_WRITE) {
2388 drain_dac(s, file->f_flags & O_NONBLOCK);
2389 mutex_lock(&s->open_sem_dac);
2390 stop_dac(s);
2391 dealloc_dmabuf(s, &s->dma_dac);
2392 s->open_mode &= ~FMODE_WRITE;
2393 mutex_unlock(&s->open_sem_dac);
2394 wake_up(&s->open_wait_dac);
2395 }
2396 if (file->f_mode & FMODE_READ) {
2397 drain_adc(s, file->f_flags & O_NONBLOCK);
2398 mutex_lock(&s->open_sem_adc);
2399 stop_adc(s);
2400 dealloc_dmabuf(s, &s->dma_adc);
2401 s->open_mode &= ~FMODE_READ;
2402 mutex_unlock(&s->open_sem_adc);
2403 wake_up(&s->open_wait_adc);
2404 }
2405 return 0;
2406 }
2407
cs4297a_locked_open(struct inode * inode,struct file * file)2408 static int cs4297a_locked_open(struct inode *inode, struct file *file)
2409 {
2410 int minor = iminor(inode);
2411 struct cs4297a_state *s=NULL;
2412 struct list_head *entry;
2413
2414 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2415 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2416 (unsigned) inode, (unsigned) file, file->f_mode));
2417 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2418 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2419
2420 list_for_each(entry, &cs4297a_devs)
2421 {
2422 s = list_entry(entry, struct cs4297a_state, list);
2423
2424 if (!((s->dev_audio ^ minor) & ~0xf))
2425 break;
2426 }
2427 if (entry == &cs4297a_devs)
2428 return -ENODEV;
2429 if (!s) {
2430 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2431 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2432 return -ENODEV;
2433 }
2434 VALIDATE_STATE(s);
2435 file->private_data = s;
2436
2437 // wait for device to become free
2438 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2439 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2440 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2441 return -ENODEV;
2442 }
2443 if (file->f_mode & FMODE_WRITE) {
2444 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2445 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2446 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2447 ;
2448 }
2449
2450 mutex_lock(&s->open_sem_dac);
2451 while (s->open_mode & FMODE_WRITE) {
2452 if (file->f_flags & O_NONBLOCK) {
2453 mutex_unlock(&s->open_sem_dac);
2454 return -EBUSY;
2455 }
2456 mutex_unlock(&s->open_sem_dac);
2457 oss_broken_sleep_on(&s->open_wait_dac, MAX_SCHEDULE_TIMEOUT);
2458
2459 if (signal_pending(current)) {
2460 printk("open - sig pending\n");
2461 return -ERESTARTSYS;
2462 }
2463 mutex_lock(&s->open_sem_dac);
2464 }
2465 }
2466 if (file->f_mode & FMODE_READ) {
2467 mutex_lock(&s->open_sem_adc);
2468 while (s->open_mode & FMODE_READ) {
2469 if (file->f_flags & O_NONBLOCK) {
2470 mutex_unlock(&s->open_sem_adc);
2471 return -EBUSY;
2472 }
2473 mutex_unlock(&s->open_sem_adc);
2474 oss_broken_sleep_on(&s->open_wait_adc, MAX_SCHEDULE_TIMEOUT);
2475
2476 if (signal_pending(current)) {
2477 printk("open - sig pending\n");
2478 return -ERESTARTSYS;
2479 }
2480 mutex_lock(&s->open_sem_adc);
2481 }
2482 }
2483 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2484 if (file->f_mode & FMODE_READ) {
2485 s->prop_adc.fmt = AFMT_S16_BE;
2486 s->prop_adc.fmt_original = s->prop_adc.fmt;
2487 s->prop_adc.channels = 2;
2488 s->prop_adc.rate = 48000;
2489 s->conversion = 0;
2490 s->ena &= ~FMODE_READ;
2491 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2492 s->dma_adc.subdivision = 0;
2493 mutex_unlock(&s->open_sem_adc);
2494
2495 if (prog_dmabuf_adc(s)) {
2496 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2497 "cs4297a: adc Program dmabufs failed.\n"));
2498 cs4297a_release(inode, file);
2499 return -ENOMEM;
2500 }
2501 }
2502 if (file->f_mode & FMODE_WRITE) {
2503 s->prop_dac.fmt = AFMT_S16_BE;
2504 s->prop_dac.fmt_original = s->prop_dac.fmt;
2505 s->prop_dac.channels = 2;
2506 s->prop_dac.rate = 48000;
2507 s->conversion = 0;
2508 s->ena &= ~FMODE_WRITE;
2509 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2510 s->dma_dac.subdivision = 0;
2511 mutex_unlock(&s->open_sem_dac);
2512
2513 if (prog_dmabuf_dac(s)) {
2514 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2515 "cs4297a: dac Program dmabufs failed.\n"));
2516 cs4297a_release(inode, file);
2517 return -ENOMEM;
2518 }
2519 }
2520 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2521 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2522 return nonseekable_open(inode, file);
2523 }
2524
cs4297a_open(struct inode * inode,struct file * file)2525 static int cs4297a_open(struct inode *inode, struct file *file)
2526 {
2527 int ret;
2528
2529 mutex_lock(&swarm_cs4297a_mutex);
2530 ret = cs4297a_open(inode, file);
2531 mutex_unlock(&swarm_cs4297a_mutex);
2532
2533 return ret;
2534 }
2535
2536 // ******************************************************************************************
2537 // Wave (audio) file operations struct.
2538 // ******************************************************************************************
2539 static const struct file_operations cs4297a_audio_fops = {
2540 .owner = THIS_MODULE,
2541 .llseek = no_llseek,
2542 .read = cs4297a_read,
2543 .write = cs4297a_write,
2544 .poll = cs4297a_poll,
2545 .unlocked_ioctl = cs4297a_unlocked_ioctl,
2546 .mmap = cs4297a_mmap,
2547 .open = cs4297a_open,
2548 .release = cs4297a_release,
2549 };
2550
cs4297a_interrupt(int irq,void * dev_id)2551 static void cs4297a_interrupt(int irq, void *dev_id)
2552 {
2553 struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2554 u32 status;
2555
2556 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2557
2558 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2559 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2560
2561 #if 0
2562 /* XXXKW what check *should* be done here? */
2563 if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2564 status = __raw_readq(SS_CSR(R_SER_STATUS));
2565 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2566 return;
2567 }
2568 #endif
2569
2570 if (status & M_SYNCSER_RX_SYNC_ERR) {
2571 status = __raw_readq(SS_CSR(R_SER_STATUS));
2572 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2573 return;
2574 }
2575
2576 if (status & M_SYNCSER_RX_OVERRUN) {
2577 int newptr, i;
2578 s->stats.rx_ovrrn++;
2579 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2580
2581 /* Fix things up: get the receive descriptor pool
2582 clean and give them back to the hardware */
2583 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2584 ;
2585 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2586 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2587 for (i=0; i<DMA_DESCR; i++) {
2588 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2589 }
2590 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2591 s->dma_adc.count = 0;
2592 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2593 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2594 }
2595
2596 spin_lock(&s->lock);
2597 cs4297a_update_ptr(s,CS_TRUE);
2598 spin_unlock(&s->lock);
2599
2600 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2601 "cs4297a: cs4297a_interrupt()-\n"));
2602 }
2603
2604 #if 0
2605 static struct initvol {
2606 int mixch;
2607 int vol;
2608 } initvol[] __initdata = {
2609
2610 {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2611 {SOUND_MIXER_WRITE_PCM, 0x4040},
2612 {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2613 {SOUND_MIXER_WRITE_CD, 0x4040},
2614 {SOUND_MIXER_WRITE_LINE, 0x4040},
2615 {SOUND_MIXER_WRITE_LINE1, 0x4040},
2616 {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2617 {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2618 {SOUND_MIXER_WRITE_MIC, 0x0000}
2619 };
2620 #endif
2621
cs4297a_init(void)2622 static int __init cs4297a_init(void)
2623 {
2624 struct cs4297a_state *s;
2625 u32 pwr, id;
2626 mm_segment_t fs;
2627 int rval;
2628 u64 cfg;
2629 int mdio_val;
2630
2631 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2632 "cs4297a: cs4297a_init_module()+ \n"));
2633
2634 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2635 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2636
2637 /* Check syscfg for synchronous serial on port 1 */
2638 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2639 if (!(cfg & M_SYS_SER1_ENABLE)) {
2640 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2641 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2642 if (!(cfg & M_SYS_SER1_ENABLE)) {
2643 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2644 return -1;
2645 }
2646
2647 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2648
2649 /* Force the codec (on SWARM) to reset by clearing
2650 GENO, preserving MDIO (no effect on CSWARM) */
2651 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2652 udelay(10);
2653 }
2654
2655 /* Now set GENO */
2656 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2657 /* Give the codec some time to finish resetting (start the bit clock) */
2658 udelay(100);
2659
2660 if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2661 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2662 "cs4297a: probe() no memory for state struct.\n"));
2663 return -1;
2664 }
2665 s->magic = CS4297a_MAGIC;
2666 init_waitqueue_head(&s->dma_adc.wait);
2667 init_waitqueue_head(&s->dma_dac.wait);
2668 init_waitqueue_head(&s->dma_adc.reg_wait);
2669 init_waitqueue_head(&s->dma_dac.reg_wait);
2670 init_waitqueue_head(&s->open_wait);
2671 init_waitqueue_head(&s->open_wait_adc);
2672 init_waitqueue_head(&s->open_wait_dac);
2673 mutex_init(&s->open_sem_adc);
2674 mutex_init(&s->open_sem_dac);
2675 spin_lock_init(&s->lock);
2676
2677 s->irq = K_INT_SER_1;
2678
2679 if (request_irq
2680 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2681 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2682 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2683 goto err_irq;
2684 }
2685 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2686 0) {
2687 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2688 "cs4297a: probe() register_sound_dsp() failed.\n"));
2689 goto err_dev1;
2690 }
2691 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2692 0) {
2693 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2694 "cs4297a: probe() register_sound_mixer() failed.\n"));
2695 goto err_dev2;
2696 }
2697
2698 if (ser_init(s) || dma_init(s)) {
2699 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2700 "cs4297a: ser_init failed.\n"));
2701 goto err_dev3;
2702 }
2703
2704 do {
2705 udelay(4000);
2706 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2707 } while (!rval && (pwr != 0xf));
2708
2709 if (!rval) {
2710 char *sb1250_duart_present;
2711
2712 fs = get_fs();
2713 set_fs(KERNEL_DS);
2714 #if 0
2715 val = SOUND_MASK_LINE;
2716 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2717 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
2718 val = initvol[i].vol;
2719 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2720 }
2721 // cs4297a_write_ac97(s, 0x18, 0x0808);
2722 #else
2723 // cs4297a_write_ac97(s, 0x5e, 0x180);
2724 cs4297a_write_ac97(s, 0x02, 0x0808);
2725 cs4297a_write_ac97(s, 0x18, 0x0808);
2726 #endif
2727 set_fs(fs);
2728
2729 list_add(&s->list, &cs4297a_devs);
2730
2731 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2732
2733 sb1250_duart_present = symbol_get(sb1250_duart_present);
2734 if (sb1250_duart_present)
2735 sb1250_duart_present[1] = 0;
2736
2737 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2738
2739 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2740 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2741
2742 return 0;
2743 }
2744
2745 err_dev3:
2746 unregister_sound_mixer(s->dev_mixer);
2747 err_dev2:
2748 unregister_sound_dsp(s->dev_audio);
2749 err_dev1:
2750 free_irq(s->irq, s);
2751 err_irq:
2752 kfree(s);
2753
2754 printk(KERN_INFO "cs4297a: initialization failed\n");
2755
2756 return -1;
2757 }
2758
cs4297a_cleanup(void)2759 static void __exit cs4297a_cleanup(void)
2760 {
2761 /*
2762 XXXKW
2763 disable_irq, free_irq
2764 drain DMA queue
2765 disable DMA
2766 disable TX/RX
2767 free memory
2768 */
2769 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2770 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2771 }
2772
2773 // ---------------------------------------------------------------------
2774
2775 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2776 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2777
2778 // ---------------------------------------------------------------------
2779
2780 module_init(cs4297a_init);
2781 module_exit(cs4297a_cleanup);
2782