1 /*
2 * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 SoC
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether
9 * express or implied.
10 */
11
12 #ifndef _MPC8610_I2S_H
13 #define _MPC8610_I2S_H
14
15 /* SSI registers */
16 #define CCSR_SSI_STX0 0x00
17 #define CCSR_SSI_STX1 0x04
18 #define CCSR_SSI_SRX0 0x08
19 #define CCSR_SSI_SRX1 0x0c
20 #define CCSR_SSI_SCR 0x10
21 #define CCSR_SSI_SISR 0x14
22 #define CCSR_SSI_SIER 0x18
23 #define CCSR_SSI_STCR 0x1c
24 #define CCSR_SSI_SRCR 0x20
25 #define CCSR_SSI_STCCR 0x24
26 #define CCSR_SSI_SRCCR 0x28
27 #define CCSR_SSI_SFCSR 0x2c
28 #define CCSR_SSI_STR 0x30
29 #define CCSR_SSI_SOR 0x34
30 #define CCSR_SSI_SACNT 0x38
31 #define CCSR_SSI_SACADD 0x3c
32 #define CCSR_SSI_SACDAT 0x40
33 #define CCSR_SSI_SATAG 0x44
34 #define CCSR_SSI_STMSK 0x48
35 #define CCSR_SSI_SRMSK 0x4c
36 #define CCSR_SSI_SACCST 0x50
37 #define CCSR_SSI_SACCEN 0x54
38 #define CCSR_SSI_SACCDIS 0x58
39
40 #define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000
41 #define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
42 #define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
43 #define CCSR_SSI_SCR_TCH_EN 0x00000100
44 #define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080
45 #define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060
46 #define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000
47 #define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020
48 #define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040
49 #define CCSR_SSI_SCR_SYN 0x00000010
50 #define CCSR_SSI_SCR_NET 0x00000008
51 #define CCSR_SSI_SCR_RE 0x00000004
52 #define CCSR_SSI_SCR_TE 0x00000002
53 #define CCSR_SSI_SCR_SSIEN 0x00000001
54
55 #define CCSR_SSI_SISR_RFRC 0x01000000
56 #define CCSR_SSI_SISR_TFRC 0x00800000
57 #define CCSR_SSI_SISR_CMDAU 0x00040000
58 #define CCSR_SSI_SISR_CMDDU 0x00020000
59 #define CCSR_SSI_SISR_RXT 0x00010000
60 #define CCSR_SSI_SISR_RDR1 0x00008000
61 #define CCSR_SSI_SISR_RDR0 0x00004000
62 #define CCSR_SSI_SISR_TDE1 0x00002000
63 #define CCSR_SSI_SISR_TDE0 0x00001000
64 #define CCSR_SSI_SISR_ROE1 0x00000800
65 #define CCSR_SSI_SISR_ROE0 0x00000400
66 #define CCSR_SSI_SISR_TUE1 0x00000200
67 #define CCSR_SSI_SISR_TUE0 0x00000100
68 #define CCSR_SSI_SISR_TFS 0x00000080
69 #define CCSR_SSI_SISR_RFS 0x00000040
70 #define CCSR_SSI_SISR_TLS 0x00000020
71 #define CCSR_SSI_SISR_RLS 0x00000010
72 #define CCSR_SSI_SISR_RFF1 0x00000008
73 #define CCSR_SSI_SISR_RFF0 0x00000004
74 #define CCSR_SSI_SISR_TFE1 0x00000002
75 #define CCSR_SSI_SISR_TFE0 0x00000001
76
77 #define CCSR_SSI_SIER_RFRC_EN 0x01000000
78 #define CCSR_SSI_SIER_TFRC_EN 0x00800000
79 #define CCSR_SSI_SIER_RDMAE 0x00400000
80 #define CCSR_SSI_SIER_RIE 0x00200000
81 #define CCSR_SSI_SIER_TDMAE 0x00100000
82 #define CCSR_SSI_SIER_TIE 0x00080000
83 #define CCSR_SSI_SIER_CMDAU_EN 0x00040000
84 #define CCSR_SSI_SIER_CMDDU_EN 0x00020000
85 #define CCSR_SSI_SIER_RXT_EN 0x00010000
86 #define CCSR_SSI_SIER_RDR1_EN 0x00008000
87 #define CCSR_SSI_SIER_RDR0_EN 0x00004000
88 #define CCSR_SSI_SIER_TDE1_EN 0x00002000
89 #define CCSR_SSI_SIER_TDE0_EN 0x00001000
90 #define CCSR_SSI_SIER_ROE1_EN 0x00000800
91 #define CCSR_SSI_SIER_ROE0_EN 0x00000400
92 #define CCSR_SSI_SIER_TUE1_EN 0x00000200
93 #define CCSR_SSI_SIER_TUE0_EN 0x00000100
94 #define CCSR_SSI_SIER_TFS_EN 0x00000080
95 #define CCSR_SSI_SIER_RFS_EN 0x00000040
96 #define CCSR_SSI_SIER_TLS_EN 0x00000020
97 #define CCSR_SSI_SIER_RLS_EN 0x00000010
98 #define CCSR_SSI_SIER_RFF1_EN 0x00000008
99 #define CCSR_SSI_SIER_RFF0_EN 0x00000004
100 #define CCSR_SSI_SIER_TFE1_EN 0x00000002
101 #define CCSR_SSI_SIER_TFE0_EN 0x00000001
102
103 #define CCSR_SSI_STCR_TXBIT0 0x00000200
104 #define CCSR_SSI_STCR_TFEN1 0x00000100
105 #define CCSR_SSI_STCR_TFEN0 0x00000080
106 #define CCSR_SSI_STCR_TFDIR 0x00000040
107 #define CCSR_SSI_STCR_TXDIR 0x00000020
108 #define CCSR_SSI_STCR_TSHFD 0x00000010
109 #define CCSR_SSI_STCR_TSCKP 0x00000008
110 #define CCSR_SSI_STCR_TFSI 0x00000004
111 #define CCSR_SSI_STCR_TFSL 0x00000002
112 #define CCSR_SSI_STCR_TEFS 0x00000001
113
114 #define CCSR_SSI_SRCR_RXEXT 0x00000400
115 #define CCSR_SSI_SRCR_RXBIT0 0x00000200
116 #define CCSR_SSI_SRCR_RFEN1 0x00000100
117 #define CCSR_SSI_SRCR_RFEN0 0x00000080
118 #define CCSR_SSI_SRCR_RFDIR 0x00000040
119 #define CCSR_SSI_SRCR_RXDIR 0x00000020
120 #define CCSR_SSI_SRCR_RSHFD 0x00000010
121 #define CCSR_SSI_SRCR_RSCKP 0x00000008
122 #define CCSR_SSI_SRCR_RFSI 0x00000004
123 #define CCSR_SSI_SRCR_RFSL 0x00000002
124 #define CCSR_SSI_SRCR_REFS 0x00000001
125
126 /* STCCR and SRCCR */
127 #define CCSR_SSI_SxCCR_DIV2_SHIFT 18
128 #define CCSR_SSI_SxCCR_DIV2 0x00040000
129 #define CCSR_SSI_SxCCR_PSR_SHIFT 17
130 #define CCSR_SSI_SxCCR_PSR 0x00020000
131 #define CCSR_SSI_SxCCR_WL_SHIFT 13
132 #define CCSR_SSI_SxCCR_WL_MASK 0x0001E000
133 #define CCSR_SSI_SxCCR_WL(x) \
134 (((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK)
135 #define CCSR_SSI_SxCCR_DC_SHIFT 8
136 #define CCSR_SSI_SxCCR_DC_MASK 0x00001F00
137 #define CCSR_SSI_SxCCR_DC(x) \
138 ((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK)
139 #define CCSR_SSI_SxCCR_PM_SHIFT 0
140 #define CCSR_SSI_SxCCR_PM_MASK 0x000000FF
141 #define CCSR_SSI_SxCCR_PM(x) \
142 ((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK)
143
144 /*
145 * The xFCNT bits are read-only, and the xFWM bits are read/write. Use the
146 * CCSR_SSI_SFCSR_xFCNTy() macros to read the FIFO counters, and use the
147 * CCSR_SSI_SFCSR_xFWMy() macros to set the watermarks.
148 */
149 #define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28
150 #define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000
151 #define CCSR_SSI_SFCSR_RFCNT1(x) \
152 (((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT)
153 #define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24
154 #define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000
155 #define CCSR_SSI_SFCSR_TFCNT1(x) \
156 (((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT)
157 #define CCSR_SSI_SFCSR_RFWM1_SHIFT 20
158 #define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000
159 #define CCSR_SSI_SFCSR_RFWM1(x) \
160 (((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK)
161 #define CCSR_SSI_SFCSR_TFWM1_SHIFT 16
162 #define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000
163 #define CCSR_SSI_SFCSR_TFWM1(x) \
164 (((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK)
165 #define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12
166 #define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000
167 #define CCSR_SSI_SFCSR_RFCNT0(x) \
168 (((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT)
169 #define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8
170 #define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00
171 #define CCSR_SSI_SFCSR_TFCNT0(x) \
172 (((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT)
173 #define CCSR_SSI_SFCSR_RFWM0_SHIFT 4
174 #define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0
175 #define CCSR_SSI_SFCSR_RFWM0(x) \
176 (((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK)
177 #define CCSR_SSI_SFCSR_TFWM0_SHIFT 0
178 #define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F
179 #define CCSR_SSI_SFCSR_TFWM0(x) \
180 (((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK)
181
182 #define CCSR_SSI_STR_TEST 0x00008000
183 #define CCSR_SSI_STR_RCK2TCK 0x00004000
184 #define CCSR_SSI_STR_RFS2TFS 0x00002000
185 #define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
186 #define CCSR_SSI_STR_TXD2RXD 0x00000080
187 #define CCSR_SSI_STR_TCK2RCK 0x00000040
188 #define CCSR_SSI_STR_TFS2RFS 0x00000020
189 #define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F)
190
191 #define CCSR_SSI_SOR_CLKOFF 0x00000040
192 #define CCSR_SSI_SOR_RX_CLR 0x00000020
193 #define CCSR_SSI_SOR_TX_CLR 0x00000010
194 #define CCSR_SSI_SOR_INIT 0x00000008
195 #define CCSR_SSI_SOR_WAIT_SHIFT 1
196 #define CCSR_SSI_SOR_WAIT_MASK 0x00000006
197 #define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT)
198 #define CCSR_SSI_SOR_SYNRST 0x00000001
199
200 #define CCSR_SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
201 #define CCSR_SSI_SACNT_WR 0x00000010
202 #define CCSR_SSI_SACNT_RD 0x00000008
203 #define CCSR_SSI_SACNT_RDWR_MASK 0x00000018
204 #define CCSR_SSI_SACNT_TIF 0x00000004
205 #define CCSR_SSI_SACNT_FV 0x00000002
206 #define CCSR_SSI_SACNT_AC97EN 0x00000001
207
208
209 struct device;
210
211 #if IS_ENABLED(CONFIG_DEBUG_FS)
212
213 struct fsl_ssi_dbg {
214 struct dentry *dbg_dir;
215 struct dentry *dbg_stats;
216
217 struct {
218 unsigned int rfrc;
219 unsigned int tfrc;
220 unsigned int cmdau;
221 unsigned int cmddu;
222 unsigned int rxt;
223 unsigned int rdr1;
224 unsigned int rdr0;
225 unsigned int tde1;
226 unsigned int tde0;
227 unsigned int roe1;
228 unsigned int roe0;
229 unsigned int tue1;
230 unsigned int tue0;
231 unsigned int tfs;
232 unsigned int rfs;
233 unsigned int tls;
234 unsigned int rls;
235 unsigned int rff1;
236 unsigned int rff0;
237 unsigned int tfe1;
238 unsigned int tfe0;
239 } stats;
240 };
241
242 void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
243
244 int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
245
246 void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
247
248 #else
249
250 struct fsl_ssi_dbg {
251 };
252
fsl_ssi_dbg_isr(struct fsl_ssi_dbg * stats,u32 sisr)253 static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
254 {
255 }
256
fsl_ssi_debugfs_create(struct fsl_ssi_dbg * ssi_dbg,struct device * dev)257 static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
258 struct device *dev)
259 {
260 return 0;
261 }
262
fsl_ssi_debugfs_remove(struct fsl_ssi_dbg * ssi_dbg)263 static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
264 {
265 }
266 #endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
267
268 #endif
269