1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 23 /*! \file octeon_iq.h 24 * \brief Host Driver: Implementation of Octeon input queues. "Input" is 25 * with respect to the Octeon device on the NIC. From this driver's 26 * point of view they are egress queues. 27 */ 28 29 #ifndef __OCTEON_IQ_H__ 30 #define __OCTEON_IQ_H__ 31 32 #define IQ_STATUS_RUNNING 1 33 34 #define IQ_SEND_OK 0 35 #define IQ_SEND_STOP 1 36 #define IQ_SEND_FAILED -1 37 38 /*------------------------- INSTRUCTION QUEUE --------------------------*/ 39 40 /* \cond */ 41 42 #define REQTYPE_NONE 0 43 #define REQTYPE_NORESP_NET 1 44 #define REQTYPE_NORESP_NET_SG 2 45 #define REQTYPE_RESP_NET 3 46 #define REQTYPE_RESP_NET_SG 4 47 #define REQTYPE_SOFT_COMMAND 5 48 #define REQTYPE_LAST 5 49 50 struct octeon_request_list { 51 u32 reqtype; 52 void *buf; 53 }; 54 55 /* \endcond */ 56 57 /** Input Queue statistics. Each input queue has four stats fields. */ 58 struct oct_iq_stats { 59 u64 instr_posted; /**< Instructions posted to this queue. */ 60 u64 instr_processed; /**< Instructions processed in this queue. */ 61 u64 instr_dropped; /**< Instructions that could not be processed */ 62 u64 bytes_sent; /**< Bytes sent through this queue. */ 63 u64 sgentry_sent;/**< Gather entries sent through this queue. */ 64 u64 tx_done;/**< Num of packets sent to network. */ 65 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 66 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 67 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 68 u64 tx_gso; /* count of tso */ 69 u64 tx_vxlan; /* tunnel */ 70 u64 tx_dmamap_fail; 71 u64 tx_restart; 72 /*u64 tx_timeout_count;*/ 73 }; 74 75 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 76 77 /** The instruction (input) queue. 78 * The input queue is used to post raw (instruction) mode data or packet 79 * data to Octeon device from the host. Each input queue (upto 4) for 80 * a Octeon device has one such structure to represent it. 81 */ 82 struct octeon_instr_queue { 83 struct octeon_device *oct_dev; 84 85 /** A spinlock to protect access to the input ring. */ 86 spinlock_t lock; 87 88 /** A spinlock to protect while posting on the ring. */ 89 spinlock_t post_lock; 90 91 u32 pkt_in_done; 92 93 /** A spinlock to protect access to the input ring.*/ 94 spinlock_t iq_flush_running_lock; 95 96 /** Flag that indicates if the queue uses 64 byte commands. */ 97 u32 iqcmd_64B:1; 98 99 /** Queue info. */ 100 union oct_txpciq txpciq; 101 102 u32 rsvd:17; 103 104 /* Controls whether extra flushing of IQ is done on Tx */ 105 u32 do_auto_flush:1; 106 107 u32 status:8; 108 109 /** Maximum no. of instructions in this queue. */ 110 u32 max_count; 111 112 /** Index in input ring where the driver should write the next packet */ 113 u32 host_write_index; 114 115 /** Index in input ring where Octeon is expected to read the next 116 * packet. 117 */ 118 u32 octeon_read_index; 119 120 /** This index aids in finding the window in the queue where Octeon 121 * has read the commands. 122 */ 123 u32 flush_index; 124 125 /** This field keeps track of the instructions pending in this queue. */ 126 atomic_t instr_pending; 127 128 u32 reset_instr_cnt; 129 130 /** Pointer to the Virtual Base addr of the input ring. */ 131 u8 *base_addr; 132 133 struct octeon_request_list *request_list; 134 135 /** Octeon doorbell register for the ring. */ 136 void __iomem *doorbell_reg; 137 138 /** Octeon instruction count register for this ring. */ 139 void __iomem *inst_cnt_reg; 140 141 /** Number of instructions pending to be posted to Octeon. */ 142 u32 fill_cnt; 143 144 /** The max. number of instructions that can be held pending by the 145 * driver. 146 */ 147 u32 fill_threshold; 148 149 /** The last time that the doorbell was rung. */ 150 u64 last_db_time; 151 152 /** The doorbell timeout. If the doorbell was not rung for this time and 153 * fill_cnt is non-zero, ring the doorbell again. 154 */ 155 u32 db_timeout; 156 157 /** Statistics for this input queue. */ 158 struct oct_iq_stats stats; 159 160 /** DMA mapped base address of the input descriptor ring. */ 161 u64 base_addr_dma; 162 163 /** Application context */ 164 void *app_ctx; 165 166 /* network stack queue index */ 167 int q_index; 168 169 /*os ifidx associated with this queue */ 170 int ifidx; 171 172 }; 173 174 /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 175 176 /** 32-byte instruction format. 177 * Format of instruction for a 32-byte mode input queue. 178 */ 179 struct octeon_instr_32B { 180 /** Pointer where the input data is available. */ 181 u64 dptr; 182 183 /** Instruction Header. */ 184 u64 ih; 185 186 /** Pointer where the response for a RAW mode packet will be written 187 * by Octeon. 188 */ 189 u64 rptr; 190 191 /** Input Request Header. Additional info about the input. */ 192 u64 irh; 193 194 }; 195 196 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 197 198 /** 64-byte instruction format. 199 * Format of instruction for a 64-byte mode input queue. 200 */ 201 struct octeon_instr2_64B { 202 /** Pointer where the input data is available. */ 203 u64 dptr; 204 205 /** Instruction Header. */ 206 u64 ih2; 207 208 /** Input Request Header. */ 209 u64 irh; 210 211 /** opcode/subcode specific parameters */ 212 u64 ossp[2]; 213 214 /** Return Data Parameters */ 215 u64 rdp; 216 217 /** Pointer where the response for a RAW mode packet will be written 218 * by Octeon. 219 */ 220 u64 rptr; 221 222 u64 reserved; 223 }; 224 225 struct octeon_instr3_64B { 226 /** Pointer where the input data is available. */ 227 u64 dptr; 228 229 /** Instruction Header. */ 230 u64 ih3; 231 232 /** Instruction Header. */ 233 u64 pki_ih3; 234 235 /** Input Request Header. */ 236 u64 irh; 237 238 /** opcode/subcode specific parameters */ 239 u64 ossp[2]; 240 241 /** Return Data Parameters */ 242 u64 rdp; 243 244 /** Pointer where the response for a RAW mode packet will be written 245 * by Octeon. 246 */ 247 u64 rptr; 248 249 }; 250 251 union octeon_instr_64B { 252 struct octeon_instr2_64B cmd2; 253 struct octeon_instr3_64B cmd3; 254 }; 255 256 #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) 257 258 /** The size of each buffer in soft command buffer pool 259 */ 260 #define SOFT_COMMAND_BUFFER_SIZE 1536 261 262 struct octeon_soft_command { 263 /** Soft command buffer info. */ 264 struct list_head node; 265 u64 dma_addr; 266 u32 size; 267 268 /** Command and return status */ 269 union octeon_instr_64B cmd; 270 271 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 272 u64 *status_word; 273 274 /** Data buffer info */ 275 void *virtdptr; 276 u64 dmadptr; 277 u32 datasize; 278 279 /** Return buffer info */ 280 void *virtrptr; 281 u64 dmarptr; 282 u32 rdatasize; 283 284 /** Context buffer info */ 285 void *ctxptr; 286 u32 ctxsize; 287 288 /** Time out and callback */ 289 size_t wait_time; 290 size_t timeout; 291 u32 iq_no; 292 void (*callback)(struct octeon_device *, u32, void *); 293 void *callback_arg; 294 }; 295 296 /** Maximum number of buffers to allocate into soft command buffer pool 297 */ 298 #define MAX_SOFT_COMMAND_BUFFERS 256 299 300 /** Head of a soft command buffer pool. 301 */ 302 struct octeon_sc_buffer_pool { 303 /** List structure to add delete pending entries to */ 304 struct list_head head; 305 306 /** A lock for this response list */ 307 spinlock_t lock; 308 309 atomic_t alloc_buf_count; 310 }; 311 312 int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 313 int octeon_free_sc_buffer_pool(struct octeon_device *oct); 314 struct octeon_soft_command * 315 octeon_alloc_soft_command(struct octeon_device *oct, 316 u32 datasize, u32 rdatasize, 317 u32 ctxsize); 318 void octeon_free_soft_command(struct octeon_device *oct, 319 struct octeon_soft_command *sc); 320 321 /** 322 * octeon_init_instr_queue() 323 * @param octeon_dev - pointer to the octeon device structure. 324 * @param txpciq - queue to be initialized (0 <= q_no <= 3). 325 * 326 * Called at driver init time for each input queue. iq_conf has the 327 * configuration parameters for the queue. 328 * 329 * @return Success: 0 Failure: 1 330 */ 331 int octeon_init_instr_queue(struct octeon_device *octeon_dev, 332 union oct_txpciq txpciq, 333 u32 num_descs); 334 335 /** 336 * octeon_delete_instr_queue() 337 * @param octeon_dev - pointer to the octeon device structure. 338 * @param iq_no - queue to be deleted (0 <= q_no <= 3). 339 * 340 * Called at driver unload time for each input queue. Deletes all 341 * allocated resources for the input queue. 342 * 343 * @return Success: 0 Failure: 1 344 */ 345 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 346 347 int lio_wait_for_instr_fetch(struct octeon_device *oct); 348 349 int 350 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 351 void (*fn)(void *)); 352 353 int 354 lio_process_iq_request_list(struct octeon_device *oct, 355 struct octeon_instr_queue *iq, u32 napi_budget); 356 357 int octeon_send_command(struct octeon_device *oct, u32 iq_no, 358 u32 force_db, void *cmd, void *buf, 359 u32 datasize, u32 reqtype); 360 361 void octeon_prepare_soft_command(struct octeon_device *oct, 362 struct octeon_soft_command *sc, 363 u8 opcode, u8 subcode, 364 u32 irh_ossp, u64 ossp0, 365 u64 ossp1); 366 367 int octeon_send_soft_command(struct octeon_device *oct, 368 struct octeon_soft_command *sc); 369 370 int octeon_setup_iq(struct octeon_device *oct, int ifidx, 371 int q_index, union oct_txpciq iq_no, u32 num_descs, 372 void *app_ctx); 373 int 374 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 375 u32 pending_thresh, u32 napi_budget); 376 #endif /* __OCTEON_IQ_H__ */ 377