1config MMU 2 def_bool n 3 4config FPU 5 def_bool n 6 7config RWSEM_GENERIC_SPINLOCK 8 def_bool y 9 10config RWSEM_XCHGADD_ALGORITHM 11 def_bool n 12 13config BLACKFIN 14 def_bool y 15 select HAVE_ARCH_KGDB 16 select HAVE_ARCH_TRACEHOOK 17 select HAVE_DYNAMIC_FTRACE 18 select HAVE_FTRACE_MCOUNT_RECORD 19 select HAVE_FUNCTION_GRAPH_TRACER 20 select HAVE_FUNCTION_TRACER 21 select HAVE_IDE 22 select HAVE_KERNEL_GZIP if RAMKERNEL 23 select HAVE_KERNEL_BZIP2 if RAMKERNEL 24 select HAVE_KERNEL_LZMA if RAMKERNEL 25 select HAVE_KERNEL_LZO if RAMKERNEL 26 select HAVE_OPROFILE 27 select HAVE_PERF_EVENTS 28 select ARCH_HAVE_CUSTOM_GPIO_H 29 select GPIOLIB 30 select HAVE_UID16 31 select HAVE_UNDERSCORE_SYMBOL_PREFIX 32 select VIRT_TO_BUS 33 select ARCH_WANT_IPC_PARSE_VERSION 34 select GENERIC_ATOMIC64 35 select GENERIC_IRQ_PROBE 36 select GENERIC_IRQ_SHOW 37 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG 38 select GENERIC_SMP_IDLE_THREAD 39 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS 40 select HAVE_MOD_ARCH_SPECIFIC 41 select MODULES_USE_ELF_RELA 42 select HAVE_DEBUG_STACKOVERFLOW 43 select HAVE_NMI 44 45config GENERIC_CSUM 46 def_bool y 47 48config GENERIC_BUG 49 def_bool y 50 depends on BUG 51 52config ZONE_DMA 53 def_bool y 54 55config FORCE_MAX_ZONEORDER 56 int 57 default "14" 58 59config GENERIC_CALIBRATE_DELAY 60 def_bool y 61 62config LOCKDEP_SUPPORT 63 def_bool y 64 65config STACKTRACE_SUPPORT 66 def_bool y 67 68config TRACE_IRQFLAGS_SUPPORT 69 def_bool y 70 71source "init/Kconfig" 72 73source "kernel/Kconfig.preempt" 74 75source "kernel/Kconfig.freezer" 76 77menu "Blackfin Processor Options" 78 79comment "Processor and Board Settings" 80 81choice 82 prompt "CPU" 83 default BF533 84 85config BF512 86 bool "BF512" 87 help 88 BF512 Processor Support. 89 90config BF514 91 bool "BF514" 92 help 93 BF514 Processor Support. 94 95config BF516 96 bool "BF516" 97 help 98 BF516 Processor Support. 99 100config BF518 101 bool "BF518" 102 help 103 BF518 Processor Support. 104 105config BF522 106 bool "BF522" 107 help 108 BF522 Processor Support. 109 110config BF523 111 bool "BF523" 112 help 113 BF523 Processor Support. 114 115config BF524 116 bool "BF524" 117 help 118 BF524 Processor Support. 119 120config BF525 121 bool "BF525" 122 help 123 BF525 Processor Support. 124 125config BF526 126 bool "BF526" 127 help 128 BF526 Processor Support. 129 130config BF527 131 bool "BF527" 132 help 133 BF527 Processor Support. 134 135config BF531 136 bool "BF531" 137 help 138 BF531 Processor Support. 139 140config BF532 141 bool "BF532" 142 help 143 BF532 Processor Support. 144 145config BF533 146 bool "BF533" 147 help 148 BF533 Processor Support. 149 150config BF534 151 bool "BF534" 152 help 153 BF534 Processor Support. 154 155config BF536 156 bool "BF536" 157 help 158 BF536 Processor Support. 159 160config BF537 161 bool "BF537" 162 help 163 BF537 Processor Support. 164 165config BF538 166 bool "BF538" 167 help 168 BF538 Processor Support. 169 170config BF539 171 bool "BF539" 172 help 173 BF539 Processor Support. 174 175config BF542_std 176 bool "BF542" 177 help 178 BF542 Processor Support. 179 180config BF542M 181 bool "BF542m" 182 help 183 BF542 Processor Support. 184 185config BF544_std 186 bool "BF544" 187 help 188 BF544 Processor Support. 189 190config BF544M 191 bool "BF544m" 192 help 193 BF544 Processor Support. 194 195config BF547_std 196 bool "BF547" 197 help 198 BF547 Processor Support. 199 200config BF547M 201 bool "BF547m" 202 help 203 BF547 Processor Support. 204 205config BF548_std 206 bool "BF548" 207 help 208 BF548 Processor Support. 209 210config BF548M 211 bool "BF548m" 212 help 213 BF548 Processor Support. 214 215config BF549_std 216 bool "BF549" 217 help 218 BF549 Processor Support. 219 220config BF549M 221 bool "BF549m" 222 help 223 BF549 Processor Support. 224 225config BF561 226 bool "BF561" 227 help 228 BF561 Processor Support. 229 230config BF609 231 bool "BF609" 232 select CLKDEV_LOOKUP 233 help 234 BF609 Processor Support. 235 236endchoice 237 238config SMP 239 depends on BF561 240 select TICKSOURCE_CORETMR 241 bool "Symmetric multi-processing support" 242 ---help--- 243 This enables support for systems with more than one CPU, 244 like the dual core BF561. If you have a system with only one 245 CPU, say N. If you have a system with more than one CPU, say Y. 246 247 If you don't know what to do here, say N. 248 249config NR_CPUS 250 int 251 depends on SMP 252 default 2 if BF561 253 254config HOTPLUG_CPU 255 bool "Support for hot-pluggable CPUs" 256 depends on SMP 257 default y 258 259config BF_REV_MIN 260 int 261 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 262 default 2 if (BF537 || BF536 || BF534) 263 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 264 default 4 if (BF538 || BF539) 265 266config BF_REV_MAX 267 int 268 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x 269 default 3 if (BF537 || BF536 || BF534 || BF54xM) 270 default 5 if (BF561 || BF538 || BF539) 271 default 6 if (BF533 || BF532 || BF531) 272 273choice 274 prompt "Silicon Rev" 275 default BF_REV_0_0 if (BF51x || BF52x || BF60x) 276 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 277 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 278 279config BF_REV_0_0 280 bool "0.0" 281 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 282 283config BF_REV_0_1 284 bool "0.1" 285 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) 286 287config BF_REV_0_2 288 bool "0.2" 289 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 290 291config BF_REV_0_3 292 bool "0.3" 293 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 294 295config BF_REV_0_4 296 bool "0.4" 297 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) 298 299config BF_REV_0_5 300 bool "0.5" 301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 302 303config BF_REV_0_6 304 bool "0.6" 305 depends on (BF533 || BF532 || BF531) 306 307config BF_REV_ANY 308 bool "any" 309 310config BF_REV_NONE 311 bool "none" 312 313endchoice 314 315config BF53x 316 bool 317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 318 default y 319 320config GPIO_ADI 321 def_bool y 322 depends on !PINCTRL 323 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561) 324 325config PINCTRL_BLACKFIN_ADI2 326 def_bool y 327 depends on (BF54x || BF60x) 328 select PINCTRL 329 select PINCTRL_ADI2 330 331config MEM_MT48LC64M4A2FB_7E 332 bool 333 depends on (BFIN533_STAMP) 334 default y 335 336config MEM_MT48LC16M16A2TG_75 337 bool 338 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 339 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 340 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 341 || BFIN527_BLUETECHNIX_CM) 342 default y 343 344config MEM_MT48LC32M8A2_75 345 bool 346 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 347 default y 348 349config MEM_MT48LC8M32B2B5_7 350 bool 351 depends on (BFIN561_BLUETECHNIX_CM) 352 default y 353 354config MEM_MT48LC32M16A2TG_75 355 bool 356 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) 357 default y 358 359config MEM_MT48H32M16LFCJ_75 360 bool 361 depends on (BFIN526_EZBRD) 362 default y 363 364config MEM_MT47H64M16 365 bool 366 depends on (BFIN609_EZKIT) 367 default y 368 369source "arch/blackfin/mach-bf518/Kconfig" 370source "arch/blackfin/mach-bf527/Kconfig" 371source "arch/blackfin/mach-bf533/Kconfig" 372source "arch/blackfin/mach-bf561/Kconfig" 373source "arch/blackfin/mach-bf537/Kconfig" 374source "arch/blackfin/mach-bf538/Kconfig" 375source "arch/blackfin/mach-bf548/Kconfig" 376source "arch/blackfin/mach-bf609/Kconfig" 377 378menu "Board customizations" 379 380config CMDLINE_BOOL 381 bool "Default bootloader kernel arguments" 382 383config CMDLINE 384 string "Initial kernel command string" 385 depends on CMDLINE_BOOL 386 default "console=ttyBF0,57600" 387 help 388 If you don't have a boot loader capable of passing a command line string 389 to the kernel, you may specify one here. As a minimum, you should specify 390 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 391 392config BOOT_LOAD 393 hex "Kernel load address for booting" 394 default "0x1000" 395 range 0x1000 0x20000000 396 help 397 This option allows you to set the load address of the kernel. 398 This can be useful if you are on a board which has a small amount 399 of memory or you wish to reserve some memory at the beginning of 400 the address space. 401 402 Note that you need to keep this value above 4k (0x1000) as this 403 memory region is used to capture NULL pointer references as well 404 as some core kernel functions. 405 406config PHY_RAM_BASE_ADDRESS 407 hex "Physical RAM Base" 408 default 0x0 409 help 410 set BF609 FPGA physical SRAM base address 411 412config ROM_BASE 413 hex "Kernel ROM Base" 414 depends on ROMKERNEL 415 default "0x20040040" 416 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) 417 range 0x20000000 0x30000000 if (BF54x || BF561) 418 range 0xB0000000 0xC0000000 if (BF60x) 419 help 420 Make sure your ROM base does not include any file-header 421 information that is prepended to the kernel. 422 423 For example, the bootable U-Boot format (created with 424 mkimage) has a 64 byte header (0x40). So while the image 425 you write to flash might start at say 0x20080000, you have 426 to add 0x40 to get the kernel's ROM base as it will come 427 after the header. 428 429comment "Clock/PLL Setup" 430 431config CLKIN_HZ 432 int "Frequency of the crystal on the board in Hz" 433 default "10000000" if BFIN532_IP0X 434 default "11059200" if BFIN533_STAMP 435 default "24576000" if PNAV10 436 default "25000000" # most people use this 437 default "27000000" if BFIN533_EZKIT 438 default "30000000" if BFIN561_EZKIT 439 default "24000000" if BFIN527_AD7160EVAL 440 help 441 The frequency of CLKIN crystal oscillator on the board in Hz. 442 Warning: This value should match the crystal on the board. Otherwise, 443 peripherals won't work properly. 444 445config BFIN_KERNEL_CLOCK 446 bool "Re-program Clocks while Kernel boots?" 447 default n 448 help 449 This option decides if kernel clocks are re-programed from the 450 bootloader settings. If the clocks are not set, the SDRAM settings 451 are also not changed, and the Bootloader does 100% of the hardware 452 configuration. 453 454config PLL_BYPASS 455 bool "Bypass PLL" 456 depends on BFIN_KERNEL_CLOCK && (!BF60x) 457 default n 458 459config CLKIN_HALF 460 bool "Half Clock In" 461 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 462 default n 463 help 464 If this is set the clock will be divided by 2, before it goes to the PLL. 465 466config VCO_MULT 467 int "VCO Multiplier" 468 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 469 range 1 64 470 default "22" if BFIN533_EZKIT 471 default "45" if BFIN533_STAMP 472 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 473 default "22" if BFIN533_BLUETECHNIX_CM 474 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 475 default "20" if (BFIN561_EZKIT || BF609) 476 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 477 default "25" if BFIN527_AD7160EVAL 478 help 479 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 480 PLL Frequency = (Crystal Frequency) * (this setting) 481 482choice 483 prompt "Core Clock Divider" 484 depends on BFIN_KERNEL_CLOCK 485 default CCLK_DIV_1 486 help 487 This sets the frequency of the core. It can be 1, 2, 4 or 8 488 Core Frequency = (PLL frequency) / (this setting) 489 490config CCLK_DIV_1 491 bool "1" 492 493config CCLK_DIV_2 494 bool "2" 495 496config CCLK_DIV_4 497 bool "4" 498 499config CCLK_DIV_8 500 bool "8" 501endchoice 502 503config SCLK_DIV 504 int "System Clock Divider" 505 depends on BFIN_KERNEL_CLOCK 506 range 1 15 507 default 4 508 help 509 This sets the frequency of the system clock (including SDRAM or DDR) on 510 !BF60x else it set the clock for system buses and provides the 511 source from which SCLK0 and SCLK1 are derived. 512 This can be between 1 and 15 513 System Clock = (PLL frequency) / (this setting) 514 515config SCLK0_DIV 516 int "System Clock0 Divider" 517 depends on BFIN_KERNEL_CLOCK && BF60x 518 range 1 15 519 default 1 520 help 521 This sets the frequency of the system clock0 for PVP and all other 522 peripherals not clocked by SCLK1. 523 This can be between 1 and 15 524 System Clock0 = (System Clock) / (this setting) 525 526config SCLK1_DIV 527 int "System Clock1 Divider" 528 depends on BFIN_KERNEL_CLOCK && BF60x 529 range 1 15 530 default 1 531 help 532 This sets the frequency of the system clock1 (including SPORT, SPI and ACM). 533 This can be between 1 and 15 534 System Clock1 = (System Clock) / (this setting) 535 536config DCLK_DIV 537 int "DDR Clock Divider" 538 depends on BFIN_KERNEL_CLOCK && BF60x 539 range 1 15 540 default 2 541 help 542 This sets the frequency of the DDR memory. 543 This can be between 1 and 15 544 DDR Clock = (PLL frequency) / (this setting) 545 546choice 547 prompt "DDR SDRAM Chip Type" 548 depends on BFIN_KERNEL_CLOCK 549 depends on BF54x 550 default MEM_MT46V32M16_5B 551 552config MEM_MT46V32M16_6T 553 bool "MT46V32M16_6T" 554 555config MEM_MT46V32M16_5B 556 bool "MT46V32M16_5B" 557endchoice 558 559choice 560 prompt "DDR/SDRAM Timing" 561 depends on BFIN_KERNEL_CLOCK && !BF60x 562 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 563 help 564 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 565 The calculated SDRAM timing parameters may not be 100% 566 accurate - This option is therefore marked experimental. 567 568config BFIN_KERNEL_CLOCK_MEMINIT_CALC 569 bool "Calculate Timings" 570 571config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 572 bool "Provide accurate Timings based on target SCLK" 573 help 574 Please consult the Blackfin Hardware Reference Manuals as well 575 as the memory device datasheet. 576 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 577endchoice 578 579menu "Memory Init Control" 580 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 581 582config MEM_DDRCTL0 583 depends on BF54x 584 hex "DDRCTL0" 585 default 0x0 586 587config MEM_DDRCTL1 588 depends on BF54x 589 hex "DDRCTL1" 590 default 0x0 591 592config MEM_DDRCTL2 593 depends on BF54x 594 hex "DDRCTL2" 595 default 0x0 596 597config MEM_EBIU_DDRQUE 598 depends on BF54x 599 hex "DDRQUE" 600 default 0x0 601 602config MEM_SDRRC 603 depends on !BF54x 604 hex "SDRRC" 605 default 0x0 606 607config MEM_SDGCTL 608 depends on !BF54x 609 hex "SDGCTL" 610 default 0x0 611endmenu 612 613# 614# Max & Min Speeds for various Chips 615# 616config MAX_VCO_HZ 617 int 618 default 400000000 if BF512 619 default 400000000 if BF514 620 default 400000000 if BF516 621 default 400000000 if BF518 622 default 400000000 if BF522 623 default 600000000 if BF523 624 default 400000000 if BF524 625 default 600000000 if BF525 626 default 400000000 if BF526 627 default 600000000 if BF527 628 default 400000000 if BF531 629 default 400000000 if BF532 630 default 750000000 if BF533 631 default 500000000 if BF534 632 default 400000000 if BF536 633 default 600000000 if BF537 634 default 533333333 if BF538 635 default 533333333 if BF539 636 default 600000000 if BF542 637 default 533333333 if BF544 638 default 600000000 if BF547 639 default 600000000 if BF548 640 default 533333333 if BF549 641 default 600000000 if BF561 642 default 800000000 if BF609 643 644config MIN_VCO_HZ 645 int 646 default 50000000 647 648config MAX_SCLK_HZ 649 int 650 default 200000000 if BF609 651 default 133333333 652 653config MIN_SCLK_HZ 654 int 655 default 27000000 656 657comment "Kernel Timer/Scheduler" 658 659source kernel/Kconfig.hz 660 661config SET_GENERIC_CLOCKEVENTS 662 bool "Generic clock events" 663 default y 664 select GENERIC_CLOCKEVENTS 665 666menu "Clock event device" 667 depends on GENERIC_CLOCKEVENTS 668config TICKSOURCE_GPTMR0 669 bool "GPTimer0" 670 depends on !SMP 671 select BFIN_GPTIMERS 672 673config TICKSOURCE_CORETMR 674 bool "Core timer" 675 default y 676endmenu 677 678menu "Clock source" 679 depends on GENERIC_CLOCKEVENTS 680config CYCLES_CLOCKSOURCE 681 bool "CYCLES" 682 default y 683 depends on !BFIN_SCRATCH_REG_CYCLES 684 depends on !SMP 685 help 686 If you say Y here, you will enable support for using the 'cycles' 687 registers as a clock source. Doing so means you will be unable to 688 safely write to the 'cycles' register during runtime. You will 689 still be able to read it (such as for performance monitoring), but 690 writing the registers will most likely crash the kernel. 691 692config GPTMR0_CLOCKSOURCE 693 bool "GPTimer0" 694 select BFIN_GPTIMERS 695 depends on !TICKSOURCE_GPTMR0 696endmenu 697 698comment "Misc" 699 700choice 701 prompt "Blackfin Exception Scratch Register" 702 default BFIN_SCRATCH_REG_RETN 703 help 704 Select the resource to reserve for the Exception handler: 705 - RETN: Non-Maskable Interrupt (NMI) 706 - RETE: Exception Return (JTAG/ICE) 707 - CYCLES: Performance counter 708 709 If you are unsure, please select "RETN". 710 711config BFIN_SCRATCH_REG_RETN 712 bool "RETN" 713 help 714 Use the RETN register in the Blackfin exception handler 715 as a stack scratch register. This means you cannot 716 safely use NMI on the Blackfin while running Linux, but 717 you can debug the system with a JTAG ICE and use the 718 CYCLES performance registers. 719 720 If you are unsure, please select "RETN". 721 722config BFIN_SCRATCH_REG_RETE 723 bool "RETE" 724 help 725 Use the RETE register in the Blackfin exception handler 726 as a stack scratch register. This means you cannot 727 safely use a JTAG ICE while debugging a Blackfin board, 728 but you can safely use the CYCLES performance registers 729 and the NMI. 730 731 If you are unsure, please select "RETN". 732 733config BFIN_SCRATCH_REG_CYCLES 734 bool "CYCLES" 735 help 736 Use the CYCLES register in the Blackfin exception handler 737 as a stack scratch register. This means you cannot 738 safely use the CYCLES performance registers on a Blackfin 739 board at anytime, but you can debug the system with a JTAG 740 ICE and use the NMI. 741 742 If you are unsure, please select "RETN". 743 744endchoice 745 746endmenu 747 748 749menu "Blackfin Kernel Optimizations" 750 751comment "Memory Optimizations" 752 753config I_ENTRY_L1 754 bool "Locate interrupt entry code in L1 Memory" 755 default y 756 depends on !SMP 757 help 758 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 759 into L1 instruction memory. (less latency) 760 761config EXCPT_IRQ_SYSC_L1 762 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 763 default y 764 depends on !SMP 765 help 766 If enabled, the entire ASM lowlevel exception and interrupt entry code 767 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 768 (less latency) 769 770config DO_IRQ_L1 771 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 772 default y 773 depends on !SMP 774 help 775 If enabled, the frequently called do_irq dispatcher function is linked 776 into L1 instruction memory. (less latency) 777 778config CORE_TIMER_IRQ_L1 779 bool "Locate frequently called timer_interrupt() function in L1 Memory" 780 default y 781 depends on !SMP 782 help 783 If enabled, the frequently called timer_interrupt() function is linked 784 into L1 instruction memory. (less latency) 785 786config IDLE_L1 787 bool "Locate frequently idle function in L1 Memory" 788 default y 789 depends on !SMP 790 help 791 If enabled, the frequently called idle function is linked 792 into L1 instruction memory. (less latency) 793 794config SCHEDULE_L1 795 bool "Locate kernel schedule function in L1 Memory" 796 default y 797 depends on !SMP 798 help 799 If enabled, the frequently called kernel schedule is linked 800 into L1 instruction memory. (less latency) 801 802config ARITHMETIC_OPS_L1 803 bool "Locate kernel owned arithmetic functions in L1 Memory" 804 default y 805 depends on !SMP 806 help 807 If enabled, arithmetic functions are linked 808 into L1 instruction memory. (less latency) 809 810config ACCESS_OK_L1 811 bool "Locate access_ok function in L1 Memory" 812 default y 813 depends on !SMP 814 help 815 If enabled, the access_ok function is linked 816 into L1 instruction memory. (less latency) 817 818config MEMSET_L1 819 bool "Locate memset function in L1 Memory" 820 default y 821 depends on !SMP 822 help 823 If enabled, the memset function is linked 824 into L1 instruction memory. (less latency) 825 826config MEMCPY_L1 827 bool "Locate memcpy function in L1 Memory" 828 default y 829 depends on !SMP 830 help 831 If enabled, the memcpy function is linked 832 into L1 instruction memory. (less latency) 833 834config STRCMP_L1 835 bool "locate strcmp function in L1 Memory" 836 default y 837 depends on !SMP 838 help 839 If enabled, the strcmp function is linked 840 into L1 instruction memory (less latency). 841 842config STRNCMP_L1 843 bool "locate strncmp function in L1 Memory" 844 default y 845 depends on !SMP 846 help 847 If enabled, the strncmp function is linked 848 into L1 instruction memory (less latency). 849 850config STRCPY_L1 851 bool "locate strcpy function in L1 Memory" 852 default y 853 depends on !SMP 854 help 855 If enabled, the strcpy function is linked 856 into L1 instruction memory (less latency). 857 858config STRNCPY_L1 859 bool "locate strncpy function in L1 Memory" 860 default y 861 depends on !SMP 862 help 863 If enabled, the strncpy function is linked 864 into L1 instruction memory (less latency). 865 866config SYS_BFIN_SPINLOCK_L1 867 bool "Locate sys_bfin_spinlock function in L1 Memory" 868 default y 869 depends on !SMP 870 help 871 If enabled, sys_bfin_spinlock function is linked 872 into L1 instruction memory. (less latency) 873 874config CACHELINE_ALIGNED_L1 875 bool "Locate cacheline_aligned data to L1 Data Memory" 876 default y if !BF54x 877 default n if BF54x 878 depends on !SMP && !BF531 && !CRC32 879 help 880 If enabled, cacheline_aligned data is linked 881 into L1 data memory. (less latency) 882 883config SYSCALL_TAB_L1 884 bool "Locate Syscall Table L1 Data Memory" 885 default n 886 depends on !SMP && !BF531 887 help 888 If enabled, the Syscall LUT is linked 889 into L1 data memory. (less latency) 890 891config CPLB_SWITCH_TAB_L1 892 bool "Locate CPLB Switch Tables L1 Data Memory" 893 default n 894 depends on !SMP && !BF531 895 help 896 If enabled, the CPLB Switch Tables are linked 897 into L1 data memory. (less latency) 898 899config ICACHE_FLUSH_L1 900 bool "Locate icache flush funcs in L1 Inst Memory" 901 default y 902 help 903 If enabled, the Blackfin icache flushing functions are linked 904 into L1 instruction memory. 905 906 Note that this might be required to address anomalies, but 907 these functions are pretty small, so it shouldn't be too bad. 908 If you are using a processor affected by an anomaly, the build 909 system will double check for you and prevent it. 910 911config DCACHE_FLUSH_L1 912 bool "Locate dcache flush funcs in L1 Inst Memory" 913 default y 914 depends on !SMP 915 help 916 If enabled, the Blackfin dcache flushing functions are linked 917 into L1 instruction memory. 918 919config APP_STACK_L1 920 bool "Support locating application stack in L1 Scratch Memory" 921 default y 922 depends on !SMP 923 help 924 If enabled the application stack can be located in L1 925 scratch memory (less latency). 926 927 Currently only works with FLAT binaries. 928 929config EXCEPTION_L1_SCRATCH 930 bool "Locate exception stack in L1 Scratch Memory" 931 default n 932 depends on !SMP && !APP_STACK_L1 933 help 934 Whenever an exception occurs, use the L1 Scratch memory for 935 stack storage. You cannot place the stacks of FLAT binaries 936 in L1 when using this option. 937 938 If you don't use L1 Scratch, then you should say Y here. 939 940comment "Speed Optimizations" 941config BFIN_INS_LOWOVERHEAD 942 bool "ins[bwl] low overhead, higher interrupt latency" 943 default y 944 depends on !SMP 945 help 946 Reads on the Blackfin are speculative. In Blackfin terms, this means 947 they can be interrupted at any time (even after they have been issued 948 on to the external bus), and re-issued after the interrupt occurs. 949 For memory - this is not a big deal, since memory does not change if 950 it sees a read. 951 952 If a FIFO is sitting on the end of the read, it will see two reads, 953 when the core only sees one since the FIFO receives both the read 954 which is cancelled (and not delivered to the core) and the one which 955 is re-issued (which is delivered to the core). 956 957 To solve this, interrupts are turned off before reads occur to 958 I/O space. This option controls which the overhead/latency of 959 controlling interrupts during this time 960 "n" turns interrupts off every read 961 (higher overhead, but lower interrupt latency) 962 "y" turns interrupts off every loop 963 (low overhead, but longer interrupt latency) 964 965 default behavior is to leave this set to on (type "Y"). If you are experiencing 966 interrupt latency issues, it is safe and OK to turn this off. 967 968endmenu 969 970choice 971 prompt "Kernel executes from" 972 help 973 Choose the memory type that the kernel will be running in. 974 975config RAMKERNEL 976 bool "RAM" 977 help 978 The kernel will be resident in RAM when running. 979 980config ROMKERNEL 981 bool "ROM" 982 help 983 The kernel will be resident in FLASH/ROM when running. 984 985endchoice 986 987# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both 988config XIP_KERNEL 989 bool 990 default y 991 depends on ROMKERNEL 992 993source "mm/Kconfig" 994 995config BFIN_GPTIMERS 996 tristate "Enable Blackfin General Purpose Timers API" 997 default n 998 help 999 Enable support for the General Purpose Timers API. If you 1000 are unsure, say N. 1001 1002 To compile this driver as a module, choose M here: the module 1003 will be called gptimers. 1004 1005choice 1006 prompt "Uncached DMA region" 1007 default DMA_UNCACHED_1M 1008config DMA_UNCACHED_32M 1009 bool "Enable 32M DMA region" 1010config DMA_UNCACHED_16M 1011 bool "Enable 16M DMA region" 1012config DMA_UNCACHED_8M 1013 bool "Enable 8M DMA region" 1014config DMA_UNCACHED_4M 1015 bool "Enable 4M DMA region" 1016config DMA_UNCACHED_2M 1017 bool "Enable 2M DMA region" 1018config DMA_UNCACHED_1M 1019 bool "Enable 1M DMA region" 1020config DMA_UNCACHED_512K 1021 bool "Enable 512K DMA region" 1022config DMA_UNCACHED_256K 1023 bool "Enable 256K DMA region" 1024config DMA_UNCACHED_128K 1025 bool "Enable 128K DMA region" 1026config DMA_UNCACHED_NONE 1027 bool "Disable DMA region" 1028endchoice 1029 1030 1031comment "Cache Support" 1032 1033config BFIN_ICACHE 1034 bool "Enable ICACHE" 1035 default y 1036config BFIN_EXTMEM_ICACHEABLE 1037 bool "Enable ICACHE for external memory" 1038 depends on BFIN_ICACHE 1039 default y 1040config BFIN_L2_ICACHEABLE 1041 bool "Enable ICACHE for L2 SRAM" 1042 depends on BFIN_ICACHE 1043 depends on (BF54x || BF561 || BF60x) && !SMP 1044 default n 1045 1046config BFIN_DCACHE 1047 bool "Enable DCACHE" 1048 default y 1049config BFIN_DCACHE_BANKA 1050 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 1051 depends on BFIN_DCACHE && !BF531 1052 default n 1053config BFIN_EXTMEM_DCACHEABLE 1054 bool "Enable DCACHE for external memory" 1055 depends on BFIN_DCACHE 1056 default y 1057choice 1058 prompt "External memory DCACHE policy" 1059 depends on BFIN_EXTMEM_DCACHEABLE 1060 default BFIN_EXTMEM_WRITEBACK if !SMP 1061 default BFIN_EXTMEM_WRITETHROUGH if SMP 1062config BFIN_EXTMEM_WRITEBACK 1063 bool "Write back" 1064 depends on !SMP 1065 help 1066 Write Back Policy: 1067 Cached data will be written back to SDRAM only when needed. 1068 This can give a nice increase in performance, but beware of 1069 broken drivers that do not properly invalidate/flush their 1070 cache. 1071 1072 Write Through Policy: 1073 Cached data will always be written back to SDRAM when the 1074 cache is updated. This is a completely safe setting, but 1075 performance is worse than Write Back. 1076 1077 If you are unsure of the options and you want to be safe, 1078 then go with Write Through. 1079 1080config BFIN_EXTMEM_WRITETHROUGH 1081 bool "Write through" 1082 help 1083 Write Back Policy: 1084 Cached data will be written back to SDRAM only when needed. 1085 This can give a nice increase in performance, but beware of 1086 broken drivers that do not properly invalidate/flush their 1087 cache. 1088 1089 Write Through Policy: 1090 Cached data will always be written back to SDRAM when the 1091 cache is updated. This is a completely safe setting, but 1092 performance is worse than Write Back. 1093 1094 If you are unsure of the options and you want to be safe, 1095 then go with Write Through. 1096 1097endchoice 1098 1099config BFIN_L2_DCACHEABLE 1100 bool "Enable DCACHE for L2 SRAM" 1101 depends on BFIN_DCACHE 1102 depends on (BF54x || BF561 || BF60x) && !SMP 1103 default n 1104choice 1105 prompt "L2 SRAM DCACHE policy" 1106 depends on BFIN_L2_DCACHEABLE 1107 default BFIN_L2_WRITEBACK 1108config BFIN_L2_WRITEBACK 1109 bool "Write back" 1110 1111config BFIN_L2_WRITETHROUGH 1112 bool "Write through" 1113endchoice 1114 1115 1116comment "Memory Protection Unit" 1117config MPU 1118 bool "Enable the memory protection unit" 1119 default n 1120 help 1121 Use the processor's MPU to protect applications from accessing 1122 memory they do not own. This comes at a performance penalty 1123 and is recommended only for debugging. 1124 1125comment "Asynchronous Memory Configuration" 1126 1127menu "EBIU_AMGCTL Global Control" 1128 depends on !BF60x 1129config C_AMCKEN 1130 bool "Enable CLKOUT" 1131 default y 1132 1133config C_CDPRIO 1134 bool "DMA has priority over core for ext. accesses" 1135 default n 1136 1137config C_B0PEN 1138 depends on BF561 1139 bool "Bank 0 16 bit packing enable" 1140 default y 1141 1142config C_B1PEN 1143 depends on BF561 1144 bool "Bank 1 16 bit packing enable" 1145 default y 1146 1147config C_B2PEN 1148 depends on BF561 1149 bool "Bank 2 16 bit packing enable" 1150 default y 1151 1152config C_B3PEN 1153 depends on BF561 1154 bool "Bank 3 16 bit packing enable" 1155 default n 1156 1157choice 1158 prompt "Enable Asynchronous Memory Banks" 1159 default C_AMBEN_ALL 1160 1161config C_AMBEN 1162 bool "Disable All Banks" 1163 1164config C_AMBEN_B0 1165 bool "Enable Bank 0" 1166 1167config C_AMBEN_B0_B1 1168 bool "Enable Bank 0 & 1" 1169 1170config C_AMBEN_B0_B1_B2 1171 bool "Enable Bank 0 & 1 & 2" 1172 1173config C_AMBEN_ALL 1174 bool "Enable All Banks" 1175endchoice 1176endmenu 1177 1178menu "EBIU_AMBCTL Control" 1179 depends on !BF60x 1180config BANK_0 1181 hex "Bank 0 (AMBCTL0.L)" 1182 default 0x7BB0 1183 help 1184 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1185 used to control the Asynchronous Memory Bank 0 settings. 1186 1187config BANK_1 1188 hex "Bank 1 (AMBCTL0.H)" 1189 default 0x7BB0 1190 default 0x5558 if BF54x 1191 help 1192 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1193 used to control the Asynchronous Memory Bank 1 settings. 1194 1195config BANK_2 1196 hex "Bank 2 (AMBCTL1.L)" 1197 default 0x7BB0 1198 help 1199 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1200 used to control the Asynchronous Memory Bank 2 settings. 1201 1202config BANK_3 1203 hex "Bank 3 (AMBCTL1.H)" 1204 default 0x99B3 1205 help 1206 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1207 used to control the Asynchronous Memory Bank 3 settings. 1208 1209endmenu 1210 1211config EBIU_MBSCTLVAL 1212 hex "EBIU Bank Select Control Register" 1213 depends on BF54x 1214 default 0 1215 1216config EBIU_MODEVAL 1217 hex "Flash Memory Mode Control Register" 1218 depends on BF54x 1219 default 1 1220 1221config EBIU_FCTLVAL 1222 hex "Flash Memory Bank Control Register" 1223 depends on BF54x 1224 default 6 1225endmenu 1226 1227############################################################################# 1228menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1229 1230config PCI 1231 bool "PCI support" 1232 depends on BROKEN 1233 help 1234 Support for PCI bus. 1235 1236source "drivers/pci/Kconfig" 1237 1238source "drivers/pcmcia/Kconfig" 1239 1240endmenu 1241 1242menu "Executable file formats" 1243 1244source "fs/Kconfig.binfmt" 1245 1246endmenu 1247 1248menu "Power management options" 1249 1250source "kernel/power/Kconfig" 1251 1252config ARCH_SUSPEND_POSSIBLE 1253 def_bool y 1254 1255choice 1256 prompt "Standby Power Saving Mode" 1257 depends on PM && !BF60x 1258 default PM_BFIN_SLEEP_DEEPER 1259config PM_BFIN_SLEEP_DEEPER 1260 bool "Sleep Deeper" 1261 help 1262 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1263 power dissipation by disabling the clock to the processor core (CCLK). 1264 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1265 to 0.85 V to provide the greatest power savings, while preserving the 1266 processor state. 1267 The PLL and system clock (SCLK) continue to operate at a very low 1268 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1269 the SDRAM is put into Self Refresh Mode. Typically an external event 1270 such as GPIO interrupt or RTC activity wakes up the processor. 1271 Various Peripherals such as UART, SPORT, PPI may not function as 1272 normal during Sleep Deeper, due to the reduced SCLK frequency. 1273 When in the sleep mode, system DMA access to L1 memory is not supported. 1274 1275 If unsure, select "Sleep Deeper". 1276 1277config PM_BFIN_SLEEP 1278 bool "Sleep" 1279 help 1280 Sleep Mode (High Power Savings) - The sleep mode reduces power 1281 dissipation by disabling the clock to the processor core (CCLK). 1282 The PLL and system clock (SCLK), however, continue to operate in 1283 this mode. Typically an external event or RTC activity will wake 1284 up the processor. When in the sleep mode, system DMA access to L1 1285 memory is not supported. 1286 1287 If unsure, select "Sleep Deeper". 1288endchoice 1289 1290comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1291 depends on PM 1292 1293config PM_BFIN_WAKE_PH6 1294 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1295 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1296 default n 1297 help 1298 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1299 1300config PM_BFIN_WAKE_GP 1301 bool "Allow Wake-Up from GPIOs" 1302 depends on PM && BF54x 1303 default n 1304 help 1305 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1306 (all processors, except ADSP-BF549). This option sets 1307 the general-purpose wake-up enable (GPWE) control bit to enable 1308 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1309 On ADSP-BF549 this option enables the same functionality on the 1310 /MRXON pin also PH7. 1311 1312config PM_BFIN_WAKE_PA15 1313 bool "Allow Wake-Up from PA15" 1314 depends on PM && BF60x 1315 default n 1316 help 1317 Enable PA15 Wake-Up 1318 1319config PM_BFIN_WAKE_PA15_POL 1320 int "Wake-up priority" 1321 depends on PM_BFIN_WAKE_PA15 1322 default 0 1323 help 1324 Wake-Up priority 0(low) 1(high) 1325 1326config PM_BFIN_WAKE_PB15 1327 bool "Allow Wake-Up from PB15" 1328 depends on PM && BF60x 1329 default n 1330 help 1331 Enable PB15 Wake-Up 1332 1333config PM_BFIN_WAKE_PB15_POL 1334 int "Wake-up priority" 1335 depends on PM_BFIN_WAKE_PB15 1336 default 0 1337 help 1338 Wake-Up priority 0(low) 1(high) 1339 1340config PM_BFIN_WAKE_PC15 1341 bool "Allow Wake-Up from PC15" 1342 depends on PM && BF60x 1343 default n 1344 help 1345 Enable PC15 Wake-Up 1346 1347config PM_BFIN_WAKE_PC15_POL 1348 int "Wake-up priority" 1349 depends on PM_BFIN_WAKE_PC15 1350 default 0 1351 help 1352 Wake-Up priority 0(low) 1(high) 1353 1354config PM_BFIN_WAKE_PD06 1355 bool "Allow Wake-Up from PD06(ETH0_PHYINT)" 1356 depends on PM && BF60x 1357 default n 1358 help 1359 Enable PD06(ETH0_PHYINT) Wake-up 1360 1361config PM_BFIN_WAKE_PD06_POL 1362 int "Wake-up priority" 1363 depends on PM_BFIN_WAKE_PD06 1364 default 0 1365 help 1366 Wake-Up priority 0(low) 1(high) 1367 1368config PM_BFIN_WAKE_PE12 1369 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" 1370 depends on PM && BF60x 1371 default n 1372 help 1373 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up 1374 1375config PM_BFIN_WAKE_PE12_POL 1376 int "Wake-up priority" 1377 depends on PM_BFIN_WAKE_PE12 1378 default 0 1379 help 1380 Wake-Up priority 0(low) 1(high) 1381 1382config PM_BFIN_WAKE_PG04 1383 bool "Allow Wake-Up from PG04(CAN0_RX)" 1384 depends on PM && BF60x 1385 default n 1386 help 1387 Enable PG04(CAN0_RX) Wake-up 1388 1389config PM_BFIN_WAKE_PG04_POL 1390 int "Wake-up priority" 1391 depends on PM_BFIN_WAKE_PG04 1392 default 0 1393 help 1394 Wake-Up priority 0(low) 1(high) 1395 1396config PM_BFIN_WAKE_PG13 1397 bool "Allow Wake-Up from PG13" 1398 depends on PM && BF60x 1399 default n 1400 help 1401 Enable PG13 Wake-Up 1402 1403config PM_BFIN_WAKE_PG13_POL 1404 int "Wake-up priority" 1405 depends on PM_BFIN_WAKE_PG13 1406 default 0 1407 help 1408 Wake-Up priority 0(low) 1(high) 1409 1410config PM_BFIN_WAKE_USB 1411 bool "Allow Wake-Up from (USB)" 1412 depends on PM && BF60x 1413 default n 1414 help 1415 Enable (USB) Wake-up 1416 1417config PM_BFIN_WAKE_USB_POL 1418 int "Wake-up priority" 1419 depends on PM_BFIN_WAKE_USB 1420 default 0 1421 help 1422 Wake-Up priority 0(low) 1(high) 1423 1424endmenu 1425 1426menu "CPU Frequency scaling" 1427 1428source "drivers/cpufreq/Kconfig" 1429 1430config BFIN_CPU_FREQ 1431 bool 1432 depends on CPU_FREQ 1433 default y 1434 1435config CPU_VOLTAGE 1436 bool "CPU Voltage scaling" 1437 depends on CPU_FREQ 1438 default n 1439 help 1440 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1441 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1442 manuals. There is a theoretical risk that during VDDINT transitions 1443 the PLL may unlock. 1444 1445endmenu 1446 1447source "net/Kconfig" 1448 1449source "drivers/Kconfig" 1450 1451source "drivers/firmware/Kconfig" 1452 1453source "fs/Kconfig" 1454 1455source "arch/blackfin/Kconfig.debug" 1456 1457source "security/Kconfig" 1458 1459source "crypto/Kconfig" 1460 1461source "lib/Kconfig" 1462