1 /*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CSIO_HW_H__
36 #define __CSIO_HW_H__
37
38 #include <linux/kernel.h>
39 #include <linux/pci.h>
40 #include <linux/device.h>
41 #include <linux/workqueue.h>
42 #include <linux/compiler.h>
43 #include <linux/cdev.h>
44 #include <linux/list.h>
45 #include <linux/mempool.h>
46 #include <linux/io.h>
47 #include <linux/spinlock_types.h>
48 #include <scsi/scsi_device.h>
49 #include <scsi/scsi_transport_fc.h>
50
51 #include "t4_hw.h"
52 #include "csio_hw_chip.h"
53 #include "csio_wr.h"
54 #include "csio_mb.h"
55 #include "csio_scsi.h"
56 #include "csio_defs.h"
57 #include "t4_regs.h"
58 #include "t4_msg.h"
59
60 /*
61 * An error value used by host. Should not clash with FW defined return values.
62 */
63 #define FW_HOSTERROR 255
64
65 #define CSIO_HW_NAME "Chelsio FCoE Adapter"
66 #define CSIO_MAX_PFN 8
67 #define CSIO_MAX_PPORTS 4
68
69 #define CSIO_MAX_LUN 0xFFFF
70 #define CSIO_MAX_QUEUE 2048
71 #define CSIO_MAX_CMD_PER_LUN 32
72 #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
73 #define CSIO_MAX_SECTOR_SIZE 128
74
75 /* Interrupts */
76 #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
77 * (Forward intr iq + fw iq) */
78 #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
79 #define CSIO_MAX_SCSI_CPU 128
80 #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
81 #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
82
83 /* Queues */
84 enum {
85 CSIO_INTR_WRSIZE = 128,
86 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
87 CSIO_FWEVT_WRSIZE = 128,
88 CSIO_FWEVT_IQLEN = 128,
89 CSIO_FWEVT_FLBUFS = 64,
90 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
91 CSIO_HW_NIQ = 1,
92 CSIO_HW_NFLQ = 1,
93 CSIO_HW_NEQ = 1,
94 CSIO_HW_NINTXQ = 1,
95 };
96
97 struct csio_msix_entries {
98 unsigned short vector; /* Assigned MSI-X vector */
99 void *dev_id; /* Priv object associated w/ this msix*/
100 char desc[24]; /* Description of this vector */
101 };
102
103 struct csio_scsi_qset {
104 int iq_idx; /* Ingress index */
105 int eq_idx; /* Egress index */
106 uint32_t intr_idx; /* MSIX Vector index */
107 };
108
109 struct csio_scsi_cpu_info {
110 int16_t max_cpus;
111 };
112
113 extern int csio_dbg_level;
114 extern unsigned int csio_port_mask;
115 extern int csio_msi;
116
117 #define CSIO_VENDOR_ID 0x1425
118 #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
119 #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
120
121 #define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
122 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
123 PM_TX_F | PM_RX_F | ULP_RX_F | \
124 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
125
126 /*
127 * Hard parameters used to initialize the card in the absence of a
128 * configuration file.
129 */
130 enum {
131 /* General */
132 CSIO_SGE_DBFIFO_INT_THRESH = 10,
133
134 CSIO_SGE_RX_DMA_OFFSET = 2,
135
136 CSIO_SGE_FLBUF_SIZE1 = 65536,
137 CSIO_SGE_FLBUF_SIZE2 = 1536,
138 CSIO_SGE_FLBUF_SIZE3 = 9024,
139 CSIO_SGE_FLBUF_SIZE4 = 9216,
140 CSIO_SGE_FLBUF_SIZE5 = 2048,
141 CSIO_SGE_FLBUF_SIZE6 = 128,
142 CSIO_SGE_FLBUF_SIZE7 = 8192,
143 CSIO_SGE_FLBUF_SIZE8 = 16384,
144
145 CSIO_SGE_TIMER_VAL_0 = 5,
146 CSIO_SGE_TIMER_VAL_1 = 10,
147 CSIO_SGE_TIMER_VAL_2 = 20,
148 CSIO_SGE_TIMER_VAL_3 = 50,
149 CSIO_SGE_TIMER_VAL_4 = 100,
150 CSIO_SGE_TIMER_VAL_5 = 200,
151
152 CSIO_SGE_INT_CNT_VAL_0 = 1,
153 CSIO_SGE_INT_CNT_VAL_1 = 4,
154 CSIO_SGE_INT_CNT_VAL_2 = 8,
155 CSIO_SGE_INT_CNT_VAL_3 = 16,
156 };
157
158 /* Slowpath events */
159 enum csio_evt {
160 CSIO_EVT_FW = 0, /* FW event */
161 CSIO_EVT_MBX, /* MBX event */
162 CSIO_EVT_SCN, /* State change notification */
163 CSIO_EVT_DEV_LOSS, /* Device loss event */
164 CSIO_EVT_MAX, /* Max supported event */
165 };
166
167 #define CSIO_EVT_MSG_SIZE 512
168 #define CSIO_EVTQ_SIZE 512
169
170 /* Event msg */
171 struct csio_evt_msg {
172 struct list_head list; /* evt queue*/
173 enum csio_evt type;
174 uint8_t data[CSIO_EVT_MSG_SIZE];
175 };
176
177 enum {
178 SERNUM_LEN = 16, /* Serial # length */
179 EC_LEN = 16, /* E/C length */
180 ID_LEN = 16, /* ID length */
181 };
182
183 enum {
184 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
185 };
186
187 /* serial flash and firmware constants */
188 enum {
189 SF_ATTEMPTS = 10, /* max retries for SF operations */
190
191 /* flash command opcodes */
192 SF_PROG_PAGE = 2, /* program page */
193 SF_WR_DISABLE = 4, /* disable writes */
194 SF_RD_STATUS = 5, /* read status register */
195 SF_WR_ENABLE = 6, /* enable writes */
196 SF_RD_DATA_FAST = 0xb, /* read flash */
197 SF_RD_ID = 0x9f, /* read ID */
198 SF_ERASE_SECTOR = 0xd8, /* erase sector */
199 };
200
201 /* Management module */
202 enum {
203 CSIO_MGMT_EQ_WRSIZE = 512,
204 CSIO_MGMT_IQ_WRSIZE = 128,
205 CSIO_MGMT_EQLEN = 64,
206 CSIO_MGMT_IQLEN = 64,
207 };
208
209 #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
210 #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
211
212 /* mgmt module stats */
213 struct csio_mgmtm_stats {
214 uint32_t n_abort_req; /* Total abort request */
215 uint32_t n_abort_rsp; /* Total abort response */
216 uint32_t n_close_req; /* Total close request */
217 uint32_t n_close_rsp; /* Total close response */
218 uint32_t n_err; /* Total Errors */
219 uint32_t n_drop; /* Total request dropped */
220 uint32_t n_active; /* Count of active_q */
221 uint32_t n_cbfn; /* Count of cbfn_q */
222 };
223
224 /* MGMT module */
225 struct csio_mgmtm {
226 struct csio_hw *hw; /* Pointer to HW moduel */
227 int eq_idx; /* Egress queue index */
228 int iq_idx; /* Ingress queue index */
229 int msi_vec; /* MSI vector */
230 struct list_head active_q; /* Outstanding ELS/CT */
231 struct list_head abort_q; /* Outstanding abort req */
232 struct list_head cbfn_q; /* Completion queue */
233 struct list_head mgmt_req_freelist; /* Free poll of reqs */
234 /* ELSCT request freelist*/
235 struct timer_list mgmt_timer; /* MGMT timer */
236 struct csio_mgmtm_stats stats; /* ELS/CT stats */
237 };
238
239 struct csio_adap_desc {
240 char model_no[16];
241 char description[32];
242 };
243
244 struct pci_params {
245 uint16_t vendor_id;
246 uint16_t device_id;
247 int vpd_cap_addr;
248 uint16_t speed;
249 uint8_t width;
250 };
251
252 /* User configurable hw parameters */
253 struct csio_hw_params {
254 uint32_t sf_size; /* serial flash
255 * size in bytes
256 */
257 uint32_t sf_nsec; /* # of flash sectors */
258 struct pci_params pci;
259 uint32_t log_level; /* Module-level for
260 * debug log.
261 */
262 };
263
264 struct csio_vpd {
265 uint32_t cclk;
266 uint8_t ec[EC_LEN + 1];
267 uint8_t sn[SERNUM_LEN + 1];
268 uint8_t id[ID_LEN + 1];
269 };
270
271 struct csio_pport {
272 uint16_t pcap;
273 uint8_t portid;
274 uint8_t link_status;
275 uint16_t link_speed;
276 uint8_t mac[6];
277 uint8_t mod_type;
278 uint8_t rsvd1;
279 uint8_t rsvd2;
280 uint8_t rsvd3;
281 };
282
283 /* fcoe resource information */
284 struct csio_fcoe_res_info {
285 uint16_t e_d_tov;
286 uint16_t r_a_tov_seq;
287 uint16_t r_a_tov_els;
288 uint16_t r_r_tov;
289 uint32_t max_xchgs;
290 uint32_t max_ssns;
291 uint32_t used_xchgs;
292 uint32_t used_ssns;
293 uint32_t max_fcfs;
294 uint32_t max_vnps;
295 uint32_t used_fcfs;
296 uint32_t used_vnps;
297 };
298
299 /* HW State machine Events */
300 enum csio_hw_ev {
301 CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
302 CSIO_HWE_INIT, /* Config done, start Init */
303 CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
304 CSIO_HWE_FATAL, /* Fatal error during initialization */
305 CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
306 CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
307 CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
308 CSIO_HWE_QUIESCED, /* HBA quiesced */
309 CSIO_HWE_HBA_RESET, /* HBA reset requested */
310 CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
311 CSIO_HWE_FW_DLOAD, /* FW download requested */
312 CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
313 CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
314 CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
315 CSIO_HWE_MAX, /* Max HW event */
316 };
317
318 /* hw stats */
319 struct csio_hw_stats {
320 uint32_t n_evt_activeq; /* Number of event in active Q */
321 uint32_t n_evt_freeq; /* Number of event in free Q */
322 uint32_t n_evt_drop; /* Number of event droped */
323 uint32_t n_evt_unexp; /* Number of unexpected events */
324 uint32_t n_pcich_offline;/* Number of pci channel offline */
325 uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
326 uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
327 uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
328 uint32_t n_cpl_unexp; /* Number of unexpected cpl */
329 uint32_t n_mbint_unexp; /* Number of unexpected mbox */
330 /* interrupt */
331 uint32_t n_plint_unexp; /* Number of unexpected PL */
332 /* interrupt */
333 uint32_t n_plint_cnt; /* Number of PL interrupt */
334 uint32_t n_int_stray; /* Number of stray interrupt */
335 uint32_t n_err; /* Number of hw errors */
336 uint32_t n_err_fatal; /* Number of fatal errors */
337 uint32_t n_err_nomem; /* Number of memory alloc failure */
338 uint32_t n_err_io; /* Number of IO failure */
339 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
340 uint64_t n_reset_start; /* Start time after the reset */
341 uint32_t rsvd1;
342 };
343
344 /* Defines for hw->flags */
345 #define CSIO_HWF_MASTER 0x00000001 /* This is the Master
346 * function for the
347 * card.
348 */
349 #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
350 * enable bit set?
351 */
352 #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
353 #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
354 * allocated memory.
355 */
356 #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
357 * allocated in FW.
358 */
359 #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
360 #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
361 * id cached */
362 #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
363 * FW events
364 */
365 #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
366 * params
367 */
368 #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
369 * enabled?
370 */
371
372 #define csio_is_hw_intr_enabled(__hw) \
373 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
374 #define csio_is_host_intr_enabled(__hw) \
375 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
376 #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
377 #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
378 #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
379 #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
380 #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
381
382 /* Defines for intr_mode */
383 enum csio_intr_mode {
384 CSIO_IM_NONE = 0,
385 CSIO_IM_INTX = 1,
386 CSIO_IM_MSI = 2,
387 CSIO_IM_MSIX = 3,
388 };
389
390 /* Master HW structure: One per function */
391 struct csio_hw {
392 struct csio_sm sm; /* State machine: should
393 * be the 1st member.
394 */
395 spinlock_t lock; /* Lock for hw */
396
397 struct csio_scsim scsim; /* SCSI module*/
398 struct csio_wrm wrm; /* Work request module*/
399 struct pci_dev *pdev; /* PCI device */
400
401 void __iomem *regstart; /* Virtual address of
402 * register map
403 */
404 /* SCSI queue sets */
405 uint32_t num_sqsets; /* Number of SCSI
406 * queue sets */
407 uint32_t num_scsi_msix_cpus; /* Number of CPUs that
408 * will be used
409 * for ingress
410 * processing.
411 */
412
413 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
414 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
415
416 uint32_t evtflag; /* Event flag */
417 uint32_t flags; /* HW flags */
418
419 struct csio_mgmtm mgmtm; /* management module */
420 struct csio_mbm mbm; /* Mailbox module */
421
422 /* Lnodes */
423 uint32_t num_lns; /* Number of lnodes */
424 struct csio_lnode *rln; /* Root lnode */
425 struct list_head sln_head; /* Sibling node list
426 * list
427 */
428 int intr_iq_idx; /* Forward interrupt
429 * queue.
430 */
431 int fwevt_iq_idx; /* FW evt queue */
432 struct work_struct evtq_work; /* Worker thread for
433 * HW events.
434 */
435 struct list_head evt_free_q; /* freelist of evt
436 * elements
437 */
438 struct list_head evt_active_q; /* active evt queue*/
439
440 /* board related info */
441 char name[32];
442 char hw_ver[16];
443 char model_desc[32];
444 char drv_version[32];
445 char fwrev_str[32];
446 uint32_t optrom_ver;
447 uint32_t fwrev;
448 uint32_t tp_vers;
449 char chip_ver;
450 uint16_t chip_id; /* Tells T4/T5 chip */
451 enum csio_dev_state fw_state;
452 struct csio_vpd vpd;
453
454 uint8_t pfn; /* Physical Function
455 * number
456 */
457 uint32_t port_vec; /* Port vector */
458 uint8_t num_pports; /* Number of physical
459 * ports.
460 */
461 uint8_t rst_retries; /* Reset retries */
462 uint8_t cur_evt; /* current s/m evt */
463 uint8_t prev_evt; /* Previous s/m evt */
464 uint32_t dev_num; /* device number */
465 struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
466 struct csio_hw_params params; /* Hw parameters */
467
468 struct pci_pool *scsi_pci_pool; /* PCI pool for SCSI */
469 mempool_t *mb_mempool; /* Mailbox memory pool*/
470 mempool_t *rnode_mempool; /* rnode memory pool */
471
472 /* Interrupt */
473 enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
474 uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
475 * index
476 */
477 uint32_t nondata_intr_idx; /* nondata MSIX/intr
478 * idx
479 */
480
481 uint8_t cfg_neq; /* FW configured no of
482 * egress queues
483 */
484 uint8_t cfg_niq; /* FW configured no of
485 * iq queues.
486 */
487
488 struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
489 struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
490 * Operations
491 */
492
493 /* MSIX vectors */
494 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
495
496 struct dentry *debugfs_root; /* Debug FS */
497 struct csio_hw_stats stats; /* Hw statistics */
498 };
499
500 /* Register access macros */
501 #define csio_reg(_b, _r) ((_b) + (_r))
502
503 #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
504 #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
505 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
506 #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
507
508 #define csio_wr_reg8(_h, _v, _r) writeb((_v), \
509 csio_reg((_h)->regstart, (_r)))
510 #define csio_wr_reg16(_h, _v, _r) writew((_v), \
511 csio_reg((_h)->regstart, (_r)))
512 #define csio_wr_reg32(_h, _v, _r) writel((_v), \
513 csio_reg((_h)->regstart, (_r)))
514 #define csio_wr_reg64(_h, _v, _r) writeq((_v), \
515 csio_reg((_h)->regstart, (_r)))
516
517 void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
518
519 /* Core clocks <==> uSecs */
520 static inline uint32_t
csio_core_ticks_to_us(struct csio_hw * hw,uint32_t ticks)521 csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
522 {
523 /* add Core Clock / 2 to round ticks to nearest uS */
524 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
525 }
526
527 static inline uint32_t
csio_us_to_core_ticks(struct csio_hw * hw,uint32_t us)528 csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
529 {
530 return (us * hw->vpd.cclk) / 1000;
531 }
532
533 /* Easy access macros */
534 #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
535 #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
536 #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
537 #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
538
539 #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
540 #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
541 #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
542
543 #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
544 #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
545 #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
546 #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
547
548 /* Printing/logging */
549 #define CSIO_DEVID(__dev) ((__dev)->dev_num)
550 #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
551 #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
552
553 #define csio_info(__hw, __fmt, ...) \
554 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
555
556 #define csio_fatal(__hw, __fmt, ...) \
557 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
558
559 #define csio_err(__hw, __fmt, ...) \
560 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
561
562 #define csio_warn(__hw, __fmt, ...) \
563 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
564
565 #ifdef __CSIO_DEBUG__
566 #define csio_dbg(__hw, __fmt, ...) \
567 csio_info((__hw), __fmt, ##__VA_ARGS__);
568 #else
569 #define csio_dbg(__hw, __fmt, ...)
570 #endif
571
572 int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
573 int, int, uint32_t *);
574 void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
575 unsigned int, unsigned int);
576 int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
577 void csio_hw_intr_disable(struct csio_hw *);
578 int csio_hw_slow_intr_handler(struct csio_hw *);
579 int csio_handle_intr_status(struct csio_hw *, unsigned int,
580 const struct intr_info *);
581
582 int csio_hw_start(struct csio_hw *);
583 int csio_hw_stop(struct csio_hw *);
584 int csio_hw_reset(struct csio_hw *);
585 int csio_is_hw_ready(struct csio_hw *);
586 int csio_is_hw_removing(struct csio_hw *);
587
588 int csio_fwevtq_handler(struct csio_hw *);
589 void csio_evtq_worker(struct work_struct *);
590 int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
591 void csio_evtq_flush(struct csio_hw *hw);
592
593 int csio_request_irqs(struct csio_hw *);
594 void csio_intr_enable(struct csio_hw *);
595 void csio_intr_disable(struct csio_hw *, bool);
596 void csio_hw_fatal_err(struct csio_hw *);
597
598 struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
599 int csio_config_queues(struct csio_hw *);
600
601 int csio_hw_init(struct csio_hw *);
602 void csio_hw_exit(struct csio_hw *);
603 #endif /* ifndef __CSIO_HW_H__ */
604