• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (c) 2014-2015 Hisilicon Limited.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #ifndef __HNS_DSAF_MAIN_H
11 #define __HNS_DSAF_MAIN_H
12 #include "hnae.h"
13 
14 #include "hns_dsaf_reg.h"
15 #include "hns_dsaf_mac.h"
16 
17 struct hns_mac_cb;
18 
19 #define DSAF_DRV_NAME "hns_dsaf"
20 #define DSAF_MOD_VERSION "v1.0"
21 #define DSAF_DEVICE_NAME "dsaf"
22 
23 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
24 
25 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/
26 
27 #define DSAF_MAX_CHIP_NUM 2  /*max 2 chips */
28 
29 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
30 
31 #define HNS_DSAF_MAX_DESC_CNT 1024
32 #define HNS_DSAF_MIN_DESC_CNT 16
33 
34 #define DSAF_INVALID_ENTRY_IDX 0xffff
35 
36 #define DSAF_CFG_READ_CNT   30
37 
38 #define MAC_NUM_OCTETS_PER_ADDR 6
39 
40 #define DSAF_DUMP_REGS_NUM 504
41 #define DSAF_STATIC_NUM 28
42 #define DSAF_V2_STATIC_NUM	44
43 #define DSAF_PRIO_NR	8
44 #define DSAF_REG_PER_ZONE	3
45 
46 #define DSAF_ROCE_CREDIT_CHN	8
47 #define DSAF_ROCE_CHAN_MODE	3
48 
49 enum dsaf_roce_port_mode {
50 	DSAF_ROCE_6PORT_MODE,
51 	DSAF_ROCE_4PORT_MODE,
52 	DSAF_ROCE_2PORT_MODE,
53 	DSAF_ROCE_CHAN_MODE_NUM,
54 };
55 
56 enum dsaf_roce_port_num {
57 	DSAF_ROCE_PORT_0,
58 	DSAF_ROCE_PORT_1,
59 	DSAF_ROCE_PORT_2,
60 	DSAF_ROCE_PORT_3,
61 	DSAF_ROCE_PORT_4,
62 	DSAF_ROCE_PORT_5,
63 };
64 
65 enum dsaf_roce_qos_sl {
66 	DSAF_ROCE_SL_0,
67 	DSAF_ROCE_SL_1,
68 	DSAF_ROCE_SL_2,
69 	DSAF_ROCE_SL_3,
70 };
71 
72 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
73 #define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP)
74 
75 enum hal_dsaf_mode {
76 	HRD_DSAF_NO_DSAF_MODE	= 0x0,
77 	HRD_DSAF_MODE		= 0x1,
78 };
79 
80 enum hal_dsaf_tc_mode {
81 	HRD_DSAF_4TC_MODE		= 0X0,
82 	HRD_DSAF_8TC_MODE		= 0X1,
83 };
84 
85 struct dsaf_vm_def_vlan {
86 	u32 vm_def_vlan_id;
87 	u32 vm_def_vlan_cfi;
88 	u32 vm_def_vlan_pri;
89 };
90 
91 struct dsaf_tbl_tcam_data {
92 	u32 tbl_tcam_data_high;
93 	u32 tbl_tcam_data_low;
94 };
95 
96 #define DSAF_PORT_MSK_NUM \
97 	((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
98 struct dsaf_tbl_tcam_mcast_cfg {
99 	u8 tbl_mcast_old_en;
100 	u8 tbl_mcast_item_vld;
101 	u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
102 };
103 
104 struct dsaf_tbl_tcam_ucast_cfg {
105 	u32 tbl_ucast_old_en;
106 	u32 tbl_ucast_item_vld;
107 	u32 tbl_ucast_mac_discard;
108 	u32 tbl_ucast_dvc;
109 	u32 tbl_ucast_out_port;
110 };
111 
112 struct dsaf_tbl_line_cfg {
113 	u32 tbl_line_mac_discard;
114 	u32 tbl_line_dvc;
115 	u32 tbl_line_out_port;
116 };
117 
118 enum dsaf_port_rate_mode {
119 	DSAF_PORT_RATE_1000 = 0,
120 	DSAF_PORT_RATE_2500,
121 	DSAF_PORT_RATE_10000
122 };
123 
124 enum dsaf_stp_port_type {
125 	DSAF_STP_PORT_TYPE_DISCARD = 0,
126 	DSAF_STP_PORT_TYPE_BLOCK = 1,
127 	DSAF_STP_PORT_TYPE_LISTEN = 2,
128 	DSAF_STP_PORT_TYPE_LEARN = 3,
129 	DSAF_STP_PORT_TYPE_FORWARD = 4
130 };
131 
132 enum dsaf_sw_port_type {
133 	DSAF_SW_PORT_TYPE_NON_VLAN = 0,
134 	DSAF_SW_PORT_TYPE_ACCESS = 1,
135 	DSAF_SW_PORT_TYPE_TRUNK = 2,
136 };
137 
138 #define DSAF_SUB_BASE_SIZE                        (0x10000)
139 
140 /* dsaf mode define */
141 enum dsaf_mode {
142 	DSAF_MODE_INVALID = 0,	/**< Invalid dsaf mode */
143 	DSAF_MODE_ENABLE_FIX,	/**< en DSAF-mode, fixed to queue*/
144 	DSAF_MODE_ENABLE_0VM,	/**< en DSAF-mode, support 0 VM */
145 	DSAF_MODE_ENABLE_8VM,	/**< en DSAF-mode, support 8 VM */
146 	DSAF_MODE_ENABLE_16VM,	/**< en DSAF-mode, support 16 VM */
147 	DSAF_MODE_ENABLE_32VM,	/**< en DSAF-mode, support 32 VM */
148 	DSAF_MODE_ENABLE_128VM,	/**< en DSAF-mode, support 128 VM */
149 	DSAF_MODE_ENABLE,		/**< before is enable DSAF mode*/
150 	DSAF_MODE_DISABLE_SP,	/* <non-dsaf, single port mode */
151 	DSAF_MODE_DISABLE_FIX,	/**< non-dasf, fixed to queue*/
152 	DSAF_MODE_DISABLE_2PORT_8VM,	/**< non-dasf, 2port 8VM */
153 	DSAF_MODE_DISABLE_2PORT_16VM,	/**< non-dasf, 2port 16VM */
154 	DSAF_MODE_DISABLE_2PORT_64VM,	/**< non-dasf, 2port 64VM */
155 	DSAF_MODE_DISABLE_6PORT_0VM,	/**< non-dasf, 6port 0VM */
156 	DSAF_MODE_DISABLE_6PORT_2VM,	/**< non-dasf, 6port 2VM */
157 	DSAF_MODE_DISABLE_6PORT_4VM,	/**< non-dasf, 6port 4VM */
158 	DSAF_MODE_DISABLE_6PORT_16VM,	/**< non-dasf, 6port 16VM */
159 	DSAF_MODE_MAX		/**< the last one, use as the num */
160 };
161 
162 #define DSAF_DEST_PORT_NUM 256	/* DSAF max port num */
163 #define DSAF_WORD_BIT_CNT 32  /* the num bit of word */
164 
165 /*mac entry, mc or uc entry*/
166 struct dsaf_drv_mac_single_dest_entry {
167 	/* mac addr, match the entry*/
168 	u8 addr[MAC_NUM_OCTETS_PER_ADDR];
169 	u16 in_vlan_id; /* value of VlanId */
170 
171 	/* the vld input port num, dsaf-mode fix 0, */
172 	/*	non-dasf is the entry whitch port vld*/
173 	u8 in_port_num;
174 
175 	u8 port_num; /*output port num*/
176 	u8 rsv[6];
177 };
178 
179 /*only mc entry*/
180 struct dsaf_drv_mac_multi_dest_entry {
181 	/* mac addr, match the entry*/
182 	u8 addr[MAC_NUM_OCTETS_PER_ADDR];
183 	u16 in_vlan_id;
184 	/* this mac addr output port,*/
185 	/*	bit0-bit5 means Port0-Port5(1bit is vld)**/
186 	u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
187 
188 	/* the vld input port num, dsaf-mode fix 0,*/
189 	/*	non-dasf is the entry whitch port vld*/
190 	u8 in_port_num;
191 	u8 rsv[7];
192 };
193 
194 struct dsaf_hw_stats {
195 	u64 pad_drop;
196 	u64 man_pkts;
197 	u64 rx_pkts;
198 	u64 rx_pkt_id;
199 	u64 rx_pause_frame;
200 	u64 release_buf_num;
201 	u64 sbm_drop;
202 	u64 crc_false;
203 	u64 bp_drop;
204 	u64 rslt_drop;
205 	u64 local_addr_false;
206 	u64 vlan_drop;
207 	u64 stp_drop;
208 	u64 rx_pfc[DSAF_PRIO_NR];
209 	u64 tx_pfc[DSAF_PRIO_NR];
210 	u64 tx_pkts;
211 };
212 
213 struct hnae_vf_cb {
214 	u8 port_index;
215 	struct hns_mac_cb *mac_cb;
216 	struct dsaf_device *dsaf_dev;
217 	struct hnae_handle  ae_handle; /* must be the last number */
218 };
219 
220 struct dsaf_int_xge_src {
221 	u32    xid_xge_ecc_err_int_src;
222 	u32    xid_xge_fsm_timout_int_src;
223 	u32    sbm_xge_lnk_fsm_timout_int_src;
224 	u32    sbm_xge_lnk_ecc_2bit_int_src;
225 	u32    sbm_xge_mib_req_failed_int_src;
226 	u32    sbm_xge_mib_req_fsm_timout_int_src;
227 	u32    sbm_xge_mib_rels_fsm_timout_int_src;
228 	u32    sbm_xge_sram_ecc_2bit_int_src;
229 	u32    sbm_xge_mib_buf_sum_err_int_src;
230 	u32    sbm_xge_mib_req_extra_int_src;
231 	u32    sbm_xge_mib_rels_extra_int_src;
232 	u32    voq_xge_start_to_over_0_int_src;
233 	u32    voq_xge_start_to_over_1_int_src;
234 	u32    voq_xge_ecc_err_int_src;
235 };
236 
237 struct dsaf_int_ppe_src {
238 	u32    xid_ppe_fsm_timout_int_src;
239 	u32    sbm_ppe_lnk_fsm_timout_int_src;
240 	u32    sbm_ppe_lnk_ecc_2bit_int_src;
241 	u32    sbm_ppe_mib_req_failed_int_src;
242 	u32    sbm_ppe_mib_req_fsm_timout_int_src;
243 	u32    sbm_ppe_mib_rels_fsm_timout_int_src;
244 	u32    sbm_ppe_sram_ecc_2bit_int_src;
245 	u32    sbm_ppe_mib_buf_sum_err_int_src;
246 	u32    sbm_ppe_mib_req_extra_int_src;
247 	u32    sbm_ppe_mib_rels_extra_int_src;
248 	u32    voq_ppe_start_to_over_0_int_src;
249 	u32    voq_ppe_ecc_err_int_src;
250 	u32    xod_ppe_fifo_rd_empty_int_src;
251 	u32    xod_ppe_fifo_wr_full_int_src;
252 };
253 
254 struct dsaf_int_rocee_src {
255 	u32    xid_rocee_fsm_timout_int_src;
256 	u32    sbm_rocee_lnk_fsm_timout_int_src;
257 	u32    sbm_rocee_lnk_ecc_2bit_int_src;
258 	u32    sbm_rocee_mib_req_failed_int_src;
259 	u32    sbm_rocee_mib_req_fsm_timout_int_src;
260 	u32    sbm_rocee_mib_rels_fsm_timout_int_src;
261 	u32    sbm_rocee_sram_ecc_2bit_int_src;
262 	u32    sbm_rocee_mib_buf_sum_err_int_src;
263 	u32    sbm_rocee_mib_req_extra_int_src;
264 	u32    sbm_rocee_mib_rels_extra_int_src;
265 	u32    voq_rocee_start_to_over_0_int_src;
266 	u32    voq_rocee_ecc_err_int_src;
267 };
268 
269 struct dsaf_int_tbl_src {
270 	u32    tbl_da0_mis_src;
271 	u32    tbl_da1_mis_src;
272 	u32    tbl_da2_mis_src;
273 	u32    tbl_da3_mis_src;
274 	u32    tbl_da4_mis_src;
275 	u32    tbl_da5_mis_src;
276 	u32    tbl_da6_mis_src;
277 	u32    tbl_da7_mis_src;
278 	u32    tbl_sa_mis_src;
279 	u32    tbl_old_sech_end_src;
280 	u32    lram_ecc_err1_src;
281 	u32    lram_ecc_err2_src;
282 	u32    tram_ecc_err1_src;
283 	u32    tram_ecc_err2_src;
284 	u32    tbl_ucast_bcast_xge0_src;
285 	u32    tbl_ucast_bcast_xge1_src;
286 	u32    tbl_ucast_bcast_xge2_src;
287 	u32    tbl_ucast_bcast_xge3_src;
288 	u32    tbl_ucast_bcast_xge4_src;
289 	u32    tbl_ucast_bcast_xge5_src;
290 	u32    tbl_ucast_bcast_ppe_src;
291 	u32    tbl_ucast_bcast_rocee_src;
292 };
293 
294 struct dsaf_int_stat {
295 	struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
296 	struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
297 	struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
298 	struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
299 
300 };
301 
302 struct dsaf_misc_op {
303 	void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status,
304 			     u16 speed, int data);
305 	void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
306 	int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
307 			       enum hnae_led_state status);
308 	/* reset series function, it will be reset if the dereset is 0 */
309 	void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
310 	void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
311 	void (*xge_core_srst)(struct dsaf_device *dsaf_dev, u32 port,
312 			      bool dereset);
313 	void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
314 	void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
315 	void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
316 	void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
317 				   bool dereset);
318 	void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);
319 
320 	phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
321 	int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
322 
323 	int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en);
324 };
325 
326 /* Dsaf device struct define ,and mac ->  dsaf */
327 struct dsaf_device {
328 	struct device *dev;
329 	struct hnae_ae_dev ae_dev;
330 
331 	u8 __iomem *sc_base;
332 	u8 __iomem *sds_base;
333 	u8 __iomem *ppe_base;
334 	u8 __iomem *io_base;
335 	struct regmap *sub_ctrl;
336 	phys_addr_t ppe_paddr;
337 
338 	u32 desc_num; /*  desc num per queue*/
339 	u32 buf_size; /*  ring buffer size */
340 	u32 reset_offset; /* reset field offset in sub sysctrl */
341 	int buf_size_type; /* ring buffer size-type */
342 	enum dsaf_mode dsaf_mode;	 /* dsaf mode  */
343 	enum hal_dsaf_mode dsaf_en;
344 	enum hal_dsaf_tc_mode dsaf_tc_mode;
345 	u32 dsaf_ver;
346 
347 	struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
348 	struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
349 	struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM];
350 	struct dsaf_misc_op *misc_op;
351 
352 	struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
353 	struct dsaf_int_stat int_stat;
354 	/* make sure tcam table config spinlock */
355 	spinlock_t tcam_lock;
356 };
357 
hns_dsaf_dev_priv(const struct dsaf_device * dsaf_dev)358 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
359 {
360 	return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
361 }
362 
363 struct dsaf_drv_tbl_tcam_key {
364 	union {
365 		struct {
366 			u8 mac_3;
367 			u8 mac_2;
368 			u8 mac_1;
369 			u8 mac_0;
370 		} bits;
371 
372 		u32 val;
373 	} high;
374 	union {
375 		struct {
376 			u32 port:4; /* port id, */
377 			/* dsaf-mode fixed 0, non-dsaf-mode port id*/
378 			u32 vlan:12; /* vlan id */
379 			u32 mac_5:8;
380 			u32 mac_4:8;
381 		} bits;
382 
383 		u32 val;
384 	} low;
385 };
386 
387 struct dsaf_drv_soft_mac_tbl {
388 	struct dsaf_drv_tbl_tcam_key tcam_key;
389 	u16 index; /*the entry's index in tcam tab*/
390 };
391 
392 struct dsaf_drv_priv {
393 	/* soft tab Mac key, for hardware tab*/
394 	struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
395 };
396 
hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device * dsaf_dev,u32 tab_tcam_addr)397 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
398 					      u32 tab_tcam_addr)
399 {
400 	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
401 			   DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
402 			   tab_tcam_addr);
403 }
404 
hns_dsaf_tbl_tcam_load_pul(struct dsaf_device * dsaf_dev)405 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
406 {
407 	u32 o_tbl_pul;
408 
409 	o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
410 	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
411 	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
412 	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
413 	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
414 }
415 
hns_dsaf_tbl_line_addr_cfg(struct dsaf_device * dsaf_dev,u32 tab_line_addr)416 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
417 					      u32 tab_line_addr)
418 {
419 	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
420 			   DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
421 			   tab_line_addr);
422 }
423 
hns_ae_get_vf_cb(struct hnae_handle * handle)424 static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
425 	struct hnae_handle *handle)
426 {
427 	return container_of(handle, struct hnae_vf_cb, ae_handle);
428 }
429 
430 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
431 			      struct dsaf_drv_mac_single_dest_entry *mac_entry);
432 int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev,
433 			      struct dsaf_drv_mac_multi_dest_entry *mac_entry);
434 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
435 			     struct dsaf_drv_mac_single_dest_entry *mac_entry);
436 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
437 			   u8 in_port_num, u8 *addr);
438 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
439 			     struct dsaf_drv_mac_single_dest_entry *mac_entry);
440 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
441 			      struct dsaf_drv_mac_single_dest_entry *mac_entry);
442 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
443 			      struct dsaf_drv_mac_multi_dest_entry *mac_entry);
444 int hns_dsaf_get_mac_entry_by_index(
445 	struct dsaf_device *dsaf_dev,
446 	u16 entry_index,
447 	struct dsaf_drv_mac_multi_dest_entry *mac_entry);
448 
449 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
450 
451 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
452 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
453 
454 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
455 
456 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset);
457 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
458 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
459 			  struct dsaf_device *dsaf_dev);
460 
461 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
462 int hns_dsaf_get_regs_count(void);
463 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
464 
465 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
466 				  u32 *en);
467 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
468 				 u32 en);
469 
470 #endif /* __HNS_DSAF_MAIN_H__ */
471