1 /* 2 * skl-tplg-interface.h - Intel DSP FW private data interface 3 * 4 * Copyright (C) 2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * Nilofer, Samreen <samreen.nilofer@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #ifndef __HDA_TPLG_INTERFACE_H__ 20 #define __HDA_TPLG_INTERFACE_H__ 21 22 /* 23 * Default types range from 0~12. type can range from 0 to 0xff 24 * SST types start at higher to avoid any overlapping in future 25 */ 26 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100 27 28 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/ 29 #define MAX_IN_QUEUE 8 30 #define MAX_OUT_QUEUE 8 31 32 #define SKL_UUID_STR_SZ 40 33 /* Event types goes here */ 34 /* Reserve event type 0 for no event handlers */ 35 enum skl_event_types { 36 SKL_EVENT_NONE = 0, 37 SKL_MIXER_EVENT, 38 SKL_MUX_EVENT, 39 SKL_VMIXER_EVENT, 40 SKL_PGA_EVENT 41 }; 42 43 /** 44 * enum skl_ch_cfg - channel configuration 45 * 46 * @SKL_CH_CFG_MONO: One channel only 47 * @SKL_CH_CFG_STEREO: L & R 48 * @SKL_CH_CFG_2_1: L, R & LFE 49 * @SKL_CH_CFG_3_0: L, C & R 50 * @SKL_CH_CFG_3_1: L, C, R & LFE 51 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs 52 * @SKL_CH_CFG_4_0: L, C, R & Cs 53 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs 54 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE 55 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two 56 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] 57 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] 58 * @SKL_CH_CFG_INVALID: Invalid 59 */ 60 enum skl_ch_cfg { 61 SKL_CH_CFG_MONO = 0, 62 SKL_CH_CFG_STEREO = 1, 63 SKL_CH_CFG_2_1 = 2, 64 SKL_CH_CFG_3_0 = 3, 65 SKL_CH_CFG_3_1 = 4, 66 SKL_CH_CFG_QUATRO = 5, 67 SKL_CH_CFG_4_0 = 6, 68 SKL_CH_CFG_5_0 = 7, 69 SKL_CH_CFG_5_1 = 8, 70 SKL_CH_CFG_DUAL_MONO = 9, 71 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, 72 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, 73 SKL_CH_CFG_4_CHANNEL = 12, 74 SKL_CH_CFG_INVALID 75 }; 76 77 enum skl_module_type { 78 SKL_MODULE_TYPE_MIXER = 0, 79 SKL_MODULE_TYPE_COPIER, 80 SKL_MODULE_TYPE_UPDWMIX, 81 SKL_MODULE_TYPE_SRCINT, 82 SKL_MODULE_TYPE_ALGO, 83 SKL_MODULE_TYPE_BASE_OUTFMT, 84 SKL_MODULE_TYPE_KPB, 85 }; 86 87 enum skl_core_affinity { 88 SKL_AFFINITY_CORE_0 = 0, 89 SKL_AFFINITY_CORE_1, 90 SKL_AFFINITY_CORE_MAX 91 }; 92 93 enum skl_pipe_conn_type { 94 SKL_PIPE_CONN_TYPE_NONE = 0, 95 SKL_PIPE_CONN_TYPE_FE, 96 SKL_PIPE_CONN_TYPE_BE 97 }; 98 99 enum skl_hw_conn_type { 100 SKL_CONN_NONE = 0, 101 SKL_CONN_SOURCE = 1, 102 SKL_CONN_SINK = 2 103 }; 104 105 enum skl_dev_type { 106 SKL_DEVICE_BT = 0x0, 107 SKL_DEVICE_DMIC = 0x1, 108 SKL_DEVICE_I2S = 0x2, 109 SKL_DEVICE_SLIMBUS = 0x3, 110 SKL_DEVICE_HDALINK = 0x4, 111 SKL_DEVICE_HDAHOST = 0x5, 112 SKL_DEVICE_NONE 113 }; 114 115 /** 116 * enum skl_interleaving - interleaving style 117 * 118 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN] 119 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN] 120 */ 121 enum skl_interleaving { 122 SKL_INTERLEAVING_PER_CHANNEL = 0, 123 SKL_INTERLEAVING_PER_SAMPLE = 1, 124 }; 125 126 enum skl_sample_type { 127 SKL_SAMPLE_TYPE_INT_MSB = 0, 128 SKL_SAMPLE_TYPE_INT_LSB = 1, 129 SKL_SAMPLE_TYPE_INT_SIGNED = 2, 130 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, 131 SKL_SAMPLE_TYPE_FLOAT = 4 132 }; 133 134 enum module_pin_type { 135 /* All pins of the module takes same PCM inputs or outputs 136 * e.g. mixout 137 */ 138 SKL_PIN_TYPE_HOMOGENEOUS, 139 /* All pins of the module takes different PCM inputs or outputs 140 * e.g mux 141 */ 142 SKL_PIN_TYPE_HETEROGENEOUS, 143 }; 144 145 enum skl_module_param_type { 146 SKL_PARAM_DEFAULT = 0, 147 SKL_PARAM_INIT, 148 SKL_PARAM_SET, 149 SKL_PARAM_BIND 150 }; 151 152 struct skl_dfw_algo_data { 153 u32 set_params:2; 154 u32 rsvd:30; 155 u32 param_id; 156 u32 max; 157 char params[0]; 158 } __packed; 159 160 #define LIB_NAME_LENGTH 128 161 #define HDA_MAX_LIB 16 162 163 struct lib_info { 164 char name[LIB_NAME_LENGTH]; 165 } __packed; 166 167 struct skl_dfw_manifest { 168 u32 lib_count; 169 struct lib_info lib[HDA_MAX_LIB]; 170 } __packed; 171 172 enum skl_tkn_dir { 173 SKL_DIR_IN, 174 SKL_DIR_OUT 175 }; 176 177 enum skl_tuple_type { 178 SKL_TYPE_TUPLE, 179 SKL_TYPE_DATA 180 }; 181 182 #endif 183