1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15 #define _HAL_INIT_C_
16
17 #include <linux/firmware.h>
18 #include <linux/vmalloc.h>
19 #include <drv_types.h>
20 #include <rtw_efuse.h>
21 #include <phy.h>
22 #include <rtl8188e_hal.h>
23
24 #include <rtw_iol.h>
25
iol_mode_enable(struct adapter * padapter,u8 enable)26 void iol_mode_enable(struct adapter *padapter, u8 enable)
27 {
28 u8 reg_0xf0 = 0;
29
30 if (enable) {
31 /* Enable initial offload */
32 reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
33 usb_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
34
35 if (!padapter->bFWReady) {
36 DBG_88E("bFWReady == false call reset 8051...\n");
37 _8051Reset88E(padapter);
38 }
39
40 } else {
41 /* disable initial offload */
42 reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
43 usb_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
44 }
45 }
46
iol_execute(struct adapter * padapter,u8 control)47 s32 iol_execute(struct adapter *padapter, u8 control)
48 {
49 s32 status = _FAIL;
50 u8 reg_0x88 = 0;
51 unsigned long start = 0;
52
53 control = control&0x0f;
54 reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
55 usb_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
56
57 start = jiffies;
58 while ((reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0)) & control &&
59 jiffies_to_msecs(jiffies - start) < 1000) {
60 udelay(5);
61 }
62
63 reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
64 status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
65 if (reg_0x88 & control<<4)
66 status = _FAIL;
67 return status;
68 }
69
iol_InitLLTTable(struct adapter * padapter,u8 txpktbuf_bndy)70 static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
71 {
72 s32 rst = _SUCCESS;
73 iol_mode_enable(padapter, 1);
74 usb_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
75 rst = iol_execute(padapter, CMD_INIT_LLT);
76 iol_mode_enable(padapter, 0);
77 return rst;
78 }
79
80
rtl8188e_iol_efuse_patch(struct adapter * padapter)81 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
82 {
83 s32 result = _SUCCESS;
84
85 DBG_88E("==> %s\n", __func__);
86 if (rtw_IOL_applied(padapter)) {
87 iol_mode_enable(padapter, 1);
88 result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
89 if (result == _SUCCESS)
90 result = iol_execute(padapter, CMD_EFUSE_PATCH);
91
92 iol_mode_enable(padapter, 0);
93 }
94 return result;
95 }
96
97 #define MAX_REG_BOLCK_SIZE 196
98
_8051Reset88E(struct adapter * padapter)99 void _8051Reset88E(struct adapter *padapter)
100 {
101 u8 u1bTmp;
102
103 u1bTmp = usb_read8(padapter, REG_SYS_FUNC_EN+1);
104 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2)));
105 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2)));
106 DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
107 }
108
rtl8188e_InitializeFirmwareVars(struct adapter * padapter)109 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter)
110 {
111 /* Init Fw LPS related. */
112 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
113
114 /* Init H2C counter. by tynli. 2009.12.09. */
115 padapter->HalData->LastHMEBoxNum = 0;
116 }
117
rtw_hal_free_data(struct adapter * padapter)118 void rtw_hal_free_data(struct adapter *padapter)
119 {
120 kfree(padapter->HalData);
121 padapter->HalData = NULL;
122 }
123
rtw_hal_read_chip_version(struct adapter * padapter)124 void rtw_hal_read_chip_version(struct adapter *padapter)
125 {
126 u32 value32;
127 struct HAL_VERSION ChipVersion;
128 struct hal_data_8188e *pHalData = padapter->HalData;
129
130 value32 = usb_read32(padapter, REG_SYS_CFG);
131 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
132 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
133 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
134
135 dump_chip_info(ChipVersion);
136
137 pHalData->VersionID = ChipVersion;
138 pHalData->NumTotalRFPath = 1;
139 }
140
rtw_hal_set_odm_var(struct adapter * Adapter,enum hal_odm_variable eVariable,void * pValue1,bool bSet)141 void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
142 {
143 struct odm_dm_struct *podmpriv = &Adapter->HalData->odmpriv;
144
145 switch (eVariable) {
146 case HAL_ODM_STA_INFO:
147 {
148 struct sta_info *psta = pValue1;
149
150 if (bSet) {
151 DBG_88E("### Set STA_(%d) info\n", psta->mac_id);
152 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
153 ODM_RAInfo_Init(podmpriv, psta->mac_id);
154 } else {
155 DBG_88E("### Clean STA_(%d) info\n", psta->mac_id);
156 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
157 }
158 }
159 break;
160 case HAL_ODM_P2P_STATE:
161 podmpriv->bWIFI_Direct = bSet;
162 break;
163 case HAL_ODM_WIFI_DISPLAY_STATE:
164 podmpriv->bWIFI_Display = bSet;
165 break;
166 default:
167 break;
168 }
169 }
170
rtw_hal_notch_filter(struct adapter * adapter,bool enable)171 void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
172 {
173 if (enable) {
174 DBG_88E("Enable notch filter\n");
175 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1));
176 } else {
177 DBG_88E("Disable notch filter\n");
178 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1));
179 }
180 }
181
182 /* */
183 /* */
184 /* LLT R/W/Init function */
185 /* */
186 /* */
_LLTWrite(struct adapter * padapter,u32 address,u32 data)187 static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
188 {
189 s32 status = _SUCCESS;
190 s32 count = 0;
191 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
192 u16 LLTReg = REG_LLT_INIT;
193
194 usb_write32(padapter, LLTReg, value);
195
196 /* polling */
197 do {
198 value = usb_read32(padapter, LLTReg);
199 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
200 break;
201
202 if (count > POLLING_LLT_THRESHOLD) {
203 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
204 status = _FAIL;
205 break;
206 }
207 udelay(5);
208 } while (count++);
209
210 return status;
211 }
212
InitLLTTable(struct adapter * padapter,u8 txpktbuf_bndy)213 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
214 {
215 s32 status = _FAIL;
216 u32 i;
217 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
218
219 if (rtw_IOL_applied(padapter)) {
220 status = iol_InitLLTTable(padapter, txpktbuf_bndy);
221 } else {
222 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
223 status = _LLTWrite(padapter, i, i + 1);
224 if (_SUCCESS != status)
225 return status;
226 }
227
228 /* end of list */
229 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
230 if (_SUCCESS != status)
231 return status;
232
233 /* Make the other pages as ring buffer */
234 /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
235 /* Otherwise used as local loopback buffer. */
236 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
237 status = _LLTWrite(padapter, i, (i + 1));
238 if (_SUCCESS != status)
239 return status;
240 }
241
242 /* Let last entry point to the start entry of ring buffer */
243 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
244 if (_SUCCESS != status) {
245 return status;
246 }
247 }
248
249 return status;
250 }
251
252 void
Hal_InitPGData88E(struct adapter * padapter)253 Hal_InitPGData88E(struct adapter *padapter)
254 {
255 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
256
257 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
258 if (!is_boot_from_eeprom(padapter)) {
259 /* Read EFUSE real map to shadow. */
260 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
261 }
262 } else {/* autoload fail */
263 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
264 /* update to default value 0xFF */
265 if (!is_boot_from_eeprom(padapter))
266 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
267 }
268 }
269
270 void
Hal_EfuseParseIDCode88E(struct adapter * padapter,u8 * hwinfo)271 Hal_EfuseParseIDCode88E(
272 struct adapter *padapter,
273 u8 *hwinfo
274 )
275 {
276 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
277 u16 EEPROMId;
278
279 /* Checl 0x8129 again for making sure autoload status!! */
280 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
281 if (EEPROMId != RTL_EEPROM_ID) {
282 DBG_88E("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
283 pEEPROM->bautoload_fail_flag = true;
284 } else {
285 pEEPROM->bautoload_fail_flag = false;
286 }
287
288 DBG_88E("EEPROM ID = 0x%04x\n", EEPROMId);
289 }
290
Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g * pwrInfo24G,u8 * PROMContent,bool AutoLoadFail)291 static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
292 {
293 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
294
295 memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
296
297 if (AutoLoadFail) {
298 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
299 /* 2.4G default value */
300 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
301 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
302 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
303 }
304 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
305 if (TxCount == 0) {
306 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
307 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
308 } else {
309 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
310 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
311 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
312 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
313 }
314 }
315 }
316 return;
317 }
318
319 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
320 /* 2.4G default value */
321 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
322 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
323 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
324 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
325 }
326 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
327 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
328 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
329 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
330 }
331 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
332 if (TxCount == 0) {
333 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
334 if (PROMContent[eeAddr] == 0xFF) {
335 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
336 } else {
337 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
338 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
339 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
340 }
341
342 if (PROMContent[eeAddr] == 0xFF) {
343 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
344 } else {
345 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
346 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
347 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
348 }
349 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
350 eeAddr++;
351 } else {
352 if (PROMContent[eeAddr] == 0xFF) {
353 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
354 } else {
355 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
356 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
357 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
358 }
359
360 if (PROMContent[eeAddr] == 0xFF) {
361 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
362 } else {
363 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
364 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
365 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
366 }
367 eeAddr++;
368
369 if (PROMContent[eeAddr] == 0xFF) {
370 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
371 } else {
372 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
373 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
374 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
375 }
376
377 if (PROMContent[eeAddr] == 0xFF) {
378 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
379 } else {
380 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
381 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
382 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
383 }
384 eeAddr++;
385 }
386 }
387 }
388 }
389
Hal_GetChnlGroup88E(u8 chnl,u8 * pGroup)390 static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup)
391 {
392 u8 bIn24G = true;
393
394 if (chnl <= 14) {
395 bIn24G = true;
396
397 if (chnl < 3) /* Channel 1-2 */
398 *pGroup = 0;
399 else if (chnl < 6) /* Channel 3-5 */
400 *pGroup = 1;
401 else if (chnl < 9) /* Channel 6-8 */
402 *pGroup = 2;
403 else if (chnl < 12) /* Channel 9-11 */
404 *pGroup = 3;
405 else if (chnl < 14) /* Channel 12-13 */
406 *pGroup = 4;
407 else if (chnl == 14) /* Channel 14 */
408 *pGroup = 5;
409 } else {
410
411 /* probably, this branch is suitable only for 5 GHz */
412
413 bIn24G = false;
414
415 if (chnl <= 40)
416 *pGroup = 0;
417 else if (chnl <= 48)
418 *pGroup = 1;
419 else if (chnl <= 56)
420 *pGroup = 2;
421 else if (chnl <= 64)
422 *pGroup = 3;
423 else if (chnl <= 104)
424 *pGroup = 4;
425 else if (chnl <= 112)
426 *pGroup = 5;
427 else if (chnl <= 120)
428 *pGroup = 5;
429 else if (chnl <= 128)
430 *pGroup = 6;
431 else if (chnl <= 136)
432 *pGroup = 7;
433 else if (chnl <= 144)
434 *pGroup = 8;
435 else if (chnl <= 153)
436 *pGroup = 9;
437 else if (chnl <= 161)
438 *pGroup = 10;
439 else if (chnl <= 177)
440 *pGroup = 11;
441 }
442 return bIn24G;
443 }
444
Hal_ReadPowerSavingMode88E(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)445 void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
446 {
447 if (AutoLoadFail) {
448 padapter->pwrctrlpriv.bHWPowerdown = false;
449 padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
450 } else {
451 /* hw power down mode selection , 0:rf-off / 1:power down */
452
453 if (padapter->registrypriv.hwpdn_mode == 2)
454 padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4));
455 else
456 padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
457
458 /* decide hw if support remote wakeup function */
459 /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
460 padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false;
461
462 DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
463 padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown , padapter->pwrctrlpriv.bSupportRemoteWakeup);
464
465 DBG_88E("### PS params => power_mgnt(%x), usbss_enable(%x) ###\n", padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
466 }
467 }
468
Hal_ReadTxPowerInfo88E(struct adapter * padapter,u8 * PROMContent,bool AutoLoadFail)469 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
470 {
471 struct hal_data_8188e *pHalData = padapter->HalData;
472 struct txpowerinfo24g pwrInfo24G;
473 u8 rfPath, ch, group;
474 u8 bIn24G, TxCount;
475
476 Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
477
478 if (!AutoLoadFail)
479 pHalData->bTXPowerDataReadFromEEPORM = true;
480
481 for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) {
482 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
483 bIn24G = Hal_GetChnlGroup88E(ch, &group);
484 if (bIn24G) {
485 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
486 if (ch == 14)
487 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4];
488 else
489 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
490 }
491 if (bIn24G) {
492 DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch);
493 DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_CCK_Base[rfPath][ch]);
494 DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_BW40_Base[rfPath][ch]);
495 }
496 }
497 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
498 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
499 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
500 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
501 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
502 DBG_88E("======= TxCount %d =======\n", TxCount);
503 DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]);
504 DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]);
505 DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]);
506 DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]);
507 }
508 }
509
510 /* 2010/10/19 MH Add Regulator recognize for CU. */
511 if (!AutoLoadFail) {
512 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */
513 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
514 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
515 } else {
516 pHalData->EEPROMRegulatory = 0;
517 }
518 DBG_88E("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
519 }
520
Hal_EfuseParseXtal_8188E(struct adapter * pAdapter,u8 * hwinfo,bool AutoLoadFail)521 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
522 {
523 struct hal_data_8188e *pHalData = pAdapter->HalData;
524
525 if (!AutoLoadFail) {
526 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
527 if (pHalData->CrystalCap == 0xFF)
528 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
529 } else {
530 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
531 }
532 DBG_88E("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
533 }
534
Hal_EfuseParseBoardType88E(struct adapter * pAdapter,u8 * hwinfo,bool AutoLoadFail)535 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
536 {
537 struct hal_data_8188e *pHalData = pAdapter->HalData;
538
539 if (!AutoLoadFail)
540 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_88E]
541 & 0xE0) >> 5;
542 else
543 pHalData->BoardType = 0;
544 DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType);
545 }
546
Hal_EfuseParseEEPROMVer88E(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)547 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
548 {
549 struct hal_data_8188e *pHalData = padapter->HalData;
550
551 if (!AutoLoadFail) {
552 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
553 if (pHalData->EEPROMVersion == 0xFF)
554 pHalData->EEPROMVersion = EEPROM_Default_Version;
555 } else {
556 pHalData->EEPROMVersion = 1;
557 }
558 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
559 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
560 pHalData->EEPROMVersion));
561 }
562
rtl8188e_EfuseParseChnlPlan(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)563 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
564 {
565 padapter->mlmepriv.ChannelPlan =
566 hal_com_get_channel_plan(padapter,
567 hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
568 padapter->registrypriv.channel_plan,
569 RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
570
571 DBG_88E("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
572 }
573
Hal_EfuseParseCustomerID88E(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)574 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
575 {
576 struct hal_data_8188e *pHalData = padapter->HalData;
577
578 if (!AutoLoadFail) {
579 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
580 } else {
581 pHalData->EEPROMCustomerID = 0;
582 pHalData->EEPROMSubCustomerID = 0;
583 }
584 DBG_88E("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
585 }
586
Hal_ReadAntennaDiversity88E(struct adapter * pAdapter,u8 * PROMContent,bool AutoLoadFail)587 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
588 {
589 struct hal_data_8188e *pHalData = pAdapter->HalData;
590 struct registry_priv *registry_par = &pAdapter->registrypriv;
591
592 if (!AutoLoadFail) {
593 /* Antenna Diversity setting. */
594 if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
595 pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
596 if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
597 pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;
598 } else {
599 pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
600 }
601
602 if (registry_par->antdiv_type == 0) {
603 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
604 pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
605 if (pHalData->TRxAntDivType == 0xFF)
606 pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
607 } else {
608 pHalData->TRxAntDivType = registry_par->antdiv_type;
609 }
610
611 if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
612 pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
613 } else {
614 pHalData->AntDivCfg = 0;
615 pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */
616 }
617 DBG_88E("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n", pHalData->AntDivCfg, pHalData->TRxAntDivType);
618 }
619
Hal_ReadThermalMeter_88E(struct adapter * Adapter,u8 * PROMContent,bool AutoloadFail)620 void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
621 {
622 struct hal_data_8188e *pHalData = Adapter->HalData;
623
624 /* ThermalMeter from EEPROM */
625 if (!AutoloadFail)
626 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
627 else
628 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
629
630 if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) {
631 pHalData->bAPKThermalMeterIgnore = true;
632 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
633 }
634 DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
635 }
636