1 #ifndef MDP5_XML
2 #define MDP5_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-05-10 05:06:30)
12 - /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
13 - /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55)
14
15 Copyright (C) 2013-2016 by the following authors:
16 - Rob Clark <robdclark@gmail.com> (robclark)
17 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
18
19 Permission is hereby granted, free of charge, to any person obtaining
20 a copy of this software and associated documentation files (the
21 "Software"), to deal in the Software without restriction, including
22 without limitation the rights to use, copy, modify, merge, publish,
23 distribute, sublicense, and/or sell copies of the Software, and to
24 permit persons to whom the Software is furnished to do so, subject to
25 the following conditions:
26
27 The above copyright notice and this permission notice (including the
28 next paragraph) shall be included in all copies or substantial
29 portions of the Software.
30
31 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
34 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
35 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
36 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
38 */
39
40
41 enum mdp5_intf_type {
42 INTF_DISABLED = 0,
43 INTF_DSI = 1,
44 INTF_HDMI = 3,
45 INTF_LCDC = 5,
46 INTF_eDP = 9,
47 INTF_VIRTUAL = 100,
48 INTF_WB = 101,
49 };
50
51 enum mdp5_intfnum {
52 NO_INTF = 0,
53 INTF0 = 1,
54 INTF1 = 2,
55 INTF2 = 3,
56 INTF3 = 4,
57 };
58
59 enum mdp5_pipe {
60 SSPP_VIG0 = 0,
61 SSPP_VIG1 = 1,
62 SSPP_VIG2 = 2,
63 SSPP_RGB0 = 3,
64 SSPP_RGB1 = 4,
65 SSPP_RGB2 = 5,
66 SSPP_DMA0 = 6,
67 SSPP_DMA1 = 7,
68 SSPP_VIG3 = 8,
69 SSPP_RGB3 = 9,
70 };
71
72 enum mdp5_ctl_mode {
73 MODE_NONE = 0,
74 MODE_WB_0_BLOCK = 1,
75 MODE_WB_1_BLOCK = 2,
76 MODE_WB_0_LINE = 3,
77 MODE_WB_1_LINE = 4,
78 MODE_WB_2_LINE = 5,
79 };
80
81 enum mdp5_pack_3d {
82 PACK_3D_FRAME_INT = 0,
83 PACK_3D_H_ROW_INT = 1,
84 PACK_3D_V_ROW_INT = 2,
85 PACK_3D_COL_INT = 3,
86 };
87
88 enum mdp5_scale_filter {
89 SCALE_FILTER_NEAREST = 0,
90 SCALE_FILTER_BIL = 1,
91 SCALE_FILTER_PCMN = 2,
92 SCALE_FILTER_CA = 3,
93 };
94
95 enum mdp5_pipe_bwc {
96 BWC_LOSSLESS = 0,
97 BWC_Q_HIGH = 1,
98 BWC_Q_MED = 2,
99 };
100
101 enum mdp5_cursor_format {
102 CURSOR_FMT_ARGB8888 = 0,
103 CURSOR_FMT_ARGB1555 = 2,
104 CURSOR_FMT_ARGB4444 = 4,
105 };
106
107 enum mdp5_cursor_alpha {
108 CURSOR_ALPHA_CONST = 0,
109 CURSOR_ALPHA_PER_PIXEL = 2,
110 };
111
112 enum mdp5_igc_type {
113 IGC_VIG = 0,
114 IGC_RGB = 1,
115 IGC_DMA = 2,
116 IGC_DSPP = 3,
117 };
118
119 enum mdp5_data_format {
120 DATA_FORMAT_RGB = 0,
121 DATA_FORMAT_YUV = 1,
122 };
123
124 enum mdp5_block_size {
125 BLOCK_SIZE_64 = 0,
126 BLOCK_SIZE_128 = 1,
127 };
128
129 enum mdp5_rotate_mode {
130 ROTATE_0 = 0,
131 ROTATE_90 = 1,
132 };
133
134 enum mdp5_chroma_downsample_method {
135 DS_MTHD_NO_PIXEL_DROP = 0,
136 DS_MTHD_PIXEL_DROP = 1,
137 };
138
139 #define MDP5_IRQ_WB_0_DONE 0x00000001
140 #define MDP5_IRQ_WB_1_DONE 0x00000002
141 #define MDP5_IRQ_WB_2_DONE 0x00000010
142 #define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
143 #define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
144 #define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
145 #define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
146 #define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
147 #define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
148 #define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
149 #define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
150 #define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
151 #define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
152 #define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
153 #define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
154 #define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
155 #define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
156 #define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
157 #define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
158 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
159 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
160 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
161 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
162 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
163 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
164 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
165 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
166 #define REG_MDSS_HW_VERSION 0x00000000
167 #define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
168 #define MDSS_HW_VERSION_STEP__SHIFT 0
MDSS_HW_VERSION_STEP(uint32_t val)169 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
170 {
171 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
172 }
173 #define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
174 #define MDSS_HW_VERSION_MINOR__SHIFT 16
MDSS_HW_VERSION_MINOR(uint32_t val)175 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
176 {
177 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
178 }
179 #define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
180 #define MDSS_HW_VERSION_MAJOR__SHIFT 28
MDSS_HW_VERSION_MAJOR(uint32_t val)181 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
182 {
183 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
184 }
185
186 #define REG_MDSS_HW_INTR_STATUS 0x00000010
187 #define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
188 #define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
189 #define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
190 #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
191 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
192
193 #define REG_MDP5_HW_VERSION 0x00000000
194 #define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
195 #define MDP5_HW_VERSION_STEP__SHIFT 0
MDP5_HW_VERSION_STEP(uint32_t val)196 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
197 {
198 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
199 }
200 #define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
201 #define MDP5_HW_VERSION_MINOR__SHIFT 16
MDP5_HW_VERSION_MINOR(uint32_t val)202 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
203 {
204 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
205 }
206 #define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
207 #define MDP5_HW_VERSION_MAJOR__SHIFT 28
MDP5_HW_VERSION_MAJOR(uint32_t val)208 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
209 {
210 return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
211 }
212
213 #define REG_MDP5_DISP_INTF_SEL 0x00000004
214 #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
215 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)216 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
217 {
218 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
219 }
220 #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
221 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)222 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
223 {
224 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
225 }
226 #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
227 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)228 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
229 {
230 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
231 }
232 #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
233 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)234 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
235 {
236 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
237 }
238
239 #define REG_MDP5_INTR_EN 0x00000010
240
241 #define REG_MDP5_INTR_STATUS 0x00000014
242
243 #define REG_MDP5_INTR_CLEAR 0x00000018
244
245 #define REG_MDP5_HIST_INTR_EN 0x0000001c
246
247 #define REG_MDP5_HIST_INTR_STATUS 0x00000020
248
249 #define REG_MDP5_HIST_INTR_CLEAR 0x00000024
250
251 #define REG_MDP5_SPARE_0 0x00000028
252 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
253
REG_MDP5_SMP_ALLOC_W(uint32_t i0)254 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
255
REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0)256 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
257 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
258 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)259 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
260 {
261 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
262 }
263 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
264 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)265 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
266 {
267 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
268 }
269 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
270 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)271 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
272 {
273 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
274 }
275
REG_MDP5_SMP_ALLOC_R(uint32_t i0)276 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
277
REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0)278 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
279 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
280 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)281 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
282 {
283 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
284 }
285 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
286 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)287 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
288 {
289 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
290 }
291 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
292 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)293 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
294 {
295 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
296 }
297
__offset_IGC(enum mdp5_igc_type idx)298 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
299 {
300 switch (idx) {
301 case IGC_VIG: return 0x00000200;
302 case IGC_RGB: return 0x00000210;
303 case IGC_DMA: return 0x00000220;
304 case IGC_DSPP: return 0x00000300;
305 default: return INVALID_IDX(idx);
306 }
307 }
REG_MDP5_IGC(enum mdp5_igc_type i0)308 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
309
REG_MDP5_IGC_LUT(enum mdp5_igc_type i0,uint32_t i1)310 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
311
REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0,uint32_t i1)312 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
313 #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
314 #define MDP5_IGC_LUT_REG_VAL__SHIFT 0
MDP5_IGC_LUT_REG_VAL(uint32_t val)315 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
316 {
317 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
318 }
319 #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
320 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
321 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
322 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
323
324 #define REG_MDP5_SPLIT_DPL_EN 0x000002f4
325
326 #define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
327 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
328 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
329 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
330 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
331
332 #define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
333 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
334 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
335 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
336 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
337
__offset_CTL(uint32_t idx)338 static inline uint32_t __offset_CTL(uint32_t idx)
339 {
340 switch (idx) {
341 case 0: return (mdp5_cfg->ctl.base[0]);
342 case 1: return (mdp5_cfg->ctl.base[1]);
343 case 2: return (mdp5_cfg->ctl.base[2]);
344 case 3: return (mdp5_cfg->ctl.base[3]);
345 case 4: return (mdp5_cfg->ctl.base[4]);
346 default: return INVALID_IDX(idx);
347 }
348 }
REG_MDP5_CTL(uint32_t i0)349 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
350
__offset_LAYER(uint32_t idx)351 static inline uint32_t __offset_LAYER(uint32_t idx)
352 {
353 switch (idx) {
354 case 0: return 0x00000000;
355 case 1: return 0x00000004;
356 case 2: return 0x00000008;
357 case 3: return 0x0000000c;
358 case 4: return 0x00000010;
359 case 5: return 0x00000024;
360 default: return INVALID_IDX(idx);
361 }
362 }
REG_MDP5_CTL_LAYER(uint32_t i0,uint32_t i1)363 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
364
REG_MDP5_CTL_LAYER_REG(uint32_t i0,uint32_t i1)365 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
366 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
367 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
MDP5_CTL_LAYER_REG_VIG0(uint32_t val)368 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
369 {
370 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
371 }
372 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
373 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
MDP5_CTL_LAYER_REG_VIG1(uint32_t val)374 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
375 {
376 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
377 }
378 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
379 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
MDP5_CTL_LAYER_REG_VIG2(uint32_t val)380 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
381 {
382 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
383 }
384 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
385 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
MDP5_CTL_LAYER_REG_RGB0(uint32_t val)386 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
387 {
388 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
389 }
390 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
391 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
MDP5_CTL_LAYER_REG_RGB1(uint32_t val)392 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
393 {
394 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
395 }
396 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
397 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
MDP5_CTL_LAYER_REG_RGB2(uint32_t val)398 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
399 {
400 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
401 }
402 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
403 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
MDP5_CTL_LAYER_REG_DMA0(uint32_t val)404 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
405 {
406 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
407 }
408 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
409 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
MDP5_CTL_LAYER_REG_DMA1(uint32_t val)410 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
411 {
412 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
413 }
414 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
415 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
416 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
417 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
MDP5_CTL_LAYER_REG_VIG3(uint32_t val)418 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
419 {
420 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
421 }
422 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
423 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
MDP5_CTL_LAYER_REG_RGB3(uint32_t val)424 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
425 {
426 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
427 }
428
REG_MDP5_CTL_OP(uint32_t i0)429 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
430 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
431 #define MDP5_CTL_OP_MODE__SHIFT 0
MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)432 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
433 {
434 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
435 }
436 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
437 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)438 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
439 {
440 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
441 }
442 #define MDP5_CTL_OP_CMD_MODE 0x00020000
443 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
444 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
445 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)446 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
447 {
448 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
449 }
450
REG_MDP5_CTL_FLUSH(uint32_t i0)451 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
452 #define MDP5_CTL_FLUSH_VIG0 0x00000001
453 #define MDP5_CTL_FLUSH_VIG1 0x00000002
454 #define MDP5_CTL_FLUSH_VIG2 0x00000004
455 #define MDP5_CTL_FLUSH_RGB0 0x00000008
456 #define MDP5_CTL_FLUSH_RGB1 0x00000010
457 #define MDP5_CTL_FLUSH_RGB2 0x00000020
458 #define MDP5_CTL_FLUSH_LM0 0x00000040
459 #define MDP5_CTL_FLUSH_LM1 0x00000080
460 #define MDP5_CTL_FLUSH_LM2 0x00000100
461 #define MDP5_CTL_FLUSH_LM3 0x00000200
462 #define MDP5_CTL_FLUSH_LM4 0x00000400
463 #define MDP5_CTL_FLUSH_DMA0 0x00000800
464 #define MDP5_CTL_FLUSH_DMA1 0x00001000
465 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
466 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
467 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
468 #define MDP5_CTL_FLUSH_WB 0x00010000
469 #define MDP5_CTL_FLUSH_CTL 0x00020000
470 #define MDP5_CTL_FLUSH_VIG3 0x00040000
471 #define MDP5_CTL_FLUSH_RGB3 0x00080000
472 #define MDP5_CTL_FLUSH_LM5 0x00100000
473 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
474 #define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
475 #define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
476 #define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
477 #define MDP5_CTL_FLUSH_TIMING_3 0x10000000
478 #define MDP5_CTL_FLUSH_TIMING_2 0x20000000
479 #define MDP5_CTL_FLUSH_TIMING_1 0x40000000
480 #define MDP5_CTL_FLUSH_TIMING_0 0x80000000
481
REG_MDP5_CTL_START(uint32_t i0)482 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
483
REG_MDP5_CTL_PACK_3D(uint32_t i0)484 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
485
__offset_LAYER_EXT(uint32_t idx)486 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
487 {
488 switch (idx) {
489 case 0: return 0x00000040;
490 case 1: return 0x00000044;
491 case 2: return 0x00000048;
492 case 3: return 0x0000004c;
493 case 4: return 0x00000050;
494 case 5: return 0x00000054;
495 default: return INVALID_IDX(idx);
496 }
497 }
REG_MDP5_CTL_LAYER_EXT(uint32_t i0,uint32_t i1)498 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
499
REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0,uint32_t i1)500 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
501 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
502 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
503 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
504 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
505 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
506 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
507 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
508 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
509 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
510 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
511 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
512 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)513 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
514 {
515 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
516 }
517 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
518 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)519 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
520 {
521 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
522 }
523
__offset_PIPE(enum mdp5_pipe idx)524 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
525 {
526 switch (idx) {
527 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
528 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
529 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
530 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
531 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
532 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
533 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
534 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
535 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
536 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
537 default: return INVALID_IDX(idx);
538 }
539 }
REG_MDP5_PIPE(enum mdp5_pipe i0)540 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
541
REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0)542 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
543 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
544 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)545 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
546 {
547 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
548 }
549 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
550 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)551 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
552 {
553 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
554 }
555 #define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
556
REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0)557 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
558
REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0)559 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
560
REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0)561 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
562
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0)563 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
564 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
565 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)566 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
567 {
568 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
569 }
570 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
571 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)572 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
573 {
574 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
575 }
576
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0)577 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
578 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
579 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)580 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
581 {
582 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
583 }
584 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
585 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)586 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
587 {
588 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
589 }
590
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0)591 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
592 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
593 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)594 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
595 {
596 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
597 }
598 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
599 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)600 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
601 {
602 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
603 }
604
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0)605 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
606 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
607 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)608 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
609 {
610 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
611 }
612 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
613 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)614 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
615 {
616 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
617 }
618
REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0)619 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
620 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
621 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)622 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
623 {
624 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
625 }
626
REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0,uint32_t i1)627 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
628
REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0,uint32_t i1)629 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
630 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
631 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)632 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
633 {
634 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
635 }
636 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
637 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)638 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
639 {
640 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
641 }
642
REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0,uint32_t i1)643 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
644
REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0,uint32_t i1)645 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
646 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
647 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)648 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
649 {
650 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
651 }
652 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
653 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)654 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
655 {
656 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
657 }
658
REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0,uint32_t i1)659 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
660
REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0,uint32_t i1)661 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
662 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
663 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)664 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
665 {
666 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
667 }
668
REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0,uint32_t i1)669 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
670
REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0,uint32_t i1)671 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
672 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
673 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)674 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
675 {
676 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
677 }
678
REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0)679 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
680 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
681 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)682 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
683 {
684 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
685 }
686 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
687 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)688 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
689 {
690 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
691 }
692
REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0)693 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
694 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
695 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)696 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
697 {
698 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
699 }
700 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
701 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)702 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
703 {
704 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
705 }
706
REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0)707 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
708 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
709 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
MDP5_PIPE_SRC_XY_Y(uint32_t val)710 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
711 {
712 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
713 }
714 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
715 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
MDP5_PIPE_SRC_XY_X(uint32_t val)716 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
717 {
718 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
719 }
720
REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0)721 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
722 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
723 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)724 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
725 {
726 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
727 }
728 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
729 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)730 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
731 {
732 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
733 }
734
REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0)735 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
736 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
737 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
MDP5_PIPE_OUT_XY_Y(uint32_t val)738 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
739 {
740 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
741 }
742 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
743 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
MDP5_PIPE_OUT_XY_X(uint32_t val)744 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
745 {
746 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
747 }
748
REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0)749 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
750
REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0)751 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
752
REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0)753 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
754
REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0)755 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
756
REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0)757 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
758 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
759 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)760 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
761 {
762 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
763 }
764 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
765 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)766 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
767 {
768 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
769 }
770
REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0)771 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
772 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
773 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)774 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
775 {
776 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
777 }
778 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
779 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)780 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
781 {
782 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
783 }
784
REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0)785 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
786
REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0)787 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
788 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
789 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)790 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
791 {
792 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
793 }
794 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
795 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)796 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
797 {
798 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
799 }
800 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
801 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)802 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
803 {
804 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
805 }
806 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
807 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)808 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
809 {
810 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
811 }
812 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
813 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
814 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)815 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
816 {
817 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
818 }
819 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
820 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
821 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)822 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
823 {
824 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
825 }
826 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
827 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
828 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
829 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)830 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
831 {
832 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
833 }
834 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
835 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)836 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
837 {
838 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
839 }
840
REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0)841 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
842 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
843 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)844 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
845 {
846 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
847 }
848 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
849 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)850 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
851 {
852 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
853 }
854 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
855 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)856 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
857 {
858 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
859 }
860 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
861 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)862 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
863 {
864 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
865 }
866
REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0)867 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
868 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
869 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
870 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)871 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
872 {
873 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
874 }
875 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
876 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
877 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
878 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
879 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
880 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
881 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
882 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
883
REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0)884 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
885
REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0)886 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
887
REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0)888 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
889
REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0)890 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
891
REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0)892 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
893
REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0)894 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
895
REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0)896 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
897
REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0)898 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
899
REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0)900 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
901
REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0)902 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
903
REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0)904 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
905
REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0)906 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
907 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
908 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
MDP5_PIPE_DECIMATION_VERT(uint32_t val)909 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
910 {
911 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
912 }
913 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
914 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
MDP5_PIPE_DECIMATION_HORZ(uint32_t val)915 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
916 {
917 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
918 }
919
__offset_SW_PIX_EXT(enum mdp_component_type idx)920 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
921 {
922 switch (idx) {
923 case COMP_0: return 0x00000100;
924 case COMP_1_2: return 0x00000110;
925 case COMP_3: return 0x00000120;
926 default: return INVALID_IDX(idx);
927 }
928 }
REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0,enum mdp_component_type i1)929 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
930
REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0,enum mdp_component_type i1)931 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
932 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
933 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)934 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
935 {
936 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
937 }
938 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
939 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)940 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
941 {
942 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
943 }
944 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
945 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)946 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
947 {
948 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
949 }
950 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
951 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)952 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
953 {
954 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
955 }
956
REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0,enum mdp_component_type i1)957 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
958 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
959 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)960 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
961 {
962 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
963 }
964 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
965 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)966 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
967 {
968 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
969 }
970 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
971 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)972 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
973 {
974 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
975 }
976 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
977 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)978 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
979 {
980 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
981 }
982
REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0,enum mdp_component_type i1)983 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
984 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
985 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)986 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
987 {
988 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
989 }
990 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
991 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)992 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
993 {
994 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
995 }
996
REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0)997 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
998 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
999 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
1000 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1001 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)1002 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1003 {
1004 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1005 }
1006 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1007 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)1008 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1009 {
1010 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1011 }
1012 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1013 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)1014 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1015 {
1016 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1017 }
1018 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1019 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)1020 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1021 {
1022 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1023 }
1024 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1025 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)1026 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1027 {
1028 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1029 }
1030 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1031 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)1032 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1033 {
1034 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1035 }
1036
REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0)1037 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1038
REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0)1039 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1040
REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0)1041 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1042
REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0)1043 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1044
REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0)1045 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1046
REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0)1047 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1048
__offset_LM(uint32_t idx)1049 static inline uint32_t __offset_LM(uint32_t idx)
1050 {
1051 switch (idx) {
1052 case 0: return (mdp5_cfg->lm.base[0]);
1053 case 1: return (mdp5_cfg->lm.base[1]);
1054 case 2: return (mdp5_cfg->lm.base[2]);
1055 case 3: return (mdp5_cfg->lm.base[3]);
1056 case 4: return (mdp5_cfg->lm.base[4]);
1057 case 5: return (mdp5_cfg->lm.base[5]);
1058 default: return INVALID_IDX(idx);
1059 }
1060 }
REG_MDP5_LM(uint32_t i0)1061 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1062
REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0)1063 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1064 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1065 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1066 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1067 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
1068
REG_MDP5_LM_OUT_SIZE(uint32_t i0)1069 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1070 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1071 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)1072 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1073 {
1074 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1075 }
1076 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1077 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)1078 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1079 {
1080 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1081 }
1082
REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0)1083 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1084
REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0)1085 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1086
__offset_BLEND(uint32_t idx)1087 static inline uint32_t __offset_BLEND(uint32_t idx)
1088 {
1089 switch (idx) {
1090 case 0: return 0x00000020;
1091 case 1: return 0x00000050;
1092 case 2: return 0x00000080;
1093 case 3: return 0x000000b0;
1094 case 4: return 0x00000230;
1095 case 5: return 0x00000260;
1096 case 6: return 0x00000290;
1097 default: return INVALID_IDX(idx);
1098 }
1099 }
REG_MDP5_LM_BLEND(uint32_t i0,uint32_t i1)1100 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1101
REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0,uint32_t i1)1102 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1103 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1104 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)1105 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1106 {
1107 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1108 }
1109 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1110 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1111 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1112 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1113 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1114 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)1115 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1116 {
1117 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1118 }
1119 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1120 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1121 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1122 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1123
REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0,uint32_t i1)1124 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1125
REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0,uint32_t i1)1126 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1127
REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0,uint32_t i1)1128 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1129
REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0,uint32_t i1)1130 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1131
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)1132 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1133
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)1134 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1135
REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0,uint32_t i1)1136 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1137
REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0,uint32_t i1)1138 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1139
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)1140 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1141
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)1142 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1143
REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0)1144 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1145 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1146 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)1147 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1148 {
1149 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1150 }
1151 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1152 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)1153 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1154 {
1155 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1156 }
1157
REG_MDP5_LM_CURSOR_SIZE(uint32_t i0)1158 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1159 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1160 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)1161 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1162 {
1163 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1164 }
1165 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1166 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)1167 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1168 {
1169 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1170 }
1171
REG_MDP5_LM_CURSOR_XY(uint32_t i0)1172 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1173 #define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1174 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)1175 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1176 {
1177 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1178 }
1179 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1180 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)1181 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1182 {
1183 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1184 }
1185
REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0)1186 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1187 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1188 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)1189 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1190 {
1191 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1192 }
1193
REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0)1194 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1195 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1196 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)1197 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1198 {
1199 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1200 }
1201
REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0)1202 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1203
REG_MDP5_LM_CURSOR_START_XY(uint32_t i0)1204 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1205 #define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1206 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)1207 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1208 {
1209 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1210 }
1211 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1212 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)1213 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1214 {
1215 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1216 }
1217
REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0)1218 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1219 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1220 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1221 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)1222 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1223 {
1224 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1225 }
1226 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1227
REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0)1228 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1229
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0)1230 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1231
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0)1232 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1233
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0)1234 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1235
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0)1236 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1237
REG_MDP5_LM_GC_LUT_BASE(uint32_t i0)1238 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1239
__offset_DSPP(uint32_t idx)1240 static inline uint32_t __offset_DSPP(uint32_t idx)
1241 {
1242 switch (idx) {
1243 case 0: return (mdp5_cfg->dspp.base[0]);
1244 case 1: return (mdp5_cfg->dspp.base[1]);
1245 case 2: return (mdp5_cfg->dspp.base[2]);
1246 case 3: return (mdp5_cfg->dspp.base[3]);
1247 default: return INVALID_IDX(idx);
1248 }
1249 }
REG_MDP5_DSPP(uint32_t i0)1250 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1251
REG_MDP5_DSPP_OP_MODE(uint32_t i0)1252 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1253 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1254 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1255 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)1256 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1257 {
1258 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1259 }
1260 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1261 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1262 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1263 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1264 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1265 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1266 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1267 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1268
REG_MDP5_DSPP_PCC_BASE(uint32_t i0)1269 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1270
REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0)1271 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1272
REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0)1273 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1274
REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0)1275 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1276
REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0)1277 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1278
REG_MDP5_DSPP_PA_BASE(uint32_t i0)1279 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1280
REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0)1281 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1282
REG_MDP5_DSPP_GC_BASE(uint32_t i0)1283 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1284
__offset_PP(uint32_t idx)1285 static inline uint32_t __offset_PP(uint32_t idx)
1286 {
1287 switch (idx) {
1288 case 0: return (mdp5_cfg->pp.base[0]);
1289 case 1: return (mdp5_cfg->pp.base[1]);
1290 case 2: return (mdp5_cfg->pp.base[2]);
1291 case 3: return (mdp5_cfg->pp.base[3]);
1292 default: return INVALID_IDX(idx);
1293 }
1294 }
REG_MDP5_PP(uint32_t i0)1295 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1296
REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0)1297 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1298
REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0)1299 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1300 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1301 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)1302 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1303 {
1304 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1305 }
1306 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1307 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1308
REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0)1309 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1310
REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0)1311 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1312 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1313 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)1314 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1315 {
1316 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1317 }
1318 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1319 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)1320 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1321 {
1322 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1323 }
1324
REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0)1325 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1326
REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0)1327 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1328 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1329 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)1330 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1331 {
1332 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1333 }
1334 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1335 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)1336 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1337 {
1338 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1339 }
1340
REG_MDP5_PP_SYNC_THRESH(uint32_t i0)1341 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1342 #define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1343 #define MDP5_PP_SYNC_THRESH_START__SHIFT 0
MDP5_PP_SYNC_THRESH_START(uint32_t val)1344 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1345 {
1346 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1347 }
1348 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1349 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)1350 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1351 {
1352 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1353 }
1354
REG_MDP5_PP_START_POS(uint32_t i0)1355 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1356
REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0)1357 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1358
REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0)1359 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1360
REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0)1361 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1362
REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0)1363 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1364
REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0)1365 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1366
REG_MDP5_PP_FBC_MODE(uint32_t i0)1367 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1368
REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0)1369 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1370
REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0)1371 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1372
__offset_WB(uint32_t idx)1373 static inline uint32_t __offset_WB(uint32_t idx)
1374 {
1375 switch (idx) {
1376 #if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1377 case 0: return (mdp5_cfg->wb.base[0]);
1378 case 1: return (mdp5_cfg->wb.base[1]);
1379 case 2: return (mdp5_cfg->wb.base[2]);
1380 case 3: return (mdp5_cfg->wb.base[3]);
1381 case 4: return (mdp5_cfg->wb.base[4]);
1382 #endif
1383 default: return INVALID_IDX(idx);
1384 }
1385 }
REG_MDP5_WB(uint32_t i0)1386 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1387
REG_MDP5_WB_DST_FORMAT(uint32_t i0)1388 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1389 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1390 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)1391 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1392 {
1393 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1394 }
1395 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1396 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)1397 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1398 {
1399 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1400 }
1401 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1402 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)1403 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1404 {
1405 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1406 }
1407 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1408 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)1409 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1410 {
1411 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1412 }
1413 #define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1414 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1415 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)1416 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1417 {
1418 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1419 }
1420 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1421 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)1422 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1423 {
1424 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1425 }
1426 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1427 #define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1428 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1429 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1430 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)1431 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1432 {
1433 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1434 }
1435 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1436 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1437 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)1438 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1439 {
1440 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1441 }
1442 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1443 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)1444 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1445 {
1446 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1447 }
1448 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1449 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)1450 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1451 {
1452 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1453 }
1454
REG_MDP5_WB_DST_OP_MODE(uint32_t i0)1455 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1456 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1457 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1458 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)1459 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1460 {
1461 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1462 }
1463 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1464 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)1465 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1466 {
1467 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1468 }
1469 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1470 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)1471 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1472 {
1473 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1474 }
1475 #define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1476 #define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1477 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1478 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)1479 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1480 {
1481 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1482 }
1483 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1484 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)1485 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1486 {
1487 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1488 }
1489 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1490 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1491 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)1492 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1493 {
1494 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1495 }
1496 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1497 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)1498 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1499 {
1500 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1501 }
1502 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1503 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)1504 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1505 {
1506 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1507 }
1508
REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0)1509 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1510 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1511 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)1512 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1513 {
1514 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1515 }
1516 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1517 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)1518 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1519 {
1520 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1521 }
1522 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1523 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)1524 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1525 {
1526 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1527 }
1528 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1529 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)1530 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1531 {
1532 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1533 }
1534
REG_MDP5_WB_DST0_ADDR(uint32_t i0)1535 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1536
REG_MDP5_WB_DST1_ADDR(uint32_t i0)1537 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1538
REG_MDP5_WB_DST2_ADDR(uint32_t i0)1539 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1540
REG_MDP5_WB_DST3_ADDR(uint32_t i0)1541 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1542
REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0)1543 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1544 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1545 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)1546 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1547 {
1548 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1549 }
1550 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1551 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)1552 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1553 {
1554 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1555 }
1556
REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0)1557 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1558 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1559 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)1560 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1561 {
1562 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1563 }
1564 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1565 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)1566 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1567 {
1568 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1569 }
1570
REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0)1571 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1572
REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0)1573 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1574
REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0)1575 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1576
REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0)1577 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1578
REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0)1579 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1580
REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0)1581 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1582
REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0)1583 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1584
REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0)1585 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1586
REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0)1587 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1588
REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0)1589 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1590
REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0)1591 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1592
REG_MDP5_WB_OUT_SIZE(uint32_t i0)1593 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1594 #define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1595 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
MDP5_WB_OUT_SIZE_DST_W(uint32_t val)1596 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1597 {
1598 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1599 }
1600 #define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1601 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
MDP5_WB_OUT_SIZE_DST_H(uint32_t val)1602 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1603 {
1604 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1605 }
1606
REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0)1607 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1608
REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0)1609 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1610 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1611 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)1612 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1613 {
1614 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1615 }
1616 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1617 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)1618 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1619 {
1620 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1621 }
1622
REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0)1623 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1624 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1625 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)1626 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1627 {
1628 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1629 }
1630 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1631 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)1632 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1633 {
1634 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1635 }
1636
REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0)1637 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1638 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1639 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)1640 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1641 {
1642 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1643 }
1644 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1645 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)1646 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1647 {
1648 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1649 }
1650
REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0)1651 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1652 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1653 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)1654 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1655 {
1656 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1657 }
1658 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1659 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)1660 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1661 {
1662 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1663 }
1664
REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0)1665 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1666 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1667 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)1668 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1669 {
1670 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1671 }
1672
REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0,uint32_t i1)1673 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1674
REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0,uint32_t i1)1675 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1676 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1677 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)1678 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1679 {
1680 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1681 }
1682 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1683 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)1684 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1685 {
1686 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1687 }
1688
REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0,uint32_t i1)1689 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1690
REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0,uint32_t i1)1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1692 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1693 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)1694 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1695 {
1696 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1697 }
1698 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1699 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)1700 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1701 {
1702 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1703 }
1704
REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0,uint32_t i1)1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1706
REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0,uint32_t i1)1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1708 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1709 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)1710 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1711 {
1712 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1713 }
1714
REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0,uint32_t i1)1715 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1716
REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0,uint32_t i1)1717 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1718 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1719 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)1720 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1721 {
1722 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1723 }
1724
__offset_INTF(uint32_t idx)1725 static inline uint32_t __offset_INTF(uint32_t idx)
1726 {
1727 switch (idx) {
1728 case 0: return (mdp5_cfg->intf.base[0]);
1729 case 1: return (mdp5_cfg->intf.base[1]);
1730 case 2: return (mdp5_cfg->intf.base[2]);
1731 case 3: return (mdp5_cfg->intf.base[3]);
1732 case 4: return (mdp5_cfg->intf.base[4]);
1733 default: return INVALID_IDX(idx);
1734 }
1735 }
REG_MDP5_INTF(uint32_t i0)1736 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1737
REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0)1738 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1739
REG_MDP5_INTF_CONFIG(uint32_t i0)1740 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1741
REG_MDP5_INTF_HSYNC_CTL(uint32_t i0)1742 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1743 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1744 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)1745 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1746 {
1747 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1748 }
1749 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1750 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)1751 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1752 {
1753 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1754 }
1755
REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0)1756 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1757
REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0)1758 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1759
REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0)1760 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1761
REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0)1762 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1763
REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0)1764 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1765
REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0)1766 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1767
REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0)1768 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1769
REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0)1770 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1771
REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0)1772 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1773 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1774 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)1775 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1776 {
1777 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1778 }
1779 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1780
REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0)1781 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1782 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1783 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)1784 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1785 {
1786 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1787 }
1788
REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0)1789 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1790
REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0)1791 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1792
REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0)1793 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1794 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1795 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)1796 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1797 {
1798 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1799 }
1800 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1801 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)1802 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1803 {
1804 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1805 }
1806
REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0)1807 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1808 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1809 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)1810 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1811 {
1812 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1813 }
1814 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1815 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)1816 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1817 {
1818 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1819 }
1820 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1821
REG_MDP5_INTF_BORDER_COLOR(uint32_t i0)1822 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1823
REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0)1824 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1825
REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0)1826 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1827
REG_MDP5_INTF_POLARITY_CTL(uint32_t i0)1828 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1829 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1830 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1831 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1832
REG_MDP5_INTF_TEST_CTL(uint32_t i0)1833 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1834
REG_MDP5_INTF_TP_COLOR0(uint32_t i0)1835 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1836
REG_MDP5_INTF_TP_COLOR1(uint32_t i0)1837 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1838
REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0)1839 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1840
REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0)1841 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1842
REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0)1843 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1844
REG_MDP5_INTF_FRAME_COUNT(uint32_t i0)1845 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1846
REG_MDP5_INTF_LINE_COUNT(uint32_t i0)1847 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1848
REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0)1849 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1850
REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0)1851 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1852
REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0)1853 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1854
REG_MDP5_INTF_TPG_ENABLE(uint32_t i0)1855 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1856
REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0)1857 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1858
REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0)1859 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1860
REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0)1861 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1862
REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0)1863 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1864
REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0)1865 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1866
REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0)1867 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1868
REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0)1869 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1870
__offset_AD(uint32_t idx)1871 static inline uint32_t __offset_AD(uint32_t idx)
1872 {
1873 switch (idx) {
1874 case 0: return (mdp5_cfg->ad.base[0]);
1875 case 1: return (mdp5_cfg->ad.base[1]);
1876 default: return INVALID_IDX(idx);
1877 }
1878 }
REG_MDP5_AD(uint32_t i0)1879 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1880
REG_MDP5_AD_BYPASS(uint32_t i0)1881 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1882
REG_MDP5_AD_CTRL_0(uint32_t i0)1883 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1884
REG_MDP5_AD_CTRL_1(uint32_t i0)1885 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1886
REG_MDP5_AD_FRAME_SIZE(uint32_t i0)1887 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1888
REG_MDP5_AD_CON_CTRL_0(uint32_t i0)1889 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1890
REG_MDP5_AD_CON_CTRL_1(uint32_t i0)1891 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1892
REG_MDP5_AD_STR_MAN(uint32_t i0)1893 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1894
REG_MDP5_AD_VAR(uint32_t i0)1895 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1896
REG_MDP5_AD_DITH(uint32_t i0)1897 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1898
REG_MDP5_AD_DITH_CTRL(uint32_t i0)1899 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1900
REG_MDP5_AD_AMP_LIM(uint32_t i0)1901 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1902
REG_MDP5_AD_SLOPE(uint32_t i0)1903 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1904
REG_MDP5_AD_BW_LVL(uint32_t i0)1905 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1906
REG_MDP5_AD_LOGO_POS(uint32_t i0)1907 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1908
REG_MDP5_AD_LUT_FI(uint32_t i0)1909 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1910
REG_MDP5_AD_LUT_CC(uint32_t i0)1911 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1912
REG_MDP5_AD_STR_LIM(uint32_t i0)1913 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1914
REG_MDP5_AD_CALIB_AB(uint32_t i0)1915 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1916
REG_MDP5_AD_CALIB_CD(uint32_t i0)1917 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1918
REG_MDP5_AD_MODE_SEL(uint32_t i0)1919 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1920
REG_MDP5_AD_TFILT_CTRL(uint32_t i0)1921 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1922
REG_MDP5_AD_BL_MINMAX(uint32_t i0)1923 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1924
REG_MDP5_AD_BL(uint32_t i0)1925 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1926
REG_MDP5_AD_BL_MAX(uint32_t i0)1927 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1928
REG_MDP5_AD_AL(uint32_t i0)1929 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1930
REG_MDP5_AD_AL_MIN(uint32_t i0)1931 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1932
REG_MDP5_AD_AL_FILT(uint32_t i0)1933 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1934
REG_MDP5_AD_CFG_BUF(uint32_t i0)1935 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1936
REG_MDP5_AD_LUT_AL(uint32_t i0)1937 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1938
REG_MDP5_AD_TARG_STR(uint32_t i0)1939 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1940
REG_MDP5_AD_START_CALC(uint32_t i0)1941 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1942
REG_MDP5_AD_STR_OUT(uint32_t i0)1943 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1944
REG_MDP5_AD_BL_OUT(uint32_t i0)1945 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1946
REG_MDP5_AD_CALC_DONE(uint32_t i0)1947 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1948
1949
1950 #endif /* MDP5_XML */
1951