1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/inst.h>
23 #include <asm/mipsregs.h>
24
25 /* MIPS KVM register ids */
26 #define MIPS_CP0_32(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
28
29 #define MIPS_CP0_64(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
31
32 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
34 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
35 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
36 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
37 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
38 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
39 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
40 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
41 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
42 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
43 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
44 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
45 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
46 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
47 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
48 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
49 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
50 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
51 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
52 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
53 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
54 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
55 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
56 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
57 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
58 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
59 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
60 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
61 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
62 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
63 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
64 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
65
66
67 #define KVM_MAX_VCPUS 1
68 #define KVM_USER_MEM_SLOTS 8
69 /* memory slots that does not exposed to userspace */
70 #define KVM_PRIVATE_MEM_SLOTS 0
71
72 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
73 #define KVM_HALT_POLL_NS_DEFAULT 500000
74
75
76
77 /*
78 * Special address that contains the comm page, used for reducing # of traps
79 * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
80 * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
81 * caught.
82 */
83 #define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \
84 (0x8000 - PAGE_SIZE))
85
86 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
87 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
88
89 #define KVM_GUEST_KUSEG 0x00000000UL
90 #define KVM_GUEST_KSEG0 0x40000000UL
91 #define KVM_GUEST_KSEG23 0x60000000UL
92 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
93 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
94
95 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
96 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
97 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
98
99 /*
100 * Map an address to a certain kernel segment
101 */
102 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
103 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
104 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
105
106 #define KVM_INVALID_PAGE 0xdeadbeef
107 #define KVM_INVALID_INST 0xdeadbeef
108 #define KVM_INVALID_ADDR 0xdeadbeef
109
110 /*
111 * EVA has overlapping user & kernel address spaces, so user VAs may be >
112 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
113 * PAGE_OFFSET.
114 */
115
116 #define KVM_HVA_ERR_BAD (-1UL)
117 #define KVM_HVA_ERR_RO_BAD (-2UL)
118
kvm_is_error_hva(unsigned long addr)119 static inline bool kvm_is_error_hva(unsigned long addr)
120 {
121 return IS_ERR_VALUE(addr);
122 }
123
124 extern atomic_t kvm_mips_instance;
125
126 struct kvm_vm_stat {
127 ulong remote_tlb_flush;
128 };
129
130 struct kvm_vcpu_stat {
131 u64 wait_exits;
132 u64 cache_exits;
133 u64 signal_exits;
134 u64 int_exits;
135 u64 cop_unusable_exits;
136 u64 tlbmod_exits;
137 u64 tlbmiss_ld_exits;
138 u64 tlbmiss_st_exits;
139 u64 addrerr_st_exits;
140 u64 addrerr_ld_exits;
141 u64 syscall_exits;
142 u64 resvd_inst_exits;
143 u64 break_inst_exits;
144 u64 trap_inst_exits;
145 u64 msa_fpe_exits;
146 u64 fpe_exits;
147 u64 msa_disabled_exits;
148 u64 flush_dcache_exits;
149 u64 halt_successful_poll;
150 u64 halt_attempted_poll;
151 u64 halt_poll_invalid;
152 u64 halt_wakeup;
153 };
154
155 struct kvm_arch_memory_slot {
156 };
157
158 struct kvm_arch {
159 /* Guest GVA->HPA page table */
160 unsigned long *guest_pmap;
161 unsigned long guest_pmap_npages;
162
163 /* Wired host TLB used for the commpage */
164 int commpage_tlb;
165 };
166
167 #define N_MIPS_COPROC_REGS 32
168 #define N_MIPS_COPROC_SEL 8
169
170 struct mips_coproc {
171 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
172 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
173 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
174 #endif
175 };
176
177 /*
178 * Coprocessor 0 register names
179 */
180 #define MIPS_CP0_TLB_INDEX 0
181 #define MIPS_CP0_TLB_RANDOM 1
182 #define MIPS_CP0_TLB_LOW 2
183 #define MIPS_CP0_TLB_LO0 2
184 #define MIPS_CP0_TLB_LO1 3
185 #define MIPS_CP0_TLB_CONTEXT 4
186 #define MIPS_CP0_TLB_PG_MASK 5
187 #define MIPS_CP0_TLB_WIRED 6
188 #define MIPS_CP0_HWRENA 7
189 #define MIPS_CP0_BAD_VADDR 8
190 #define MIPS_CP0_COUNT 9
191 #define MIPS_CP0_TLB_HI 10
192 #define MIPS_CP0_COMPARE 11
193 #define MIPS_CP0_STATUS 12
194 #define MIPS_CP0_CAUSE 13
195 #define MIPS_CP0_EXC_PC 14
196 #define MIPS_CP0_PRID 15
197 #define MIPS_CP0_CONFIG 16
198 #define MIPS_CP0_LLADDR 17
199 #define MIPS_CP0_WATCH_LO 18
200 #define MIPS_CP0_WATCH_HI 19
201 #define MIPS_CP0_TLB_XCONTEXT 20
202 #define MIPS_CP0_ECC 26
203 #define MIPS_CP0_CACHE_ERR 27
204 #define MIPS_CP0_TAG_LO 28
205 #define MIPS_CP0_TAG_HI 29
206 #define MIPS_CP0_ERROR_PC 30
207 #define MIPS_CP0_DEBUG 23
208 #define MIPS_CP0_DEPC 24
209 #define MIPS_CP0_PERFCNT 25
210 #define MIPS_CP0_ERRCTL 26
211 #define MIPS_CP0_DATA_LO 28
212 #define MIPS_CP0_DATA_HI 29
213 #define MIPS_CP0_DESAVE 31
214
215 #define MIPS_CP0_CONFIG_SEL 0
216 #define MIPS_CP0_CONFIG1_SEL 1
217 #define MIPS_CP0_CONFIG2_SEL 2
218 #define MIPS_CP0_CONFIG3_SEL 3
219 #define MIPS_CP0_CONFIG4_SEL 4
220 #define MIPS_CP0_CONFIG5_SEL 5
221
222 /* Resume Flags */
223 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
224 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
225
226 #define RESUME_GUEST 0
227 #define RESUME_GUEST_DR RESUME_FLAG_DR
228 #define RESUME_HOST RESUME_FLAG_HOST
229
230 enum emulation_result {
231 EMULATE_DONE, /* no further processing */
232 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
233 EMULATE_FAIL, /* can't emulate this instruction */
234 EMULATE_WAIT, /* WAIT instruction */
235 EMULATE_PRIV_FAIL,
236 };
237
238 #define mips3_paddr_to_tlbpfn(x) \
239 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
240 #define mips3_tlbpfn_to_paddr(x) \
241 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
242
243 #define MIPS3_PG_SHIFT 6
244 #define MIPS3_PG_FRAME 0x3fffffc0
245
246 #define VPN2_MASK 0xffffe000
247 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
248 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
249 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
250 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
251 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
252 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
253 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
254 ((y) & VPN2_MASK & ~(x).tlb_mask))
255 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
256 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
257
258 struct kvm_mips_tlb {
259 long tlb_mask;
260 long tlb_hi;
261 long tlb_lo[2];
262 };
263
264 #define KVM_MIPS_AUX_FPU 0x1
265 #define KVM_MIPS_AUX_MSA 0x2
266
267 #define KVM_MIPS_GUEST_TLB_SIZE 64
268 struct kvm_vcpu_arch {
269 void *guest_ebase;
270 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
271 unsigned long host_stack;
272 unsigned long host_gp;
273
274 /* Host CP0 registers used when handling exits from guest */
275 unsigned long host_cp0_badvaddr;
276 unsigned long host_cp0_epc;
277 u32 host_cp0_cause;
278
279 /* GPRS */
280 unsigned long gprs[32];
281 unsigned long hi;
282 unsigned long lo;
283 unsigned long pc;
284
285 /* FPU State */
286 struct mips_fpu_struct fpu;
287 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
288 unsigned int aux_inuse;
289
290 /* COP0 State */
291 struct mips_coproc *cop0;
292
293 /* Host KSEG0 address of the EI/DI offset */
294 void *kseg0_commpage;
295
296 /* Resume PC after MMIO completion */
297 unsigned long io_pc;
298 /* GPR used as IO source/target */
299 u32 io_gpr;
300
301 struct hrtimer comparecount_timer;
302 /* Count timer control KVM register */
303 u32 count_ctl;
304 /* Count bias from the raw time */
305 u32 count_bias;
306 /* Frequency of timer in Hz */
307 u32 count_hz;
308 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
309 s64 count_dyn_bias;
310 /* Resume time */
311 ktime_t count_resume;
312 /* Period of timer tick in ns */
313 u64 count_period;
314
315 /* Bitmask of exceptions that are pending */
316 unsigned long pending_exceptions;
317
318 /* Bitmask of pending exceptions to be cleared */
319 unsigned long pending_exceptions_clr;
320
321 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
322 unsigned long preempt_entryhi;
323
324 /* S/W Based TLB for guest */
325 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
326
327 /* Cached guest kernel/user ASIDs */
328 u32 guest_user_asid[NR_CPUS];
329 u32 guest_kernel_asid[NR_CPUS];
330 struct mm_struct guest_kernel_mm, guest_user_mm;
331
332 /* Guest ASID of last user mode execution */
333 unsigned int last_user_gasid;
334
335 int last_sched_cpu;
336
337 /* WAIT executed */
338 int wait;
339
340 u8 fpu_enabled;
341 u8 msa_enabled;
342 u8 kscratch_enabled;
343 };
344
345
346 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
347 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
348 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
349 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
350 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
351 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
352 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
353 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
354 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
355 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
356 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
357 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
358 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
359 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
360 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
361 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
362 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
363 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
364 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
365 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
366 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
367 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
368 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
369 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
370 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
371 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
372 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
373 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
374 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
375 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
376 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
377 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
378 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
379 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
380 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
381 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
382 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
383 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
384 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
385 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
386 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
387 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
388 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
389 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
390 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
391 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
392 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
393 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
394 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
395 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
396 #define kvm_read_c0_guest_kscratch1(cop0) (cop0->reg[MIPS_CP0_DESAVE][2])
397 #define kvm_read_c0_guest_kscratch2(cop0) (cop0->reg[MIPS_CP0_DESAVE][3])
398 #define kvm_read_c0_guest_kscratch3(cop0) (cop0->reg[MIPS_CP0_DESAVE][4])
399 #define kvm_read_c0_guest_kscratch4(cop0) (cop0->reg[MIPS_CP0_DESAVE][5])
400 #define kvm_read_c0_guest_kscratch5(cop0) (cop0->reg[MIPS_CP0_DESAVE][6])
401 #define kvm_read_c0_guest_kscratch6(cop0) (cop0->reg[MIPS_CP0_DESAVE][7])
402 #define kvm_write_c0_guest_kscratch1(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][2] = (val))
403 #define kvm_write_c0_guest_kscratch2(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][3] = (val))
404 #define kvm_write_c0_guest_kscratch3(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][4] = (val))
405 #define kvm_write_c0_guest_kscratch4(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][5] = (val))
406 #define kvm_write_c0_guest_kscratch5(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][6] = (val))
407 #define kvm_write_c0_guest_kscratch6(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][7] = (val))
408
409 /*
410 * Some of the guest registers may be modified asynchronously (e.g. from a
411 * hrtimer callback in hard irq context) and therefore need stronger atomicity
412 * guarantees than other registers.
413 */
414
_kvm_atomic_set_c0_guest_reg(unsigned long * reg,unsigned long val)415 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
416 unsigned long val)
417 {
418 unsigned long temp;
419 do {
420 __asm__ __volatile__(
421 " .set "MIPS_ISA_ARCH_LEVEL" \n"
422 " " __LL "%0, %1 \n"
423 " or %0, %2 \n"
424 " " __SC "%0, %1 \n"
425 " .set mips0 \n"
426 : "=&r" (temp), "+m" (*reg)
427 : "r" (val));
428 } while (unlikely(!temp));
429 }
430
_kvm_atomic_clear_c0_guest_reg(unsigned long * reg,unsigned long val)431 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
432 unsigned long val)
433 {
434 unsigned long temp;
435 do {
436 __asm__ __volatile__(
437 " .set "MIPS_ISA_ARCH_LEVEL" \n"
438 " " __LL "%0, %1 \n"
439 " and %0, %2 \n"
440 " " __SC "%0, %1 \n"
441 " .set mips0 \n"
442 : "=&r" (temp), "+m" (*reg)
443 : "r" (~val));
444 } while (unlikely(!temp));
445 }
446
_kvm_atomic_change_c0_guest_reg(unsigned long * reg,unsigned long change,unsigned long val)447 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
448 unsigned long change,
449 unsigned long val)
450 {
451 unsigned long temp;
452 do {
453 __asm__ __volatile__(
454 " .set "MIPS_ISA_ARCH_LEVEL" \n"
455 " " __LL "%0, %1 \n"
456 " and %0, %2 \n"
457 " or %0, %3 \n"
458 " " __SC "%0, %1 \n"
459 " .set mips0 \n"
460 : "=&r" (temp), "+m" (*reg)
461 : "r" (~change), "r" (val & change));
462 } while (unlikely(!temp));
463 }
464
465 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
466 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
467
468 /* Cause can be modified asynchronously from hardirq hrtimer callback */
469 #define kvm_set_c0_guest_cause(cop0, val) \
470 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
471 #define kvm_clear_c0_guest_cause(cop0, val) \
472 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
473 #define kvm_change_c0_guest_cause(cop0, change, val) \
474 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
475 change, val)
476
477 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
478 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
479 #define kvm_change_c0_guest_ebase(cop0, change, val) \
480 { \
481 kvm_clear_c0_guest_ebase(cop0, change); \
482 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
483 }
484
485 /* Helpers */
486
kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch * vcpu)487 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
488 {
489 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
490 vcpu->fpu_enabled;
491 }
492
kvm_mips_guest_has_fpu(struct kvm_vcpu_arch * vcpu)493 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
494 {
495 return kvm_mips_guest_can_have_fpu(vcpu) &&
496 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
497 }
498
kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch * vcpu)499 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
500 {
501 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
502 vcpu->msa_enabled;
503 }
504
kvm_mips_guest_has_msa(struct kvm_vcpu_arch * vcpu)505 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
506 {
507 return kvm_mips_guest_can_have_msa(vcpu) &&
508 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
509 }
510
511 struct kvm_mips_callbacks {
512 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
513 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
514 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
515 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
516 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
517 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
518 int (*handle_syscall)(struct kvm_vcpu *vcpu);
519 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
520 int (*handle_break)(struct kvm_vcpu *vcpu);
521 int (*handle_trap)(struct kvm_vcpu *vcpu);
522 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
523 int (*handle_fpe)(struct kvm_vcpu *vcpu);
524 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
525 int (*vm_init)(struct kvm *kvm);
526 int (*vcpu_init)(struct kvm_vcpu *vcpu);
527 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
528 gpa_t (*gva_to_gpa)(gva_t gva);
529 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
530 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
531 void (*queue_io_int)(struct kvm_vcpu *vcpu,
532 struct kvm_mips_interrupt *irq);
533 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
534 struct kvm_mips_interrupt *irq);
535 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
536 u32 cause);
537 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
538 u32 cause);
539 unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
540 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
541 int (*get_one_reg)(struct kvm_vcpu *vcpu,
542 const struct kvm_one_reg *reg, s64 *v);
543 int (*set_one_reg)(struct kvm_vcpu *vcpu,
544 const struct kvm_one_reg *reg, s64 v);
545 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
546 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
547 };
548 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
549 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
550
551 /* Debug: dump vcpu state */
552 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
553
554 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
555
556 /* Building of entry/exception code */
557 int kvm_mips_entry_setup(void);
558 void *kvm_mips_build_vcpu_run(void *addr);
559 void *kvm_mips_build_exception(void *addr, void *handler);
560 void *kvm_mips_build_exit(void *addr);
561
562 /* FPU/MSA context management */
563 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
564 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
565 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
566 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
567 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
568 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
569 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
570 void kvm_own_fpu(struct kvm_vcpu *vcpu);
571 void kvm_own_msa(struct kvm_vcpu *vcpu);
572 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
573 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
574
575 /* TLB handling */
576 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
577
578 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
579
580 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
581
582 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
583 struct kvm_vcpu *vcpu);
584
585 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
586 struct kvm_vcpu *vcpu);
587
588 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
589 struct kvm_mips_tlb *tlb);
590
591 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
592 u32 *opc,
593 struct kvm_run *run,
594 struct kvm_vcpu *vcpu);
595
596 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
597 u32 *opc,
598 struct kvm_run *run,
599 struct kvm_vcpu *vcpu);
600
601 extern void kvm_mips_dump_host_tlbs(void);
602 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
603 extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
604 unsigned long entrylo0,
605 unsigned long entrylo1,
606 int flush_dcache_mask);
607 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
608 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
609
610 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
611 unsigned long entryhi);
612 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
613 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
614 unsigned long gva);
615 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
616 struct kvm_vcpu *vcpu);
617 extern void kvm_local_flush_tlb_all(void);
618 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
619 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
620 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
621
622 /* Emulation */
623 u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu);
624 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
625
626 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
627 u32 *opc,
628 struct kvm_run *run,
629 struct kvm_vcpu *vcpu);
630
631 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
632 u32 *opc,
633 struct kvm_run *run,
634 struct kvm_vcpu *vcpu);
635
636 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
637 u32 *opc,
638 struct kvm_run *run,
639 struct kvm_vcpu *vcpu);
640
641 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
642 u32 *opc,
643 struct kvm_run *run,
644 struct kvm_vcpu *vcpu);
645
646 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
647 u32 *opc,
648 struct kvm_run *run,
649 struct kvm_vcpu *vcpu);
650
651 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
652 u32 *opc,
653 struct kvm_run *run,
654 struct kvm_vcpu *vcpu);
655
656 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
657 u32 *opc,
658 struct kvm_run *run,
659 struct kvm_vcpu *vcpu);
660
661 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
662 u32 *opc,
663 struct kvm_run *run,
664 struct kvm_vcpu *vcpu);
665
666 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
667 u32 *opc,
668 struct kvm_run *run,
669 struct kvm_vcpu *vcpu);
670
671 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
672 u32 *opc,
673 struct kvm_run *run,
674 struct kvm_vcpu *vcpu);
675
676 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
677 u32 *opc,
678 struct kvm_run *run,
679 struct kvm_vcpu *vcpu);
680
681 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
682 u32 *opc,
683 struct kvm_run *run,
684 struct kvm_vcpu *vcpu);
685
686 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
687 u32 *opc,
688 struct kvm_run *run,
689 struct kvm_vcpu *vcpu);
690
691 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
692 u32 *opc,
693 struct kvm_run *run,
694 struct kvm_vcpu *vcpu);
695
696 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
697 u32 *opc,
698 struct kvm_run *run,
699 struct kvm_vcpu *vcpu);
700
701 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
702 struct kvm_run *run);
703
704 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
705 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
706 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
707 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
708 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
709 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
710 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
711 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
712 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
713 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
714
715 enum emulation_result kvm_mips_check_privilege(u32 cause,
716 u32 *opc,
717 struct kvm_run *run,
718 struct kvm_vcpu *vcpu);
719
720 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
721 u32 *opc,
722 u32 cause,
723 struct kvm_run *run,
724 struct kvm_vcpu *vcpu);
725 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
726 u32 *opc,
727 u32 cause,
728 struct kvm_run *run,
729 struct kvm_vcpu *vcpu);
730 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
731 u32 cause,
732 struct kvm_run *run,
733 struct kvm_vcpu *vcpu);
734 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
735 u32 cause,
736 struct kvm_run *run,
737 struct kvm_vcpu *vcpu);
738
739 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
740 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
741 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
742 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
743
744 /* Dynamic binary translation */
745 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
746 u32 *opc, struct kvm_vcpu *vcpu);
747 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
748 struct kvm_vcpu *vcpu);
749 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
750 struct kvm_vcpu *vcpu);
751 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
752 struct kvm_vcpu *vcpu);
753
754 /* Misc */
755 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
756 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
757
kvm_arch_hardware_disable(void)758 static inline void kvm_arch_hardware_disable(void) {}
kvm_arch_hardware_unsetup(void)759 static inline void kvm_arch_hardware_unsetup(void) {}
kvm_arch_sync_events(struct kvm * kvm)760 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_free_memslot(struct kvm * kvm,struct kvm_memory_slot * free,struct kvm_memory_slot * dont)761 static inline void kvm_arch_free_memslot(struct kvm *kvm,
762 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
kvm_arch_memslots_updated(struct kvm * kvm,struct kvm_memslots * slots)763 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
kvm_arch_flush_shadow_all(struct kvm * kvm)764 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
kvm_arch_flush_shadow_memslot(struct kvm * kvm,struct kvm_memory_slot * slot)765 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
766 struct kvm_memory_slot *slot) {}
kvm_arch_vcpu_uninit(struct kvm_vcpu * vcpu)767 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)768 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
kvm_arch_vcpu_blocking(struct kvm_vcpu * vcpu)769 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
kvm_arch_vcpu_unblocking(struct kvm_vcpu * vcpu)770 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)771 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
772
773 #endif /* __MIPS_KVM_HOST_H__ */
774