1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 /* 5 * CPU model specific register (MSR) numbers. 6 * 7 * Do not add new entries to this file unless the definitions are shared 8 * between multiple compilation units. 9 */ 10 11 /* x86-64 specific MSRs */ 12 #define MSR_EFER 0xc0000080 /* extended feature register */ 13 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 14 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 15 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 16 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 17 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 18 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 19 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 20 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 21 22 /* EFER bits: */ 23 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 24 #define _EFER_LME 8 /* Long mode enable */ 25 #define _EFER_LMA 10 /* Long mode active (read-only) */ 26 #define _EFER_NX 11 /* No execute enable */ 27 #define _EFER_SVME 12 /* Enable virtualization */ 28 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 29 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 30 31 #define EFER_SCE (1<<_EFER_SCE) 32 #define EFER_LME (1<<_EFER_LME) 33 #define EFER_LMA (1<<_EFER_LMA) 34 #define EFER_NX (1<<_EFER_NX) 35 #define EFER_SVME (1<<_EFER_SVME) 36 #define EFER_LMSLE (1<<_EFER_LMSLE) 37 #define EFER_FFXSR (1<<_EFER_FFXSR) 38 39 /* Intel MSRs. Some also available on other CPUs */ 40 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 41 #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ 42 #define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ 43 44 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 45 #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ 46 47 #define MSR_IA32_PERFCTR0 0x000000c1 48 #define MSR_IA32_PERFCTR1 0x000000c2 49 #define MSR_FSB_FREQ 0x000000cd 50 #define MSR_PLATFORM_INFO 0x000000ce 51 52 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 53 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 54 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 55 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 56 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 57 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 58 59 #define MSR_MTRRcap 0x000000fe 60 61 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 62 #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ 63 #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ 64 65 #define MSR_IA32_BBL_CR_CTL 0x00000119 66 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 67 68 #define MSR_IA32_SYSENTER_CS 0x00000174 69 #define MSR_IA32_SYSENTER_ESP 0x00000175 70 #define MSR_IA32_SYSENTER_EIP 0x00000176 71 72 #define MSR_IA32_MCG_CAP 0x00000179 73 #define MSR_IA32_MCG_STATUS 0x0000017a 74 #define MSR_IA32_MCG_CTL 0x0000017b 75 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 76 77 #define MSR_OFFCORE_RSP_0 0x000001a6 78 #define MSR_OFFCORE_RSP_1 0x000001a7 79 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 80 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 81 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 82 83 #define MSR_LBR_SELECT 0x000001c8 84 #define MSR_LBR_TOS 0x000001c9 85 #define MSR_LBR_NHM_FROM 0x00000680 86 #define MSR_LBR_NHM_TO 0x000006c0 87 #define MSR_LBR_CORE_FROM 0x00000040 88 #define MSR_LBR_CORE_TO 0x00000060 89 90 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 91 #define LBR_INFO_MISPRED BIT_ULL(63) 92 #define LBR_INFO_IN_TX BIT_ULL(62) 93 #define LBR_INFO_ABORT BIT_ULL(61) 94 #define LBR_INFO_CYCLES 0xffff 95 96 #define MSR_IA32_PEBS_ENABLE 0x000003f1 97 #define MSR_IA32_DS_AREA 0x00000600 98 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 99 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 100 101 #define MSR_IA32_RTIT_CTL 0x00000570 102 #define MSR_IA32_RTIT_STATUS 0x00000571 103 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 104 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 105 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 106 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 107 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 108 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 109 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 110 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 111 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 112 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 113 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 114 115 #define MSR_MTRRfix64K_00000 0x00000250 116 #define MSR_MTRRfix16K_80000 0x00000258 117 #define MSR_MTRRfix16K_A0000 0x00000259 118 #define MSR_MTRRfix4K_C0000 0x00000268 119 #define MSR_MTRRfix4K_C8000 0x00000269 120 #define MSR_MTRRfix4K_D0000 0x0000026a 121 #define MSR_MTRRfix4K_D8000 0x0000026b 122 #define MSR_MTRRfix4K_E0000 0x0000026c 123 #define MSR_MTRRfix4K_E8000 0x0000026d 124 #define MSR_MTRRfix4K_F0000 0x0000026e 125 #define MSR_MTRRfix4K_F8000 0x0000026f 126 #define MSR_MTRRdefType 0x000002ff 127 128 #define MSR_IA32_CR_PAT 0x00000277 129 130 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 131 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 132 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 133 #define MSR_IA32_LASTINTFROMIP 0x000001dd 134 #define MSR_IA32_LASTINTTOIP 0x000001de 135 136 /* DEBUGCTLMSR bits (others vary by model): */ 137 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 138 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 139 #define DEBUGCTLMSR_TR (1UL << 6) 140 #define DEBUGCTLMSR_BTS (1UL << 7) 141 #define DEBUGCTLMSR_BTINT (1UL << 8) 142 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 143 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 144 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 145 146 #define MSR_PEBS_FRONTEND 0x000003f7 147 148 #define MSR_IA32_POWER_CTL 0x000001fc 149 150 #define MSR_IA32_MC0_CTL 0x00000400 151 #define MSR_IA32_MC0_STATUS 0x00000401 152 #define MSR_IA32_MC0_ADDR 0x00000402 153 #define MSR_IA32_MC0_MISC 0x00000403 154 155 /* C-state Residency Counters */ 156 #define MSR_PKG_C3_RESIDENCY 0x000003f8 157 #define MSR_PKG_C6_RESIDENCY 0x000003f9 158 #define MSR_PKG_C7_RESIDENCY 0x000003fa 159 #define MSR_CORE_C3_RESIDENCY 0x000003fc 160 #define MSR_CORE_C6_RESIDENCY 0x000003fd 161 #define MSR_CORE_C7_RESIDENCY 0x000003fe 162 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 163 #define MSR_PKG_C2_RESIDENCY 0x0000060d 164 #define MSR_PKG_C8_RESIDENCY 0x00000630 165 #define MSR_PKG_C9_RESIDENCY 0x00000631 166 #define MSR_PKG_C10_RESIDENCY 0x00000632 167 168 /* Interrupt Response Limit */ 169 #define MSR_PKGC3_IRTL 0x0000060a 170 #define MSR_PKGC6_IRTL 0x0000060b 171 #define MSR_PKGC7_IRTL 0x0000060c 172 #define MSR_PKGC8_IRTL 0x00000633 173 #define MSR_PKGC9_IRTL 0x00000634 174 #define MSR_PKGC10_IRTL 0x00000635 175 176 /* Run Time Average Power Limiting (RAPL) Interface */ 177 178 #define MSR_RAPL_POWER_UNIT 0x00000606 179 180 #define MSR_PKG_POWER_LIMIT 0x00000610 181 #define MSR_PKG_ENERGY_STATUS 0x00000611 182 #define MSR_PKG_PERF_STATUS 0x00000613 183 #define MSR_PKG_POWER_INFO 0x00000614 184 185 #define MSR_DRAM_POWER_LIMIT 0x00000618 186 #define MSR_DRAM_ENERGY_STATUS 0x00000619 187 #define MSR_DRAM_PERF_STATUS 0x0000061b 188 #define MSR_DRAM_POWER_INFO 0x0000061c 189 190 #define MSR_PP0_POWER_LIMIT 0x00000638 191 #define MSR_PP0_ENERGY_STATUS 0x00000639 192 #define MSR_PP0_POLICY 0x0000063a 193 #define MSR_PP0_PERF_STATUS 0x0000063b 194 195 #define MSR_PP1_POWER_LIMIT 0x00000640 196 #define MSR_PP1_ENERGY_STATUS 0x00000641 197 #define MSR_PP1_POLICY 0x00000642 198 199 /* Config TDP MSRs */ 200 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 201 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 202 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 203 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 204 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 205 206 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 207 208 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 209 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 210 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 211 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 212 213 #define MSR_CORE_C1_RES 0x00000660 214 215 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 216 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 217 218 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 219 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 220 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 221 222 /* Hardware P state interface */ 223 #define MSR_PPERF 0x0000064e 224 #define MSR_PERF_LIMIT_REASONS 0x0000064f 225 #define MSR_PM_ENABLE 0x00000770 226 #define MSR_HWP_CAPABILITIES 0x00000771 227 #define MSR_HWP_REQUEST_PKG 0x00000772 228 #define MSR_HWP_INTERRUPT 0x00000773 229 #define MSR_HWP_REQUEST 0x00000774 230 #define MSR_HWP_STATUS 0x00000777 231 232 /* CPUID.6.EAX */ 233 #define HWP_BASE_BIT (1<<7) 234 #define HWP_NOTIFICATIONS_BIT (1<<8) 235 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 236 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 237 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 238 239 /* IA32_HWP_CAPABILITIES */ 240 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 241 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 242 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 243 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 244 245 /* IA32_HWP_REQUEST */ 246 #define HWP_MIN_PERF(x) (x & 0xff) 247 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 248 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 249 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 250 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 251 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 252 253 /* IA32_HWP_STATUS */ 254 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 255 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 256 257 /* IA32_HWP_INTERRUPT */ 258 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 259 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 260 261 #define MSR_AMD64_MC0_MASK 0xc0010044 262 263 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 264 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 265 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 266 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 267 268 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 269 270 /* These are consecutive and not in the normal 4er MCE bank block */ 271 #define MSR_IA32_MC0_CTL2 0x00000280 272 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 273 274 #define MSR_P6_PERFCTR0 0x000000c1 275 #define MSR_P6_PERFCTR1 0x000000c2 276 #define MSR_P6_EVNTSEL0 0x00000186 277 #define MSR_P6_EVNTSEL1 0x00000187 278 279 #define MSR_KNC_PERFCTR0 0x00000020 280 #define MSR_KNC_PERFCTR1 0x00000021 281 #define MSR_KNC_EVNTSEL0 0x00000028 282 #define MSR_KNC_EVNTSEL1 0x00000029 283 284 /* Alternative perfctr range with full access. */ 285 #define MSR_IA32_PMC0 0x000004c1 286 287 /* AMD64 MSRs. Not complete. See the architecture manual for a more 288 complete list. */ 289 290 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 291 #define MSR_AMD64_TSC_RATIO 0xc0000104 292 #define MSR_AMD64_NB_CFG 0xc001001f 293 #define MSR_AMD64_PATCH_LOADER 0xc0010020 294 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 295 #define MSR_AMD64_OSVW_STATUS 0xc0010141 296 #define MSR_AMD64_LS_CFG 0xc0011020 297 #define MSR_AMD64_DC_CFG 0xc0011022 298 #define MSR_AMD64_BU_CFG2 0xc001102a 299 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 300 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 301 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 302 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 303 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 304 #define MSR_AMD64_IBSOPCTL 0xc0011033 305 #define MSR_AMD64_IBSOPRIP 0xc0011034 306 #define MSR_AMD64_IBSOPDATA 0xc0011035 307 #define MSR_AMD64_IBSOPDATA2 0xc0011036 308 #define MSR_AMD64_IBSOPDATA3 0xc0011037 309 #define MSR_AMD64_IBSDCLINAD 0xc0011038 310 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 311 #define MSR_AMD64_IBSOP_REG_COUNT 7 312 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 313 #define MSR_AMD64_IBSCTL 0xc001103a 314 #define MSR_AMD64_IBSBRTARGET 0xc001103b 315 #define MSR_AMD64_IBSOPDATA4 0xc001103d 316 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 317 318 /* Fam 17h MSRs */ 319 #define MSR_F17H_IRPERF 0xc00000e9 320 321 /* Fam 16h MSRs */ 322 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 323 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 324 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 325 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 326 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 327 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 328 329 /* Fam 15h MSRs */ 330 #define MSR_F15H_PERF_CTL 0xc0010200 331 #define MSR_F15H_PERF_CTR 0xc0010201 332 #define MSR_F15H_NB_PERF_CTL 0xc0010240 333 #define MSR_F15H_NB_PERF_CTR 0xc0010241 334 #define MSR_F15H_PTSC 0xc0010280 335 #define MSR_F15H_IC_CFG 0xc0011021 336 337 /* Fam 10h MSRs */ 338 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 339 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 340 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 341 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 342 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 343 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 344 #define MSR_FAM10H_NODE_ID 0xc001100c 345 #define MSR_F10H_DECFG 0xc0011029 346 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 347 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 348 349 /* K8 MSRs */ 350 #define MSR_K8_TOP_MEM1 0xc001001a 351 #define MSR_K8_TOP_MEM2 0xc001001d 352 #define MSR_K8_SYSCFG 0xc0010010 353 #define MSR_K8_INT_PENDING_MSG 0xc0010055 354 /* C1E active bits in int pending message */ 355 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 356 #define MSR_K8_TSEG_ADDR 0xc0010112 357 #define MSR_K8_TSEG_MASK 0xc0010113 358 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 359 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 360 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 361 362 /* K7 MSRs */ 363 #define MSR_K7_EVNTSEL0 0xc0010000 364 #define MSR_K7_PERFCTR0 0xc0010004 365 #define MSR_K7_EVNTSEL1 0xc0010001 366 #define MSR_K7_PERFCTR1 0xc0010005 367 #define MSR_K7_EVNTSEL2 0xc0010002 368 #define MSR_K7_PERFCTR2 0xc0010006 369 #define MSR_K7_EVNTSEL3 0xc0010003 370 #define MSR_K7_PERFCTR3 0xc0010007 371 #define MSR_K7_CLK_CTL 0xc001001b 372 #define MSR_K7_HWCR 0xc0010015 373 #define MSR_K7_FID_VID_CTL 0xc0010041 374 #define MSR_K7_FID_VID_STATUS 0xc0010042 375 376 /* K6 MSRs */ 377 #define MSR_K6_WHCR 0xc0000082 378 #define MSR_K6_UWCCR 0xc0000085 379 #define MSR_K6_EPMR 0xc0000086 380 #define MSR_K6_PSOR 0xc0000087 381 #define MSR_K6_PFIR 0xc0000088 382 383 /* Centaur-Hauls/IDT defined MSRs. */ 384 #define MSR_IDT_FCR1 0x00000107 385 #define MSR_IDT_FCR2 0x00000108 386 #define MSR_IDT_FCR3 0x00000109 387 #define MSR_IDT_FCR4 0x0000010a 388 389 #define MSR_IDT_MCR0 0x00000110 390 #define MSR_IDT_MCR1 0x00000111 391 #define MSR_IDT_MCR2 0x00000112 392 #define MSR_IDT_MCR3 0x00000113 393 #define MSR_IDT_MCR4 0x00000114 394 #define MSR_IDT_MCR5 0x00000115 395 #define MSR_IDT_MCR6 0x00000116 396 #define MSR_IDT_MCR7 0x00000117 397 #define MSR_IDT_MCR_CTRL 0x00000120 398 399 /* VIA Cyrix defined MSRs*/ 400 #define MSR_VIA_FCR 0x00001107 401 #define MSR_VIA_LONGHAUL 0x0000110a 402 #define MSR_VIA_RNG 0x0000110b 403 #define MSR_VIA_BCR2 0x00001147 404 405 /* Transmeta defined MSRs */ 406 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 407 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 408 #define MSR_TMTA_LRTI_READOUT 0x80868018 409 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 410 411 /* Intel defined MSRs. */ 412 #define MSR_IA32_P5_MC_ADDR 0x00000000 413 #define MSR_IA32_P5_MC_TYPE 0x00000001 414 #define MSR_IA32_TSC 0x00000010 415 #define MSR_IA32_PLATFORM_ID 0x00000017 416 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 417 #define MSR_EBC_FREQUENCY_ID 0x0000002c 418 #define MSR_SMI_COUNT 0x00000034 419 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 420 #define MSR_IA32_TSC_ADJUST 0x0000003b 421 #define MSR_IA32_BNDCFGS 0x00000d90 422 423 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 424 425 #define MSR_IA32_XSS 0x00000da0 426 427 #define FEATURE_CONTROL_LOCKED (1<<0) 428 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 429 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 430 #define FEATURE_CONTROL_LMCE (1<<20) 431 432 #define MSR_IA32_APICBASE 0x0000001b 433 #define MSR_IA32_APICBASE_BSP (1<<8) 434 #define MSR_IA32_APICBASE_ENABLE (1<<11) 435 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 436 437 #define MSR_IA32_TSCDEADLINE 0x000006e0 438 439 #define MSR_IA32_UCODE_WRITE 0x00000079 440 #define MSR_IA32_UCODE_REV 0x0000008b 441 442 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 443 #define MSR_IA32_SMBASE 0x0000009e 444 445 #define MSR_IA32_PERF_STATUS 0x00000198 446 #define MSR_IA32_PERF_CTL 0x00000199 447 #define INTEL_PERF_CTL_MASK 0xffff 448 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 449 #define MSR_AMD_PERF_STATUS 0xc0010063 450 #define MSR_AMD_PERF_CTL 0xc0010062 451 452 #define MSR_IA32_MPERF 0x000000e7 453 #define MSR_IA32_APERF 0x000000e8 454 455 #define MSR_IA32_THERM_CONTROL 0x0000019a 456 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 457 458 #define THERM_INT_HIGH_ENABLE (1 << 0) 459 #define THERM_INT_LOW_ENABLE (1 << 1) 460 #define THERM_INT_PLN_ENABLE (1 << 24) 461 462 #define MSR_IA32_THERM_STATUS 0x0000019c 463 464 #define THERM_STATUS_PROCHOT (1 << 0) 465 #define THERM_STATUS_POWER_LIMIT (1 << 10) 466 467 #define MSR_THERM2_CTL 0x0000019d 468 469 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 470 471 #define MSR_IA32_MISC_ENABLE 0x000001a0 472 473 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 474 475 #define MSR_MISC_PWR_MGMT 0x000001aa 476 477 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 478 #define ENERGY_PERF_BIAS_PERFORMANCE 0 479 #define ENERGY_PERF_BIAS_NORMAL 6 480 #define ENERGY_PERF_BIAS_POWERSAVE 15 481 482 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 483 484 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 485 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 486 487 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 488 489 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 490 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 491 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 492 493 /* Thermal Thresholds Support */ 494 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 495 #define THERM_SHIFT_THRESHOLD0 8 496 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 497 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 498 #define THERM_SHIFT_THRESHOLD1 16 499 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 500 #define THERM_STATUS_THRESHOLD0 (1 << 6) 501 #define THERM_LOG_THRESHOLD0 (1 << 7) 502 #define THERM_STATUS_THRESHOLD1 (1 << 8) 503 #define THERM_LOG_THRESHOLD1 (1 << 9) 504 505 /* MISC_ENABLE bits: architectural */ 506 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 507 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 508 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 509 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 510 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 511 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 512 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 513 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 514 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 515 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 516 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 517 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 518 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 519 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 520 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 521 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 522 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 523 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 524 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 525 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 526 527 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 528 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 529 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 530 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 531 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 532 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 533 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 534 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 535 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 536 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 537 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 538 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 539 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 540 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 541 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 542 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 543 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 544 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 545 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 546 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 547 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 548 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 549 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 550 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 551 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 552 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 553 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 554 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 555 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 556 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 557 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 558 559 #define MSR_IA32_TSC_DEADLINE 0x000006E0 560 561 /* P4/Xeon+ specific */ 562 #define MSR_IA32_MCG_EAX 0x00000180 563 #define MSR_IA32_MCG_EBX 0x00000181 564 #define MSR_IA32_MCG_ECX 0x00000182 565 #define MSR_IA32_MCG_EDX 0x00000183 566 #define MSR_IA32_MCG_ESI 0x00000184 567 #define MSR_IA32_MCG_EDI 0x00000185 568 #define MSR_IA32_MCG_EBP 0x00000186 569 #define MSR_IA32_MCG_ESP 0x00000187 570 #define MSR_IA32_MCG_EFLAGS 0x00000188 571 #define MSR_IA32_MCG_EIP 0x00000189 572 #define MSR_IA32_MCG_RESERVED 0x0000018a 573 574 /* Pentium IV performance counter MSRs */ 575 #define MSR_P4_BPU_PERFCTR0 0x00000300 576 #define MSR_P4_BPU_PERFCTR1 0x00000301 577 #define MSR_P4_BPU_PERFCTR2 0x00000302 578 #define MSR_P4_BPU_PERFCTR3 0x00000303 579 #define MSR_P4_MS_PERFCTR0 0x00000304 580 #define MSR_P4_MS_PERFCTR1 0x00000305 581 #define MSR_P4_MS_PERFCTR2 0x00000306 582 #define MSR_P4_MS_PERFCTR3 0x00000307 583 #define MSR_P4_FLAME_PERFCTR0 0x00000308 584 #define MSR_P4_FLAME_PERFCTR1 0x00000309 585 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 586 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 587 #define MSR_P4_IQ_PERFCTR0 0x0000030c 588 #define MSR_P4_IQ_PERFCTR1 0x0000030d 589 #define MSR_P4_IQ_PERFCTR2 0x0000030e 590 #define MSR_P4_IQ_PERFCTR3 0x0000030f 591 #define MSR_P4_IQ_PERFCTR4 0x00000310 592 #define MSR_P4_IQ_PERFCTR5 0x00000311 593 #define MSR_P4_BPU_CCCR0 0x00000360 594 #define MSR_P4_BPU_CCCR1 0x00000361 595 #define MSR_P4_BPU_CCCR2 0x00000362 596 #define MSR_P4_BPU_CCCR3 0x00000363 597 #define MSR_P4_MS_CCCR0 0x00000364 598 #define MSR_P4_MS_CCCR1 0x00000365 599 #define MSR_P4_MS_CCCR2 0x00000366 600 #define MSR_P4_MS_CCCR3 0x00000367 601 #define MSR_P4_FLAME_CCCR0 0x00000368 602 #define MSR_P4_FLAME_CCCR1 0x00000369 603 #define MSR_P4_FLAME_CCCR2 0x0000036a 604 #define MSR_P4_FLAME_CCCR3 0x0000036b 605 #define MSR_P4_IQ_CCCR0 0x0000036c 606 #define MSR_P4_IQ_CCCR1 0x0000036d 607 #define MSR_P4_IQ_CCCR2 0x0000036e 608 #define MSR_P4_IQ_CCCR3 0x0000036f 609 #define MSR_P4_IQ_CCCR4 0x00000370 610 #define MSR_P4_IQ_CCCR5 0x00000371 611 #define MSR_P4_ALF_ESCR0 0x000003ca 612 #define MSR_P4_ALF_ESCR1 0x000003cb 613 #define MSR_P4_BPU_ESCR0 0x000003b2 614 #define MSR_P4_BPU_ESCR1 0x000003b3 615 #define MSR_P4_BSU_ESCR0 0x000003a0 616 #define MSR_P4_BSU_ESCR1 0x000003a1 617 #define MSR_P4_CRU_ESCR0 0x000003b8 618 #define MSR_P4_CRU_ESCR1 0x000003b9 619 #define MSR_P4_CRU_ESCR2 0x000003cc 620 #define MSR_P4_CRU_ESCR3 0x000003cd 621 #define MSR_P4_CRU_ESCR4 0x000003e0 622 #define MSR_P4_CRU_ESCR5 0x000003e1 623 #define MSR_P4_DAC_ESCR0 0x000003a8 624 #define MSR_P4_DAC_ESCR1 0x000003a9 625 #define MSR_P4_FIRM_ESCR0 0x000003a4 626 #define MSR_P4_FIRM_ESCR1 0x000003a5 627 #define MSR_P4_FLAME_ESCR0 0x000003a6 628 #define MSR_P4_FLAME_ESCR1 0x000003a7 629 #define MSR_P4_FSB_ESCR0 0x000003a2 630 #define MSR_P4_FSB_ESCR1 0x000003a3 631 #define MSR_P4_IQ_ESCR0 0x000003ba 632 #define MSR_P4_IQ_ESCR1 0x000003bb 633 #define MSR_P4_IS_ESCR0 0x000003b4 634 #define MSR_P4_IS_ESCR1 0x000003b5 635 #define MSR_P4_ITLB_ESCR0 0x000003b6 636 #define MSR_P4_ITLB_ESCR1 0x000003b7 637 #define MSR_P4_IX_ESCR0 0x000003c8 638 #define MSR_P4_IX_ESCR1 0x000003c9 639 #define MSR_P4_MOB_ESCR0 0x000003aa 640 #define MSR_P4_MOB_ESCR1 0x000003ab 641 #define MSR_P4_MS_ESCR0 0x000003c0 642 #define MSR_P4_MS_ESCR1 0x000003c1 643 #define MSR_P4_PMH_ESCR0 0x000003ac 644 #define MSR_P4_PMH_ESCR1 0x000003ad 645 #define MSR_P4_RAT_ESCR0 0x000003bc 646 #define MSR_P4_RAT_ESCR1 0x000003bd 647 #define MSR_P4_SAAT_ESCR0 0x000003ae 648 #define MSR_P4_SAAT_ESCR1 0x000003af 649 #define MSR_P4_SSU_ESCR0 0x000003be 650 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 651 652 #define MSR_P4_TBPU_ESCR0 0x000003c2 653 #define MSR_P4_TBPU_ESCR1 0x000003c3 654 #define MSR_P4_TC_ESCR0 0x000003c4 655 #define MSR_P4_TC_ESCR1 0x000003c5 656 #define MSR_P4_U2L_ESCR0 0x000003b0 657 #define MSR_P4_U2L_ESCR1 0x000003b1 658 659 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 660 661 /* Intel Core-based CPU performance counters */ 662 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 663 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 664 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 665 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 666 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 667 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 668 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 669 670 /* Geode defined MSRs */ 671 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 672 673 /* Intel VT MSRs */ 674 #define MSR_IA32_VMX_BASIC 0x00000480 675 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 676 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 677 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 678 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 679 #define MSR_IA32_VMX_MISC 0x00000485 680 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 681 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 682 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 683 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 684 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 685 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 686 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 687 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 688 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 689 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 690 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 691 #define MSR_IA32_VMX_VMFUNC 0x00000491 692 693 /* VMX_BASIC bits and bitmasks */ 694 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 695 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 696 #define VMX_BASIC_64 0x0001000000000000LLU 697 #define VMX_BASIC_MEM_TYPE_SHIFT 50 698 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 699 #define VMX_BASIC_MEM_TYPE_WB 6LLU 700 #define VMX_BASIC_INOUT 0x0040000000000000LLU 701 702 /* MSR_IA32_VMX_MISC bits */ 703 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 704 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 705 /* AMD-V MSRs */ 706 707 #define MSR_VM_CR 0xc0010114 708 #define MSR_VM_IGNNE 0xc0010115 709 #define MSR_VM_HSAVE_PA 0xc0010117 710 711 #endif /* _ASM_X86_MSR_INDEX_H */ 712