1 /* 2 * mt2701-afe-common.h -- Mediatek 2701 audio driver definitions 3 * 4 * Copyright (c) 2016 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _MT_2701_AFE_COMMON_H_ 18 #define _MT_2701_AFE_COMMON_H_ 19 #include <sound/soc.h> 20 #include <linux/clk.h> 21 #include <linux/regmap.h> 22 #include "mt2701-reg.h" 23 #include "../common/mtk-base-afe.h" 24 25 #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) 26 #define MT2701_PLL_DOMAIN_0_RATE 98304000 27 #define MT2701_PLL_DOMAIN_1_RATE 90316800 28 #define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) 29 #define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2) 30 31 enum { 32 MT2701_I2S_1, 33 MT2701_I2S_2, 34 MT2701_I2S_3, 35 MT2701_I2S_4, 36 MT2701_I2S_NUM, 37 }; 38 39 enum { 40 MT2701_MEMIF_DL1, 41 MT2701_MEMIF_DL2, 42 MT2701_MEMIF_DL3, 43 MT2701_MEMIF_DL4, 44 MT2701_MEMIF_DL5, 45 MT2701_MEMIF_DL_SINGLE_NUM, 46 MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM, 47 MT2701_MEMIF_UL1, 48 MT2701_MEMIF_UL2, 49 MT2701_MEMIF_UL3, 50 MT2701_MEMIF_UL4, 51 MT2701_MEMIF_UL5, 52 MT2701_MEMIF_DLBT, 53 MT2701_MEMIF_ULBT, 54 MT2701_MEMIF_NUM, 55 MT2701_IO_I2S = MT2701_MEMIF_NUM, 56 MT2701_IO_2ND_I2S, 57 MT2701_IO_3RD_I2S, 58 MT2701_IO_4TH_I2S, 59 MT2701_IO_5TH_I2S, 60 MT2701_IO_6TH_I2S, 61 MT2701_IO_MRG, 62 }; 63 64 enum { 65 MT2701_IRQ_ASYS_START, 66 MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START, 67 MT2701_IRQ_ASYS_IRQ2, 68 MT2701_IRQ_ASYS_IRQ3, 69 MT2701_IRQ_ASYS_END, 70 }; 71 72 /* 2701 clock def */ 73 enum audio_system_clock_type { 74 MT2701_AUD_INFRA_SYS_AUDIO, 75 MT2701_AUD_AUD_MUX1_SEL, 76 MT2701_AUD_AUD_MUX2_SEL, 77 MT2701_AUD_AUD_MUX1_DIV, 78 MT2701_AUD_AUD_MUX2_DIV, 79 MT2701_AUD_AUD_48K_TIMING, 80 MT2701_AUD_AUD_44K_TIMING, 81 MT2701_AUD_AUDPLL_MUX_SEL, 82 MT2701_AUD_APLL_SEL, 83 MT2701_AUD_AUD1PLL_98M, 84 MT2701_AUD_AUD2PLL_90M, 85 MT2701_AUD_HADDS2PLL_98M, 86 MT2701_AUD_HADDS2PLL_294M, 87 MT2701_AUD_AUDPLL, 88 MT2701_AUD_AUDPLL_D4, 89 MT2701_AUD_AUDPLL_D8, 90 MT2701_AUD_AUDPLL_D16, 91 MT2701_AUD_AUDPLL_D24, 92 MT2701_AUD_AUDINTBUS, 93 MT2701_AUD_CLK_26M, 94 MT2701_AUD_SYSPLL1_D4, 95 MT2701_AUD_AUD_K1_SRC_SEL, 96 MT2701_AUD_AUD_K2_SRC_SEL, 97 MT2701_AUD_AUD_K3_SRC_SEL, 98 MT2701_AUD_AUD_K4_SRC_SEL, 99 MT2701_AUD_AUD_K5_SRC_SEL, 100 MT2701_AUD_AUD_K6_SRC_SEL, 101 MT2701_AUD_AUD_K1_SRC_DIV, 102 MT2701_AUD_AUD_K2_SRC_DIV, 103 MT2701_AUD_AUD_K3_SRC_DIV, 104 MT2701_AUD_AUD_K4_SRC_DIV, 105 MT2701_AUD_AUD_K5_SRC_DIV, 106 MT2701_AUD_AUD_K6_SRC_DIV, 107 MT2701_AUD_AUD_I2S1_MCLK, 108 MT2701_AUD_AUD_I2S2_MCLK, 109 MT2701_AUD_AUD_I2S3_MCLK, 110 MT2701_AUD_AUD_I2S4_MCLK, 111 MT2701_AUD_AUD_I2S5_MCLK, 112 MT2701_AUD_AUD_I2S6_MCLK, 113 MT2701_AUD_ASM_M_SEL, 114 MT2701_AUD_ASM_H_SEL, 115 MT2701_AUD_UNIVPLL2_D4, 116 MT2701_AUD_UNIVPLL2_D2, 117 MT2701_AUD_SYSPLL_D5, 118 MT2701_CLOCK_NUM 119 }; 120 121 static const unsigned int mt2701_afe_backup_list[] = { 122 AUDIO_TOP_CON0, 123 AUDIO_TOP_CON4, 124 AUDIO_TOP_CON5, 125 ASYS_TOP_CON, 126 AFE_CONN0, 127 AFE_CONN1, 128 AFE_CONN2, 129 AFE_CONN3, 130 AFE_CONN15, 131 AFE_CONN16, 132 AFE_CONN17, 133 AFE_CONN18, 134 AFE_CONN19, 135 AFE_CONN20, 136 AFE_CONN21, 137 AFE_CONN22, 138 AFE_DAC_CON0, 139 AFE_MEMIF_PBUF_SIZE, 140 }; 141 142 struct snd_pcm_substream; 143 struct mtk_base_irq_data; 144 145 struct mt2701_i2s_data { 146 int i2s_ctrl_reg; 147 int i2s_pwn_shift; 148 int i2s_asrc_fs_shift; 149 int i2s_asrc_fs_mask; 150 }; 151 152 enum mt2701_i2s_dir { 153 I2S_OUT, 154 I2S_IN, 155 I2S_DIR_NUM, 156 }; 157 158 struct mt2701_i2s_path { 159 int dai_id; 160 int mclk_rate; 161 int on[I2S_DIR_NUM]; 162 int occupied[I2S_DIR_NUM]; 163 const struct mt2701_i2s_data *i2s_data[2]; 164 }; 165 166 struct mt2701_afe_private { 167 struct clk *clocks[MT2701_CLOCK_NUM]; 168 struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; 169 bool mrg_enable[MT2701_STREAM_DIR_NUM]; 170 }; 171 172 #endif 173