1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2015 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22
23 /*! \file octeon_device.h
24 * \brief Host Driver: This file defines the octeon device structure.
25 */
26
27 #ifndef _OCTEON_DEVICE_H_
28 #define _OCTEON_DEVICE_H_
29
30 /** PCI VendorId Device Id */
31 #define OCTEON_CN68XX_PCIID 0x91177d
32 #define OCTEON_CN66XX_PCIID 0x92177d
33 #define OCTEON_CN23XX_PCIID_PF 0x9702177d
34 /** Driver identifies chips by these Ids, created by clubbing together
35 * DeviceId+RevisionId; Where Revision Id is not used to distinguish
36 * between chips, a value of 0 is used for revision id.
37 */
38 #define OCTEON_CN68XX 0x0091
39 #define OCTEON_CN66XX 0x0092
40 #define OCTEON_CN23XX_PF_VID 0x9702
41
42 /**RevisionId for the chips */
43 #define OCTEON_CN23XX_REV_1_0 0x00
44 #define OCTEON_CN23XX_REV_1_1 0x01
45 #define OCTEON_CN23XX_REV_2_0 0x80
46
47 /** Endian-swap modes supported by Octeon. */
48 enum octeon_pci_swap_mode {
49 OCTEON_PCI_PASSTHROUGH = 0,
50 OCTEON_PCI_64BIT_SWAP = 1,
51 OCTEON_PCI_32BIT_BYTE_SWAP = 2,
52 OCTEON_PCI_32BIT_LW_SWAP = 3
53 };
54
55 #define OCTEON_OUTPUT_INTR (2)
56 #define OCTEON_ALL_INTR 0xff
57
58 /*--------------- PCI BAR1 index registers -------------*/
59
60 /* BAR1 Mask */
61 #define PCI_BAR1_ENABLE_CA 1
62 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP
63 #define PCI_BAR1_ENTRY_VALID 1
64 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \
65 | (PCI_BAR1_ENDIAN_MODE << 1) \
66 | PCI_BAR1_ENTRY_VALID)
67
68 /** Octeon Device state.
69 * Each octeon device goes through each of these states
70 * as it is initialized.
71 */
72 #define OCT_DEV_BEGIN_STATE 0x0
73 #define OCT_DEV_PCI_MAP_DONE 0x1
74 #define OCT_DEV_DISPATCH_INIT_DONE 0x2
75 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x3
76 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4
77 #define OCT_DEV_RESP_LIST_INIT_DONE 0x5
78 #define OCT_DEV_DROQ_INIT_DONE 0x6
79 #define OCT_DEV_IO_QUEUES_DONE 0x7
80 #define OCT_DEV_CONSOLE_INIT_DONE 0x8
81 #define OCT_DEV_HOST_OK 0x9
82 #define OCT_DEV_CORE_OK 0xa
83 #define OCT_DEV_RUNNING 0xb
84 #define OCT_DEV_IN_RESET 0xc
85 #define OCT_DEV_STATE_INVALID 0xd
86
87 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID
88
89 /** Octeon Device interrupts
90 * These interrupt bits are set in int_status filed of
91 * octeon_device structure
92 */
93 #define OCT_DEV_INTR_DMA0_FORCE 0x01
94 #define OCT_DEV_INTR_DMA1_FORCE 0x02
95 #define OCT_DEV_INTR_PKT_DATA 0x04
96
97 #define LIO_RESET_SECS (3)
98
99 /*---------------------------DISPATCH LIST-------------------------------*/
100
101 /** The dispatch list entry.
102 * The driver keeps a record of functions registered for each
103 * response header opcode in this structure. Since the opcode is
104 * hashed to index into the driver's list, more than one opcode
105 * can hash to the same entry, in which case the list field points
106 * to a linked list with the other entries.
107 */
108 struct octeon_dispatch {
109 /** List head for this entry */
110 struct list_head list;
111
112 /** The opcode for which the dispatch function & arg should be used */
113 u16 opcode;
114
115 /** The function to be called for a packet received by the driver */
116 octeon_dispatch_fn_t dispatch_fn;
117
118 /* The application specified argument to be passed to the above
119 * function along with the received packet
120 */
121 void *arg;
122 };
123
124 /** The dispatch list structure. */
125 struct octeon_dispatch_list {
126 /** access to dispatch list must be atomic */
127 spinlock_t lock;
128
129 /** Count of dispatch functions currently registered */
130 u32 count;
131
132 /** The list of dispatch functions */
133 struct octeon_dispatch *dlist;
134 };
135
136 /*----------------------- THE OCTEON DEVICE ---------------------------*/
137
138 #define OCT_MEM_REGIONS 3
139 /** PCI address space mapping information.
140 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
141 * Octeon gets mapped to different physical address spaces in
142 * the kernel.
143 */
144 struct octeon_mmio {
145 /** PCI address to which the BAR is mapped. */
146 u64 start;
147
148 /** Length of this PCI address space. */
149 u32 len;
150
151 /** Length that has been mapped to phys. address space. */
152 u32 mapped_len;
153
154 /** The physical address to which the PCI address space is mapped. */
155 u8 __iomem *hw_addr;
156
157 /** Flag indicating the mapping was successful. */
158 u32 done;
159 };
160
161 #define MAX_OCTEON_MAPS 32
162
163 struct octeon_io_enable {
164 u64 iq;
165 u64 oq;
166 u64 iq64B;
167 };
168
169 struct octeon_reg_list {
170 u32 __iomem *pci_win_wr_addr_hi;
171 u32 __iomem *pci_win_wr_addr_lo;
172 u64 __iomem *pci_win_wr_addr;
173
174 u32 __iomem *pci_win_rd_addr_hi;
175 u32 __iomem *pci_win_rd_addr_lo;
176 u64 __iomem *pci_win_rd_addr;
177
178 u32 __iomem *pci_win_wr_data_hi;
179 u32 __iomem *pci_win_wr_data_lo;
180 u64 __iomem *pci_win_wr_data;
181
182 u32 __iomem *pci_win_rd_data_hi;
183 u32 __iomem *pci_win_rd_data_lo;
184 u64 __iomem *pci_win_rd_data;
185 };
186
187 #define OCTEON_CONSOLE_MAX_READ_BYTES 512
188 struct octeon_console {
189 u32 active;
190 u32 waiting;
191 u64 addr;
192 u32 buffer_size;
193 u64 input_base_addr;
194 u64 output_base_addr;
195 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES];
196 };
197
198 struct octeon_board_info {
199 char name[OCT_BOARD_NAME];
200 char serial_number[OCT_SERIAL_LEN];
201 u64 major;
202 u64 minor;
203 };
204
205 struct octeon_fn_list {
206 void (*setup_iq_regs)(struct octeon_device *, u32);
207 void (*setup_oq_regs)(struct octeon_device *, u32);
208
209 irqreturn_t (*process_interrupt_regs)(void *);
210 u64 (*msix_interrupt_handler)(void *);
211 int (*soft_reset)(struct octeon_device *);
212 int (*setup_device_regs)(struct octeon_device *);
213 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int);
214 void (*bar1_idx_write)(struct octeon_device *, u32, u32);
215 u32 (*bar1_idx_read)(struct octeon_device *, u32);
216 u32 (*update_iq_read_idx)(struct octeon_instr_queue *);
217
218 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32);
219 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32);
220
221 void (*enable_interrupt)(struct octeon_device *, u8);
222 void (*disable_interrupt)(struct octeon_device *, u8);
223
224 int (*enable_io_queues)(struct octeon_device *);
225 void (*disable_io_queues)(struct octeon_device *);
226 };
227
228 /* Must be multiple of 8, changing breaks ABI */
229 #define CVMX_BOOTMEM_NAME_LEN 128
230
231 /* Structure for named memory blocks
232 * Number of descriptors
233 * available can be changed without affecting compatibility,
234 * but name length changes require a bump in the bootmem
235 * descriptor version
236 * Note: This structure must be naturally 64 bit aligned, as a single
237 * memory image will be used by both 32 and 64 bit programs.
238 */
239 struct cvmx_bootmem_named_block_desc {
240 /** Base address of named block */
241 u64 base_addr;
242
243 /** Size actually allocated for named block */
244 u64 size;
245
246 /** name of named block */
247 char name[CVMX_BOOTMEM_NAME_LEN];
248 };
249
250 struct oct_fw_info {
251 u32 max_nic_ports; /** max nic ports for the device */
252 u32 num_gmx_ports; /** num gmx ports */
253 u64 app_cap_flags; /** firmware cap flags */
254
255 /** The core application is running in this mode.
256 * See octeon-drv-opcodes.h for values.
257 */
258 u32 app_mode;
259 char liquidio_firmware_version[32];
260 };
261
262 /* wrappers around work structs */
263 struct cavium_wk {
264 struct delayed_work work;
265 void *ctxptr;
266 u64 ctxul;
267 };
268
269 struct cavium_wq {
270 struct workqueue_struct *wq;
271 struct cavium_wk wk;
272 };
273
274 struct octdev_props {
275 /* Each interface in the Octeon device has a network
276 * device pointer (used for OS specific calls).
277 */
278 int rx_on;
279 int napi_enabled;
280 int gmxport;
281 struct net_device *netdev;
282 };
283
284 #define LIO_FLAG_MSIX_ENABLED 0x1
285 #define MSIX_PO_INT 0x1
286 #define MSIX_PI_INT 0x2
287
288 struct octeon_pf_vf_hs_word {
289 #ifdef __LITTLE_ENDIAN_BITFIELD
290 /** PKIND value assigned for the DPI interface */
291 u64 pkind : 8;
292
293 /** OCTEON core clock multiplier */
294 u64 core_tics_per_us : 16;
295
296 /** OCTEON coprocessor clock multiplier */
297 u64 coproc_tics_per_us : 16;
298
299 /** app that currently running on OCTEON */
300 u64 app_mode : 8;
301
302 /** RESERVED */
303 u64 reserved : 16;
304
305 #else
306
307 /** RESERVED */
308 u64 reserved : 16;
309
310 /** app that currently running on OCTEON */
311 u64 app_mode : 8;
312
313 /** OCTEON coprocessor clock multiplier */
314 u64 coproc_tics_per_us : 16;
315
316 /** OCTEON core clock multiplier */
317 u64 core_tics_per_us : 16;
318
319 /** PKIND value assigned for the DPI interface */
320 u64 pkind : 8;
321 #endif
322 };
323
324 struct octeon_sriov_info {
325 /* Actual rings left for PF device */
326 u32 num_pf_rings;
327
328 /* SRN of PF usable IO queues */
329 u32 pf_srn;
330 /* total pf rings */
331 u32 trs;
332
333 };
334
335 struct octeon_ioq_vector {
336 struct octeon_device *oct_dev;
337 int iq_index;
338 int droq_index;
339 int vector;
340 struct cpumask affinity_mask;
341 u32 ioq_num;
342 };
343
344 /** The Octeon device.
345 * Each Octeon device has this structure to represent all its
346 * components.
347 */
348 struct octeon_device {
349 /** Lock for PCI window configuration accesses */
350 spinlock_t pci_win_lock;
351
352 /** Lock for memory accesses */
353 spinlock_t mem_access_lock;
354
355 /** PCI device pointer */
356 struct pci_dev *pci_dev;
357
358 /** Chip specific information. */
359 void *chip;
360
361 /** Number of interfaces detected in this octeon device. */
362 u32 ifcount;
363
364 struct octdev_props props[MAX_OCTEON_LINKS];
365
366 /** Octeon Chip type. */
367 u16 chip_id;
368 u16 rev_id;
369 u16 pf_num;
370 /** This device's id - set by the driver. */
371 u32 octeon_id;
372
373 /** This device's PCIe port used for traffic. */
374 u16 pcie_port;
375
376 u16 flags;
377 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1)
378
379 /** The state of this device */
380 atomic_t status;
381
382 /** memory mapped io range */
383 struct octeon_mmio mmio[OCT_MEM_REGIONS];
384
385 struct octeon_reg_list reg_list;
386
387 struct octeon_fn_list fn_list;
388
389 struct octeon_board_info boardinfo;
390
391 u32 num_iqs;
392
393 /* The pool containing pre allocated buffers used for soft commands */
394 struct octeon_sc_buffer_pool sc_buf_pool;
395
396 /** The input instruction queues */
397 struct octeon_instr_queue *instr_queue
398 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
399
400 /** The doubly-linked list of instruction response */
401 struct octeon_response_list response_list[MAX_RESPONSE_LISTS];
402
403 u32 num_oqs;
404
405 /** The DROQ output queues */
406 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES];
407
408 struct octeon_io_enable io_qmask;
409
410 /** List of dispatch functions */
411 struct octeon_dispatch_list dispatch;
412
413 /* Interrupt Moderation */
414 struct oct_intrmod_cfg intrmod;
415
416 u32 int_status;
417
418 u64 droq_intr;
419
420 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */
421 u64 bootmem_desc_addr;
422
423 /** Placeholder memory for named blocks.
424 * Assumes single-threaded access
425 */
426 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
427
428 /** Address of consoles descriptor */
429 u64 console_desc_addr;
430
431 /** Number of consoles available. 0 means they are inaccessible */
432 u32 num_consoles;
433
434 /* Console caches */
435 struct octeon_console console[MAX_OCTEON_MAPS];
436
437 /* Coprocessor clock rate. */
438 u64 coproc_clock_rate;
439
440 /** The core application is running in this mode. See liquidio_common.h
441 * for values.
442 */
443 u32 app_mode;
444
445 struct oct_fw_info fw_info;
446
447 /** The name given to this device. */
448 char device_name[32];
449
450 /** Application Context */
451 void *app_ctx;
452
453 struct cavium_wq dma_comp_wq;
454
455 /** Lock for dma response list */
456 spinlock_t cmd_resp_wqlock;
457 u32 cmd_resp_state;
458
459 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES];
460
461 struct cavium_wk nic_poll_work;
462
463 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS];
464
465 void *priv;
466
467 int num_msix_irqs;
468
469 void *msix_entries;
470
471 struct octeon_sriov_info sriov_info;
472
473 struct octeon_pf_vf_hs_word pfvf_hsword;
474
475 int msix_on;
476
477 /** IOq information of it's corresponding MSI-X interrupt. */
478 struct octeon_ioq_vector *ioq_vector;
479
480 int rx_pause;
481 int tx_pause;
482
483 struct oct_link_stats link_stats; /*stastics from firmware*/
484
485 /* private flags to control driver-specific features through ethtool */
486 u32 priv_flags;
487
488 void *watchdog_task;
489 };
490
491 #define OCT_DRV_ONLINE 1
492 #define OCT_DRV_OFFLINE 2
493 #define OCTEON_CN6XXX(oct) ((oct->chip_id == OCTEON_CN66XX) || \
494 (oct->chip_id == OCTEON_CN68XX))
495 #define OCTEON_CN23XX_PF(oct) (oct->chip_id == OCTEON_CN23XX_PF_VID)
496 #define CHIP_FIELD(oct, TYPE, field) \
497 (((struct octeon_ ## TYPE *)(oct->chip))->field)
498
499 struct oct_intrmod_cmd {
500 struct octeon_device *oct_dev;
501 struct octeon_soft_command *sc;
502 struct oct_intrmod_cfg *cfg;
503 };
504
505 /*------------------ Function Prototypes ----------------------*/
506
507 /** Initialize device list memory */
508 void octeon_init_device_list(int conf_type);
509
510 /** Free memory for Input and Output queue structures for a octeon device */
511 void octeon_free_device_mem(struct octeon_device *);
512
513 /* Look up a free entry in the octeon_device table and allocate resources
514 * for the octeon_device structure for an octeon device. Called at init
515 * time.
516 */
517 struct octeon_device *octeon_allocate_device(u32 pci_id,
518 u32 priv_size);
519
520 /** Initialize the driver's dispatch list which is a mix of a hash table
521 * and a linked list. This is done at driver load time.
522 * @param octeon_dev - pointer to the octeon device structure.
523 * @return 0 on success, else -ve error value
524 */
525 int octeon_init_dispatch_list(struct octeon_device *octeon_dev);
526
527 /** Delete the driver's dispatch list and all registered entries.
528 * This is done at driver unload time.
529 * @param octeon_dev - pointer to the octeon device structure.
530 */
531 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev);
532
533 /** Initialize the core device fields with the info returned by the FW.
534 * @param recv_info - Receive info structure
535 * @param buf - Receive buffer
536 */
537 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf);
538
539 /** Gets the dispatch function registered to receive packets with a
540 * given opcode/subcode.
541 * @param octeon_dev - the octeon device pointer.
542 * @param opcode - the opcode for which the dispatch function
543 * is to checked.
544 * @param subcode - the subcode for which the dispatch function
545 * is to checked.
546 *
547 * @return Success: octeon_dispatch_fn_t (dispatch function pointer)
548 * @return Failure: NULL
549 *
550 * Looks up the dispatch list to get the dispatch function for a
551 * given opcode.
552 */
553 octeon_dispatch_fn_t
554 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
555 u16 subcode);
556
557 /** Get the octeon device pointer.
558 * @param octeon_id - The id for which the octeon device pointer is required.
559 * @return Success: Octeon device pointer.
560 * @return Failure: NULL.
561 */
562 struct octeon_device *lio_get_device(u32 octeon_id);
563
564 /** Get the octeon id assigned to the octeon device passed as argument.
565 * This function is exported to other modules.
566 * @param dev - octeon device pointer passed as a void *.
567 * @return octeon device id
568 */
569 int lio_get_device_id(void *dev);
570
OCTEON_MAJOR_REV(struct octeon_device * oct)571 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct)
572 {
573 u16 rev = (oct->rev_id & 0xC) >> 2;
574
575 return (rev == 0) ? 1 : rev;
576 }
577
OCTEON_MINOR_REV(struct octeon_device * oct)578 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct)
579 {
580 return oct->rev_id & 0x3;
581 }
582
583 /** Read windowed register.
584 * @param oct - pointer to the Octeon device.
585 * @param addr - Address of the register to read.
586 *
587 * This routine is called to read from the indirectly accessed
588 * Octeon registers that are visible through a PCI BAR0 mapped window
589 * register.
590 * @return - 64 bit value read from the register.
591 */
592
593 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
594
595 /** Write windowed register.
596 * @param oct - pointer to the Octeon device.
597 * @param val - Value to write
598 * @param addr - Address of the register to write
599 *
600 * This routine is called to write to the indirectly accessed
601 * Octeon registers that are visible through a PCI BAR0 mapped window
602 * register.
603 * @return Nothing.
604 */
605 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);
606
607 /* Routines for reading and writing CSRs */
608 #define octeon_write_csr(oct_dev, reg_off, value) \
609 writel(value, oct_dev->mmio[0].hw_addr + reg_off)
610
611 #define octeon_write_csr64(oct_dev, reg_off, val64) \
612 writeq(val64, oct_dev->mmio[0].hw_addr + reg_off)
613
614 #define octeon_read_csr(oct_dev, reg_off) \
615 readl(oct_dev->mmio[0].hw_addr + reg_off)
616
617 #define octeon_read_csr64(oct_dev, reg_off) \
618 readq(oct_dev->mmio[0].hw_addr + reg_off)
619
620 /**
621 * Checks if memory access is okay
622 *
623 * @param oct which octeon to send to
624 * @return Zero on success, negative on failure.
625 */
626 int octeon_mem_access_ok(struct octeon_device *oct);
627
628 /**
629 * Waits for DDR initialization.
630 *
631 * @param oct which octeon to send to
632 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
633 * in ms.
634 * If contents are 0, it waits until contents are non-zero
635 * before starting to check.
636 * @return Zero on success, negative on failure.
637 */
638 int octeon_wait_for_ddr_init(struct octeon_device *oct,
639 u32 *timeout_in_ms);
640
641 /**
642 * Wait for u-boot to boot and be waiting for a command.
643 *
644 * @param wait_time_hundredths
645 * Maximum time to wait
646 *
647 * @return Zero on success, negative on failure.
648 */
649 int octeon_wait_for_bootloader(struct octeon_device *oct,
650 u32 wait_time_hundredths);
651
652 /**
653 * Initialize console access
654 *
655 * @param oct which octeon initialize
656 * @return Zero on success, negative on failure.
657 */
658 int octeon_init_consoles(struct octeon_device *oct);
659
660 /**
661 * Adds access to a console to the device.
662 *
663 * @param oct which octeon to add to
664 * @param console_num which console
665 * @return Zero on success, negative on failure.
666 */
667 int octeon_add_console(struct octeon_device *oct, u32 console_num);
668
669 /** write or read from a console */
670 int octeon_console_write(struct octeon_device *oct, u32 console_num,
671 char *buffer, u32 write_request_size, u32 flags);
672 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num);
673
674 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num);
675
676 /** Removes all attached consoles. */
677 void octeon_remove_consoles(struct octeon_device *oct);
678
679 /**
680 * Send a string to u-boot on console 0 as a command.
681 *
682 * @param oct which octeon to send to
683 * @param cmd_str String to send
684 * @param wait_hundredths Time to wait for u-boot to accept the command.
685 *
686 * @return Zero on success, negative on failure.
687 */
688 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
689 u32 wait_hundredths);
690
691 /** Parses, validates, and downloads firmware, then boots associated cores.
692 * @param oct which octeon to download firmware to
693 * @param data - The complete firmware file image
694 * @param size - The size of the data
695 *
696 * @return 0 if success.
697 * -EINVAL if file is incompatible or badly formatted.
698 * -ENODEV if no handler was found for the application type or an
699 * invalid octeon id was passed.
700 */
701 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
702 size_t size);
703
704 char *lio_get_state_string(atomic_t *state_ptr);
705
706 /** Sets up instruction queues for the device
707 * @param oct which octeon to setup
708 *
709 * @return 0 if success. 1 if fails
710 */
711 int octeon_setup_instr_queues(struct octeon_device *oct);
712
713 /** Sets up output queues for the device
714 * @param oct which octeon to setup
715 *
716 * @return 0 if success. 1 if fails
717 */
718 int octeon_setup_output_queues(struct octeon_device *oct);
719
720 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no);
721
722 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no);
723
724 /** Turns off the input and output queues for the device
725 * @param oct which octeon to disable
726 */
727 void octeon_set_io_queues_off(struct octeon_device *oct);
728
729 /** Turns on or off the given output queue for the device
730 * @param oct which octeon to change
731 * @param q_no which queue
732 * @param enable 1 to enable, 0 to disable
733 */
734 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable);
735
736 /** Retrieve the config for the device
737 * @param oct which octeon
738 * @param card_type type of card
739 *
740 * @returns pointer to configuration
741 */
742 void *oct_get_config_info(struct octeon_device *oct, u16 card_type);
743
744 /** Gets the octeon device configuration
745 * @return - pointer to the octeon configuration struture
746 */
747 struct octeon_config *octeon_get_conf(struct octeon_device *oct);
748
749 void octeon_free_ioq_vector(struct octeon_device *oct);
750 int octeon_allocate_ioq_vector(struct octeon_device *oct);
751 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq);
752
753 /* LiquidIO driver pivate flags */
754 enum {
755 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */
756 };
757
758 #define OCT_PRIV_FLAG_DEFAULT 0x0
759
lio_get_priv_flag(struct octeon_device * octdev,u32 flag)760 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag)
761 {
762 return !!(octdev->priv_flags & (0x1 << flag));
763 }
764
lio_set_priv_flag(struct octeon_device * octdev,u32 flag,u32 val)765 static inline void lio_set_priv_flag(struct octeon_device *octdev,
766 u32 flag, u32 val)
767 {
768 if (val)
769 octdev->priv_flags |= (0x1 << flag);
770 else
771 octdev->priv_flags &= ~(0x1 << flag);
772 }
773 #endif
774