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1 /*
2  * rcar_du_regs.h  --  R-Car Display Unit Registers Definitions
3  *
4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
5  *
6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2
10  * as published by the Free Software Foundation.
11  */
12 
13 #ifndef __RCAR_DU_REGS_H__
14 #define __RCAR_DU_REGS_H__
15 
16 #define DU0_REG_OFFSET		0x00000
17 #define DU1_REG_OFFSET		0x30000
18 #define DU2_REG_OFFSET		0x40000
19 #define DU3_REG_OFFSET		0x70000
20 
21 /* -----------------------------------------------------------------------------
22  * Display Control Registers
23  */
24 
25 #define DSYSR			0x00000	/* display 1 */
26 #define DSYSR_ILTS		(1 << 29)
27 #define DSYSR_DSEC		(1 << 20)
28 #define DSYSR_IUPD		(1 << 16)
29 #define DSYSR_DRES		(1 << 9)
30 #define DSYSR_DEN		(1 << 8)
31 #define DSYSR_TVM_MASTER	(0 << 6)
32 #define DSYSR_TVM_SWITCH	(1 << 6)
33 #define DSYSR_TVM_TVSYNC	(2 << 6)
34 #define DSYSR_TVM_MASK		(3 << 6)
35 #define DSYSR_SCM_INT_NONE	(0 << 4)
36 #define DSYSR_SCM_INT_SYNC	(2 << 4)
37 #define DSYSR_SCM_INT_VIDEO	(3 << 4)
38 #define DSYSR_SCM_MASK		(3 << 4)
39 
40 #define DSMR			0x00004
41 #define DSMR_VSPM		(1 << 28)
42 #define DSMR_ODPM		(1 << 27)
43 #define DSMR_DIPM_DISP		(0 << 25)
44 #define DSMR_DIPM_CSYNC		(1 << 25)
45 #define DSMR_DIPM_DE		(3 << 25)
46 #define DSMR_DIPM_MASK		(3 << 25)
47 #define DSMR_CSPM		(1 << 24)
48 #define DSMR_DIL		(1 << 19)
49 #define DSMR_VSL		(1 << 18)
50 #define DSMR_HSL		(1 << 17)
51 #define DSMR_DDIS		(1 << 16)
52 #define DSMR_CDEL		(1 << 15)
53 #define DSMR_CDEM_CDE		(0 << 13)
54 #define DSMR_CDEM_LOW		(2 << 13)
55 #define DSMR_CDEM_HIGH		(3 << 13)
56 #define DSMR_CDEM_MASK		(3 << 13)
57 #define DSMR_CDED		(1 << 12)
58 #define DSMR_ODEV		(1 << 8)
59 #define DSMR_CSY_VH_OR		(0 << 6)
60 #define DSMR_CSY_333		(2 << 6)
61 #define DSMR_CSY_222		(3 << 6)
62 #define DSMR_CSY_MASK		(3 << 6)
63 
64 #define DSSR			0x00008
65 #define DSSR_VC1FB_DSA0		(0 << 30)
66 #define DSSR_VC1FB_DSA1		(1 << 30)
67 #define DSSR_VC1FB_DSA2		(2 << 30)
68 #define DSSR_VC1FB_INIT		(3 << 30)
69 #define DSSR_VC1FB_MASK		(3 << 30)
70 #define DSSR_VC0FB_DSA0		(0 << 28)
71 #define DSSR_VC0FB_DSA1		(1 << 28)
72 #define DSSR_VC0FB_DSA2		(2 << 28)
73 #define DSSR_VC0FB_INIT		(3 << 28)
74 #define DSSR_VC0FB_MASK		(3 << 28)
75 #define DSSR_DFB(n)		(1 << ((n)+15))
76 #define DSSR_TVR		(1 << 15)
77 #define DSSR_FRM		(1 << 14)
78 #define DSSR_VBK		(1 << 11)
79 #define DSSR_RINT		(1 << 9)
80 #define DSSR_HBK		(1 << 8)
81 #define DSSR_ADC(n)		(1 << ((n)-1))
82 
83 #define DSRCR			0x0000c
84 #define DSRCR_TVCL		(1 << 15)
85 #define DSRCR_FRCL		(1 << 14)
86 #define DSRCR_VBCL		(1 << 11)
87 #define DSRCR_RICL		(1 << 9)
88 #define DSRCR_HBCL		(1 << 8)
89 #define DSRCR_ADCL(n)		(1 << ((n)-1))
90 #define DSRCR_MASK		0x0000cbff
91 
92 #define DIER			0x00010
93 #define DIER_TVE		(1 << 15)
94 #define DIER_FRE		(1 << 14)
95 #define DIER_VBE		(1 << 11)
96 #define DIER_RIE		(1 << 9)
97 #define DIER_HBE		(1 << 8)
98 #define DIER_ADCE(n)		(1 << ((n)-1))
99 
100 #define CPCR			0x00014
101 #define CPCR_CP4CE		(1 << 19)
102 #define CPCR_CP3CE		(1 << 18)
103 #define CPCR_CP2CE		(1 << 17)
104 #define CPCR_CP1CE		(1 << 16)
105 
106 #define DPPR			0x00018
107 #define DPPR_DPE(n)		(1 << ((n)*4-1))
108 #define DPPR_DPS(n, p)		(((p)-1) << DPPR_DPS_SHIFT(n))
109 #define DPPR_DPS_SHIFT(n)	(((n)-1)*4)
110 #define DPPR_BPP16		(DPPR_DPE(8) | DPPR_DPS(8, 1))	/* plane1 */
111 #define DPPR_BPP32_P1		(DPPR_DPE(7) | DPPR_DPS(7, 1))
112 #define DPPR_BPP32_P2		(DPPR_DPE(8) | DPPR_DPS(8, 2))
113 #define DPPR_BPP32		(DPPR_BPP32_P1 | DPPR_BPP32_P2)	/* plane1 & 2 */
114 
115 #define DEFR			0x00020
116 #define DEFR_CODE		(0x7773 << 16)
117 #define DEFR_EXSL		(1 << 12)
118 #define DEFR_EXVL		(1 << 11)
119 #define DEFR_EXUP		(1 << 5)
120 #define DEFR_VCUP		(1 << 4)
121 #define DEFR_DEFE		(1 << 0)
122 
123 #define DAPCR			0x00024
124 #define DAPCR_CODE		(0x7773 << 16)
125 #define DAPCR_AP2E		(1 << 4)
126 #define DAPCR_AP1E		(1 << 0)
127 
128 #define DCPCR			0x00028
129 #define DCPCR_CODE		(0x7773 << 16)
130 #define DCPCR_CA2B		(1 << 13)
131 #define DCPCR_CD2F		(1 << 12)
132 #define DCPCR_DC2E		(1 << 8)
133 #define DCPCR_CAB		(1 << 5)
134 #define DCPCR_CDF		(1 << 4)
135 #define DCPCR_DCE		(1 << 0)
136 
137 #define DEFR2			0x00034
138 #define DEFR2_CODE		(0x7775 << 16)
139 #define DEFR2_DEFE2G		(1 << 0)
140 
141 #define DEFR3			0x00038
142 #define DEFR3_CODE		(0x7776 << 16)
143 #define DEFR3_EVDA		(1 << 14)
144 #define DEFR3_EVDM_1		(1 << 12)
145 #define DEFR3_EVDM_2		(2 << 12)
146 #define DEFR3_EVDM_3		(3 << 12)
147 #define DEFR3_VMSM2_EMA		(1 << 6)
148 #define DEFR3_VMSM1_ENA		(1 << 4)
149 #define DEFR3_DEFE3		(1 << 0)
150 
151 #define DEFR4			0x0003c
152 #define DEFR4_CODE		(0x7777 << 16)
153 #define DEFR4_LRUO		(1 << 5)
154 #define DEFR4_SPCE		(1 << 4)
155 
156 #define DVCSR			0x000d0
157 #define DVCSR_VCnFB2_DSA0(n)	(0 << ((n)*2+16))
158 #define DVCSR_VCnFB2_DSA1(n)	(1 << ((n)*2+16))
159 #define DVCSR_VCnFB2_DSA2(n)	(2 << ((n)*2+16))
160 #define DVCSR_VCnFB2_INIT(n)	(3 << ((n)*2+16))
161 #define DVCSR_VCnFB2_MASK(n)	(3 << ((n)*2+16))
162 #define DVCSR_VCnFB_DSA0(n)	(0 << ((n)*2))
163 #define DVCSR_VCnFB_DSA1(n)	(1 << ((n)*2))
164 #define DVCSR_VCnFB_DSA2(n)	(2 << ((n)*2))
165 #define DVCSR_VCnFB_INIT(n)	(3 << ((n)*2))
166 #define DVCSR_VCnFB_MASK(n)	(3 << ((n)*2))
167 
168 #define DEFR5			0x000e0
169 #define DEFR5_CODE		(0x66 << 24)
170 #define DEFR5_YCRGB2_DIS	(0 << 14)
171 #define DEFR5_YCRGB2_PRI1	(1 << 14)
172 #define DEFR5_YCRGB2_PRI2	(2 << 14)
173 #define DEFR5_YCRGB2_PRI3	(3 << 14)
174 #define DEFR5_YCRGB2_MASK	(3 << 14)
175 #define DEFR5_YCRGB1_DIS	(0 << 12)
176 #define DEFR5_YCRGB1_PRI1	(1 << 12)
177 #define DEFR5_YCRGB1_PRI2	(2 << 12)
178 #define DEFR5_YCRGB1_PRI3	(3 << 12)
179 #define DEFR5_YCRGB1_MASK	(3 << 12)
180 #define DEFR5_DEFE5		(1 << 0)
181 
182 #define DDLTR			0x000e4
183 #define DDLTR_CODE		(0x7766 << 16)
184 #define DDLTR_DLAR2		(1 << 6)
185 #define DDLTR_DLAY2		(1 << 5)
186 #define DDLTR_DLAY1		(1 << 1)
187 
188 #define DEFR6			0x000e8
189 #define DEFR6_CODE		(0x7778 << 16)
190 #define DEFR6_ODPM22_DSMR	(0 << 10)
191 #define DEFR6_ODPM22_DISP	(2 << 10)
192 #define DEFR6_ODPM22_CDE	(3 << 10)
193 #define DEFR6_ODPM22_MASK	(3 << 10)
194 #define DEFR6_ODPM12_DSMR	(0 << 8)
195 #define DEFR6_ODPM12_DISP	(2 << 8)
196 #define DEFR6_ODPM12_CDE	(3 << 8)
197 #define DEFR6_ODPM12_MASK	(3 << 8)
198 #define DEFR6_TCNE1		(1 << 6)
199 #define DEFR6_TCNE0		(1 << 4)
200 #define DEFR6_MLOS1		(1 << 2)
201 #define DEFR6_DEFAULT		(DEFR6_CODE | DEFR6_TCNE1)
202 
203 /* -----------------------------------------------------------------------------
204  * R8A7790-only Control Registers
205  */
206 
207 #define DD1SSR			0x20008
208 #define DD1SSR_TVR		(1 << 15)
209 #define DD1SSR_FRM		(1 << 14)
210 #define DD1SSR_BUF		(1 << 12)
211 #define DD1SSR_VBK		(1 << 11)
212 #define DD1SSR_RINT		(1 << 9)
213 #define DD1SSR_HBK		(1 << 8)
214 #define DD1SSR_ADC(n)		(1 << ((n)-1))
215 
216 #define DD1SRCR			0x2000c
217 #define DD1SRCR_TVR		(1 << 15)
218 #define DD1SRCR_FRM		(1 << 14)
219 #define DD1SRCR_BUF		(1 << 12)
220 #define DD1SRCR_VBK		(1 << 11)
221 #define DD1SRCR_RINT		(1 << 9)
222 #define DD1SRCR_HBK		(1 << 8)
223 #define DD1SRCR_ADC(n)		(1 << ((n)-1))
224 
225 #define DD1IER			0x20010
226 #define DD1IER_TVR		(1 << 15)
227 #define DD1IER_FRM		(1 << 14)
228 #define DD1IER_BUF		(1 << 12)
229 #define DD1IER_VBK		(1 << 11)
230 #define DD1IER_RINT		(1 << 9)
231 #define DD1IER_HBK		(1 << 8)
232 #define DD1IER_ADC(n)		(1 << ((n)-1))
233 
234 #define DEFR8			0x20020
235 #define DEFR8_CODE		(0x7790 << 16)
236 #define DEFR8_VSCS		(1 << 6)
237 #define DEFR8_DRGBS_DU(n)	((n) << 4)
238 #define DEFR8_DRGBS_MASK	(3 << 4)
239 #define DEFR8_DEFE8		(1 << 0)
240 
241 #define DOFLR			0x20024
242 #define DOFLR_CODE		(0x7790 << 16)
243 #define DOFLR_HSYCFL1		(1 << 13)
244 #define DOFLR_VSYCFL1		(1 << 12)
245 #define DOFLR_ODDFL1		(1 << 11)
246 #define DOFLR_DISPFL1		(1 << 10)
247 #define DOFLR_CDEFL1		(1 << 9)
248 #define DOFLR_RGBFL1		(1 << 8)
249 #define DOFLR_HSYCFL0		(1 << 5)
250 #define DOFLR_VSYCFL0		(1 << 4)
251 #define DOFLR_ODDFL0		(1 << 3)
252 #define DOFLR_DISPFL0		(1 << 2)
253 #define DOFLR_CDEFL0		(1 << 1)
254 #define DOFLR_RGBFL0		(1 << 0)
255 
256 #define DIDSR			0x20028
257 #define DIDSR_CODE		(0x7790 << 16)
258 #define DIDSR_LCDS_DCLKIN(n)	(0 << (8 + (n) * 2))
259 #define DIDSR_LCDS_LVDS0(n)	(2 << (8 + (n) * 2))
260 #define DIDSR_LCDS_LVDS1(n)	(3 << (8 + (n) * 2))
261 #define DIDSR_LCDS_MASK(n)	(3 << (8 + (n) * 2))
262 #define DIDSR_PDCS_CLK(n, clk)	(clk << ((n) * 2))
263 #define DIDSR_PDCS_MASK(n)	(3 << ((n) * 2))
264 
265 #define DEFR10			0x20038
266 #define DEFR10_CODE		(0x7795 << 16)
267 #define DEFR10_VSPF1_RGB	(0 << 14)
268 #define DEFR10_VSPF1_YC		(1 << 14)
269 #define DEFR10_DOCF1_RGB	(0 << 12)
270 #define DEFR10_DOCF1_YC		(1 << 12)
271 #define DEFR10_YCDF0_YCBCR444	(0 << 11)
272 #define DEFR10_YCDF0_YCBCR422	(1 << 11)
273 #define DEFR10_VSPF0_RGB	(0 << 10)
274 #define DEFR10_VSPF0_YC		(1 << 10)
275 #define DEFR10_DOCF0_RGB	(0 << 8)
276 #define DEFR10_DOCF0_YC		(1 << 8)
277 #define DEFR10_TSEL_H3_TCON1	(0 << 1) /* DEFR102 register only (DU2/DU3) */
278 #define DEFR10_DEFE10		(1 << 0)
279 
280 /* -----------------------------------------------------------------------------
281  * Display Timing Generation Registers
282  */
283 
284 #define HDSR			0x00040
285 #define HDER			0x00044
286 #define VDSR			0x00048
287 #define VDER			0x0004c
288 #define HCR			0x00050
289 #define HSWR			0x00054
290 #define VCR			0x00058
291 #define VSPR			0x0005c
292 #define EQWR			0x00060
293 #define SPWR			0x00064
294 #define CLAMPSR			0x00070
295 #define CLAMPWR			0x00074
296 #define DESR			0x00078
297 #define DEWR			0x0007c
298 
299 /* -----------------------------------------------------------------------------
300  * Display Attribute Registers
301  */
302 
303 #define CP1TR			0x00080
304 #define CP2TR			0x00084
305 #define CP3TR			0x00088
306 #define CP4TR			0x0008c
307 
308 #define DOOR			0x00090
309 #define DOOR_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))
310 #define CDER			0x00094
311 #define CDER_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))
312 #define BPOR			0x00098
313 #define BPOR_RGB(r, g, b)	(((r) << 18) | ((g) << 10) | ((b) << 2))
314 
315 #define RINTOFSR		0x0009c
316 
317 #define DSHPR			0x000c8
318 #define DSHPR_CODE		(0x7776 << 16)
319 #define DSHPR_PRIH		(0xa << 4)
320 #define DSHPR_PRIL_BPP16	(0x8 << 0)
321 #define DSHPR_PRIL_BPP32	(0x9 << 0)
322 
323 /* -----------------------------------------------------------------------------
324  * Display Plane Registers
325  */
326 
327 #define PLANE_OFF		0x00100
328 
329 #define PnMR			0x00100 /* plane 1 */
330 #define PnMR_VISL_VIN0		(0 << 26)	/* use Video Input 0 */
331 #define PnMR_VISL_VIN1		(1 << 26)	/* use Video Input 1 */
332 #define PnMR_VISL_VIN2		(2 << 26)	/* use Video Input 2 */
333 #define PnMR_VISL_VIN3		(3 << 26)	/* use Video Input 3 */
334 #define PnMR_YCDF_YUYV		(1 << 20)	/* YUYV format */
335 #define PnMR_TC_R		(0 << 17)	/* Tranparent color is PnTC1R */
336 #define PnMR_TC_CP		(1 << 17)	/* Tranparent color is color palette */
337 #define PnMR_WAE		(1 << 16)	/* Wrap around Enable */
338 #define PnMR_SPIM_TP		(0 << 12)	/* Transparent Color */
339 #define PnMR_SPIM_ALP		(1 << 12)	/* Alpha Blending */
340 #define PnMR_SPIM_EOR		(2 << 12)	/* EOR */
341 #define PnMR_SPIM_TP_OFF	(1 << 14)	/* No Transparent Color */
342 #define PnMR_CPSL_CP1		(0 << 8)	/* Color Palette selected 1 */
343 #define PnMR_CPSL_CP2		(1 << 8)	/* Color Palette selected 2 */
344 #define PnMR_CPSL_CP3		(2 << 8)	/* Color Palette selected 3 */
345 #define PnMR_CPSL_CP4		(3 << 8)	/* Color Palette selected 4 */
346 #define PnMR_DC			(1 << 7)	/* Display Area Change */
347 #define PnMR_BM_MD		(0 << 4)	/* Manual Display Change Mode */
348 #define PnMR_BM_AR		(1 << 4)	/* Auto Rendering Mode */
349 #define PnMR_BM_AD		(2 << 4)	/* Auto Display Change Mode */
350 #define PnMR_BM_VC		(3 << 4)	/* Video Capture Mode */
351 #define PnMR_DDDF_8BPP		(0 << 0)	/* 8bit */
352 #define PnMR_DDDF_16BPP		(1 << 0)	/* 16bit or 32bit */
353 #define PnMR_DDDF_ARGB		(2 << 0)	/* ARGB */
354 #define PnMR_DDDF_YC		(3 << 0)	/* YC */
355 #define PnMR_DDDF_MASK		(3 << 0)
356 
357 #define PnMWR			0x00104
358 
359 #define PnALPHAR		0x00108
360 #define PnALPHAR_ABIT_1		(0 << 12)
361 #define PnALPHAR_ABIT_0		(1 << 12)
362 #define PnALPHAR_ABIT_X		(2 << 12)
363 
364 #define PnDSXR			0x00110
365 #define PnDSYR			0x00114
366 #define PnDPXR			0x00118
367 #define PnDPYR			0x0011c
368 
369 #define PnDSA0R			0x00120
370 #define PnDSA1R			0x00124
371 #define PnDSA2R			0x00128
372 #define PnDSA_MASK		0xfffffff0
373 
374 #define PnSPXR			0x00130
375 #define PnSPYR			0x00134
376 #define PnWASPR			0x00138
377 #define PnWAMWR			0x0013c
378 
379 #define PnBTR			0x00140
380 
381 #define PnTC1R			0x00144
382 #define PnTC2R			0x00148
383 #define PnTC3R			0x0014c
384 #define PnTC3R_CODE		(0x66 << 24)
385 
386 #define PnMLR			0x00150
387 
388 #define PnSWAPR			0x00180
389 #define PnSWAPR_DIGN		(1 << 4)
390 #define PnSWAPR_SPQW		(1 << 3)
391 #define PnSWAPR_SPLW		(1 << 2)
392 #define PnSWAPR_SPWD		(1 << 1)
393 #define PnSWAPR_SPBY		(1 << 0)
394 
395 #define PnDDCR			0x00184
396 #define PnDDCR_CODE		(0x7775 << 16)
397 #define PnDDCR_LRGB1		(1 << 11)
398 #define PnDDCR_LRGB0		(1 << 10)
399 
400 #define PnDDCR2			0x00188
401 #define PnDDCR2_CODE		(0x7776 << 16)
402 #define PnDDCR2_NV21		(1 << 5)
403 #define PnDDCR2_Y420		(1 << 4)
404 #define PnDDCR2_DIVU		(1 << 1)
405 #define PnDDCR2_DIVY		(1 << 0)
406 
407 #define PnDDCR4			0x00190
408 #define PnDDCR4_CODE		(0x7766 << 16)
409 #define PnDDCR4_VSPS		(1 << 13)
410 #define PnDDCR4_SDFS_RGB	(0 << 4)
411 #define PnDDCR4_SDFS_YC		(5 << 4)
412 #define PnDDCR4_SDFS_MASK	(7 << 4)
413 #define PnDDCR4_EDF_NONE	(0 << 0)
414 #define PnDDCR4_EDF_ARGB8888	(1 << 0)
415 #define PnDDCR4_EDF_RGB888	(2 << 0)
416 #define PnDDCR4_EDF_RGB666	(3 << 0)
417 #define PnDDCR4_EDF_MASK	(7 << 0)
418 
419 #define APnMR			0x0a100
420 #define APnMR_WAE		(1 << 16)	/* Wrap around Enable */
421 #define APnMR_DC		(1 << 7)	/* Display Area Change */
422 #define APnMR_BM_MD		(0 << 4)	/* Manual Display Change Mode */
423 #define APnMR_BM_AD		(2 << 4)	/* Auto Display Change Mode */
424 
425 #define APnMWR			0x0a104
426 
427 #define APnDSXR			0x0a110
428 #define APnDSYR			0x0a114
429 #define APnDPXR			0x0a118
430 #define APnDPYR			0x0a11c
431 
432 #define APnDSA0R		0x0a120
433 #define APnDSA1R		0x0a124
434 #define APnDSA2R		0x0a128
435 
436 #define APnSPXR			0x0a130
437 #define APnSPYR			0x0a134
438 #define APnWASPR		0x0a138
439 #define APnWAMWR		0x0a13c
440 
441 #define APnBTR			0x0a140
442 
443 #define APnMLR			0x0a150
444 #define APnSWAPR		0x0a180
445 
446 /* -----------------------------------------------------------------------------
447  * Display Capture Registers
448  */
449 
450 #define DCMR			0x0c100
451 #define DCMWR			0x0c104
452 #define DCSAR			0x0c120
453 #define DCMLR			0x0c150
454 
455 /* -----------------------------------------------------------------------------
456  * Color Palette Registers
457  */
458 
459 #define CP1_000R		0x01000
460 #define CP1_255R		0x013fc
461 #define CP2_000R		0x02000
462 #define CP2_255R		0x023fc
463 #define CP3_000R		0x03000
464 #define CP3_255R		0x033fc
465 #define CP4_000R		0x04000
466 #define CP4_255R		0x043fc
467 
468 /* -----------------------------------------------------------------------------
469  * External Synchronization Control Registers
470  */
471 
472 #define ESCR			0x10000
473 #define ESCR2			0x31000
474 #define ESCR_DCLKOINV		(1 << 25)
475 #define ESCR_DCLKSEL_DCLKIN	(0 << 20)
476 #define ESCR_DCLKSEL_CLKS	(1 << 20)
477 #define ESCR_DCLKSEL_MASK	(1 << 20)
478 #define ESCR_DCLKDIS		(1 << 16)
479 #define ESCR_SYNCSEL_OFF	(0 << 8)
480 #define ESCR_SYNCSEL_EXVSYNC	(2 << 8)
481 #define ESCR_SYNCSEL_EXHSYNC	(3 << 8)
482 #define ESCR_FRQSEL_MASK	(0x3f << 0)
483 
484 #define OTAR			0x10004
485 #define OTAR2			0x31004
486 
487 /* -----------------------------------------------------------------------------
488  * Dual Display Output Control Registers
489  */
490 
491 #define DORCR			0x11000
492 #define DORCR_PG2T		(1 << 30)
493 #define DORCR_DK2S		(1 << 28)
494 #define DORCR_PG2D_DS1		(0 << 24)
495 #define DORCR_PG2D_DS2		(1 << 24)
496 #define DORCR_PG2D_FIX0		(2 << 24)
497 #define DORCR_PG2D_DOOR		(3 << 24)
498 #define DORCR_PG2D_MASK		(3 << 24)
499 #define DORCR_DR1D		(1 << 21)
500 #define DORCR_PG1D_DS1		(0 << 16)
501 #define DORCR_PG1D_DS2		(1 << 16)
502 #define DORCR_PG1D_FIX0		(2 << 16)
503 #define DORCR_PG1D_DOOR		(3 << 16)
504 #define DORCR_PG1D_MASK		(3 << 16)
505 #define DORCR_RGPV		(1 << 4)
506 #define DORCR_DPRS		(1 << 0)
507 
508 #define DPTSR			0x11004
509 #define DPTSR_PnDK(n)		(1 << ((n) + 16))
510 #define DPTSR_PnTS(n)		(1 << (n))
511 
512 #define DAPTSR			0x11008
513 #define DAPTSR_APnDK(n)		(1 << ((n) + 16))
514 #define DAPTSR_APnTS(n)		(1 << (n))
515 
516 #define DS1PR			0x11020
517 #define DS2PR			0x11024
518 
519 /* -----------------------------------------------------------------------------
520  * YC-RGB Conversion Coefficient Registers
521  */
522 
523 #define YNCR			0x11080
524 #define YNOR			0x11084
525 #define CRNOR			0x11088
526 #define CBNOR			0x1108c
527 #define RCRCR			0x11090
528 #define GCRCR			0x11094
529 #define GCBCR			0x11098
530 #define BCBCR			0x1109c
531 
532 #endif /* __RCAR_DU_REGS_H__ */
533