1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __QEDR_H__
33 #define __QEDR_H__
34
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <linux/qed/qed_if.h>
38 #include <linux/qed/qed_chain.h>
39 #include <linux/qed/qed_roce_if.h>
40 #include <linux/qed/qede_roce.h>
41 #include "qedr_hsi.h"
42
43 #define QEDR_MODULE_VERSION "8.10.10.0"
44 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
45 #define DP_NAME(dev) ((dev)->ibdev.name)
46
47 #define DP_DEBUG(dev, module, fmt, ...) \
48 pr_debug("(%s) " module ": " fmt, \
49 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
50
51 #define QEDR_MSG_INIT "INIT"
52 #define QEDR_MSG_MISC "MISC"
53 #define QEDR_MSG_CQ " CQ"
54 #define QEDR_MSG_MR " MR"
55 #define QEDR_MSG_RQ " RQ"
56 #define QEDR_MSG_SQ " SQ"
57 #define QEDR_MSG_QP " QP"
58 #define QEDR_MSG_GSI " GSI"
59
60 #define QEDR_CQ_MAGIC_NUMBER (0x11223344)
61
62 struct qedr_dev;
63
64 struct qedr_cnq {
65 struct qedr_dev *dev;
66 struct qed_chain pbl;
67 struct qed_sb_info *sb;
68 char name[32];
69 u64 n_comp;
70 __le16 *hw_cons_ptr;
71 u8 index;
72 };
73
74 #define QEDR_MAX_SGID 128
75
76 struct qedr_device_attr {
77 u32 vendor_id;
78 u32 vendor_part_id;
79 u32 hw_ver;
80 u64 fw_ver;
81 u64 node_guid;
82 u64 sys_image_guid;
83 u8 max_cnq;
84 u8 max_sge;
85 u16 max_inline;
86 u32 max_sqe;
87 u32 max_rqe;
88 u8 max_qp_resp_rd_atomic_resc;
89 u8 max_qp_req_rd_atomic_resc;
90 u64 max_dev_resp_rd_atomic_resc;
91 u32 max_cq;
92 u32 max_qp;
93 u32 max_mr;
94 u64 max_mr_size;
95 u32 max_cqe;
96 u32 max_mw;
97 u32 max_fmr;
98 u32 max_mr_mw_fmr_pbl;
99 u64 max_mr_mw_fmr_size;
100 u32 max_pd;
101 u32 max_ah;
102 u8 max_pkey;
103 u32 max_srq;
104 u32 max_srq_wr;
105 u8 max_srq_sge;
106 u8 max_stats_queues;
107 u32 dev_caps;
108
109 u64 page_size_caps;
110 u8 dev_ack_delay;
111 u32 reserved_lkey;
112 u32 bad_pkey_counter;
113 struct qed_rdma_events events;
114 };
115
116 #define QEDR_ENET_STATE_BIT (0)
117
118 struct qedr_dev {
119 struct ib_device ibdev;
120 struct qed_dev *cdev;
121 struct pci_dev *pdev;
122 struct net_device *ndev;
123
124 enum ib_atomic_cap atomic_cap;
125
126 void *rdma_ctx;
127 struct qedr_device_attr attr;
128
129 const struct qed_rdma_ops *ops;
130 struct qed_int_info int_info;
131
132 struct qed_sb_info *sb_array;
133 struct qedr_cnq *cnq_array;
134 int num_cnq;
135 int sb_start;
136
137 void __iomem *db_addr;
138 u64 db_phys_addr;
139 u32 db_size;
140 u16 dpi;
141
142 union ib_gid *sgid_tbl;
143
144 /* Lock for sgid table */
145 spinlock_t sgid_lock;
146
147 u64 guid;
148
149 u32 dp_module;
150 u8 dp_level;
151 u8 num_hwfns;
152 uint wq_multiplier;
153 u8 gsi_ll2_mac_address[ETH_ALEN];
154 int gsi_qp_created;
155 struct qedr_cq *gsi_sqcq;
156 struct qedr_cq *gsi_rqcq;
157 struct qedr_qp *gsi_qp;
158
159 unsigned long enet_state;
160 };
161
162 #define QEDR_MAX_SQ_PBL (0x8000)
163 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
164 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
165 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
166 QEDR_SQE_ELEMENT_SIZE)
167 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
168 QEDR_SQE_ELEMENT_SIZE)
169 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
170 (RDMA_RING_PAGE_SIZE) / \
171 (QEDR_SQE_ELEMENT_SIZE) /\
172 (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
173 /* RQ */
174 #define QEDR_MAX_RQ_PBL (0x2000)
175 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
176 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
177 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
178 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
179 QEDR_RQE_ELEMENT_SIZE)
180 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
181 (RDMA_RING_PAGE_SIZE) / \
182 (QEDR_RQE_ELEMENT_SIZE) /\
183 (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
184
185 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
186 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
187 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
188 sizeof(u64)) - 1)
189 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
190 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
191
192 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
193
194 #define QEDR_MAX_PORT (1)
195 #define QEDR_PORT (1)
196
197 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
198
199 #define QEDR_ROCE_PKEY_MAX 1
200 #define QEDR_ROCE_PKEY_TABLE_LEN 1
201 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
202
203 struct qedr_pbl {
204 struct list_head list_entry;
205 void *va;
206 dma_addr_t pa;
207 };
208
209 struct qedr_ucontext {
210 struct ib_ucontext ibucontext;
211 struct qedr_dev *dev;
212 struct qedr_pd *pd;
213 u64 dpi_addr;
214 u64 dpi_phys_addr;
215 u32 dpi_size;
216 u16 dpi;
217
218 struct list_head mm_head;
219
220 /* Lock to protect mm list */
221 struct mutex mm_list_lock;
222 };
223
224 union db_prod64 {
225 struct rdma_pwm_val32_data data;
226 u64 raw;
227 };
228
229 enum qedr_cq_type {
230 QEDR_CQ_TYPE_GSI,
231 QEDR_CQ_TYPE_KERNEL,
232 QEDR_CQ_TYPE_USER,
233 };
234
235 struct qedr_pbl_info {
236 u32 num_pbls;
237 u32 num_pbes;
238 u32 pbl_size;
239 u32 pbe_size;
240 bool two_layered;
241 };
242
243 struct qedr_userq {
244 struct ib_umem *umem;
245 struct qedr_pbl_info pbl_info;
246 struct qedr_pbl *pbl_tbl;
247 u64 buf_addr;
248 size_t buf_len;
249 };
250
251 struct qedr_cq {
252 struct ib_cq ibcq;
253
254 enum qedr_cq_type cq_type;
255 u32 sig;
256
257 u16 icid;
258
259 /* Lock to protect completion handler */
260 spinlock_t comp_handler_lock;
261
262 /* Lock to protect multiplem CQ's */
263 spinlock_t cq_lock;
264 u8 arm_flags;
265 struct qed_chain pbl;
266
267 void __iomem *db_addr;
268 union db_prod64 db;
269
270 u8 pbl_toggle;
271 union rdma_cqe *latest_cqe;
272 union rdma_cqe *toggle_cqe;
273
274 u32 cq_cons;
275
276 struct qedr_userq q;
277 };
278
279 struct qedr_pd {
280 struct ib_pd ibpd;
281 u32 pd_id;
282 struct qedr_ucontext *uctx;
283 };
284
285 struct qedr_mm {
286 struct {
287 u64 phy_addr;
288 unsigned long len;
289 } key;
290 struct list_head entry;
291 };
292
293 union db_prod32 {
294 struct rdma_pwm_val16_data data;
295 u32 raw;
296 };
297
298 struct qedr_qp_hwq_info {
299 /* WQE Elements */
300 struct qed_chain pbl;
301 u64 p_phys_addr_tbl;
302 u32 max_sges;
303
304 /* WQE */
305 u16 prod;
306 u16 cons;
307 u16 wqe_cons;
308 u16 gsi_cons;
309 u16 max_wr;
310
311 /* DB */
312 void __iomem *db;
313 union db_prod32 db_data;
314 };
315
316 #define QEDR_INC_SW_IDX(p_info, index) \
317 do { \
318 p_info->index = (p_info->index + 1) & \
319 qed_chain_get_capacity(p_info->pbl) \
320 } while (0)
321
322 enum qedr_qp_err_bitmap {
323 QEDR_QP_ERR_SQ_FULL = 1,
324 QEDR_QP_ERR_RQ_FULL = 2,
325 QEDR_QP_ERR_BAD_SR = 4,
326 QEDR_QP_ERR_BAD_RR = 8,
327 QEDR_QP_ERR_SQ_PBL_FULL = 16,
328 QEDR_QP_ERR_RQ_PBL_FULL = 32,
329 };
330
331 struct qedr_qp {
332 struct ib_qp ibqp; /* must be first */
333 struct qedr_dev *dev;
334
335 struct qedr_qp_hwq_info sq;
336 struct qedr_qp_hwq_info rq;
337
338 u32 max_inline_data;
339
340 /* Lock for QP's */
341 spinlock_t q_lock;
342 struct qedr_cq *sq_cq;
343 struct qedr_cq *rq_cq;
344 struct qedr_srq *srq;
345 enum qed_roce_qp_state state;
346 u32 id;
347 struct qedr_pd *pd;
348 enum ib_qp_type qp_type;
349 struct qed_rdma_qp *qed_qp;
350 u32 qp_id;
351 u16 icid;
352 u16 mtu;
353 int sgid_idx;
354 u32 rq_psn;
355 u32 sq_psn;
356 u32 qkey;
357 u32 dest_qp_num;
358
359 /* Relevant to qps created from kernel space only (ULPs) */
360 u8 prev_wqe_size;
361 u16 wqe_cons;
362 u32 err_bitmap;
363 bool signaled;
364
365 /* SQ shadow */
366 struct {
367 u64 wr_id;
368 enum ib_wc_opcode opcode;
369 u32 bytes_len;
370 u8 wqe_size;
371 bool signaled;
372 dma_addr_t icrc_mapping;
373 u32 *icrc;
374 struct qedr_mr *mr;
375 } *wqe_wr_id;
376
377 /* RQ shadow */
378 struct {
379 u64 wr_id;
380 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
381 u8 wqe_size;
382
383 u8 smac[ETH_ALEN];
384 u16 vlan_id;
385 int rc;
386 } *rqe_wr_id;
387
388 /* Relevant to qps created from user space only (applications) */
389 struct qedr_userq usq;
390 struct qedr_userq urq;
391 };
392
393 struct qedr_ah {
394 struct ib_ah ibah;
395 struct ib_ah_attr attr;
396 };
397
398 enum qedr_mr_type {
399 QEDR_MR_USER,
400 QEDR_MR_KERNEL,
401 QEDR_MR_DMA,
402 QEDR_MR_FRMR,
403 };
404
405 struct mr_info {
406 struct qedr_pbl *pbl_table;
407 struct qedr_pbl_info pbl_info;
408 struct list_head free_pbl_list;
409 struct list_head inuse_pbl_list;
410 u32 completed;
411 u32 completed_handled;
412 };
413
414 struct qedr_mr {
415 struct ib_mr ibmr;
416 struct ib_umem *umem;
417
418 struct qed_rdma_register_tid_in_params hw_mr;
419 enum qedr_mr_type type;
420
421 struct qedr_dev *dev;
422 struct mr_info info;
423
424 u64 *pages;
425 u32 npages;
426 };
427
428 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
429
430 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
431 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
432 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
433 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
434 #define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA)
435
qedr_inc_sw_cons(struct qedr_qp_hwq_info * info)436 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
437 {
438 info->cons = (info->cons + 1) % info->max_wr;
439 info->wqe_cons++;
440 }
441
qedr_inc_sw_prod(struct qedr_qp_hwq_info * info)442 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
443 {
444 info->prod = (info->prod + 1) % info->max_wr;
445 }
446
qedr_get_dmac(struct qedr_dev * dev,struct ib_ah_attr * ah_attr,u8 * mac_addr)447 static inline int qedr_get_dmac(struct qedr_dev *dev,
448 struct ib_ah_attr *ah_attr, u8 *mac_addr)
449 {
450 union ib_gid zero_sgid = { { 0 } };
451 struct in6_addr in6;
452
453 if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
454 DP_ERR(dev, "Local port GID not supported\n");
455 eth_zero_addr(mac_addr);
456 return -EINVAL;
457 }
458
459 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
460 ether_addr_copy(mac_addr, ah_attr->dmac);
461
462 return 0;
463 }
464
465 static inline
get_qedr_ucontext(struct ib_ucontext * ibucontext)466 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
467 {
468 return container_of(ibucontext, struct qedr_ucontext, ibucontext);
469 }
470
get_qedr_dev(struct ib_device * ibdev)471 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
472 {
473 return container_of(ibdev, struct qedr_dev, ibdev);
474 }
475
get_qedr_pd(struct ib_pd * ibpd)476 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
477 {
478 return container_of(ibpd, struct qedr_pd, ibpd);
479 }
480
get_qedr_cq(struct ib_cq * ibcq)481 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
482 {
483 return container_of(ibcq, struct qedr_cq, ibcq);
484 }
485
get_qedr_qp(struct ib_qp * ibqp)486 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
487 {
488 return container_of(ibqp, struct qedr_qp, ibqp);
489 }
490
get_qedr_ah(struct ib_ah * ibah)491 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
492 {
493 return container_of(ibah, struct qedr_ah, ibah);
494 }
495
get_qedr_mr(struct ib_mr * ibmr)496 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
497 {
498 return container_of(ibmr, struct qedr_mr, ibmr);
499 }
500 #endif
501