1 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
2 #define _ASM_POWERPC_PGTABLE_RADIX_H
3
4 #ifndef __ASSEMBLY__
5 #include <asm/cmpxchg.h>
6 #endif
7
8 #ifdef CONFIG_PPC_64K_PAGES
9 #include <asm/book3s/64/radix-64k.h>
10 #else
11 #include <asm/book3s/64/radix-4k.h>
12 #endif
13
14 #ifndef __ASSEMBLY__
15 #include <asm/book3s/64/tlbflush-radix.h>
16 #include <asm/cpu_has_feature.h>
17 #endif
18
19 /* An empty PTE can still have a R or C writeback */
20 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
21
22 /* Bits to set in a RPMD/RPUD/RPGD */
23 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
24 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
25 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
26
27 /* Don't have anything in the reserved bits and leaf bits */
28 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
29 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
30 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
31
32 /*
33 * Size of EA range mapped by our pagetables.
34 */
35 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
36 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
37 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
38
39 /*
40 * We support 52 bit address space, Use top bit for kernel
41 * virtual mapping. Also make sure kernel fit in the top
42 * quadrant.
43 *
44 * +------------------+
45 * +------------------+ Kernel virtual map (0xc008000000000000)
46 * | |
47 * | |
48 * | |
49 * 0b11......+------------------+ Kernel linear map (0xc....)
50 * | |
51 * | 2 quadrant |
52 * | |
53 * 0b10......+------------------+
54 * | |
55 * | 1 quadrant |
56 * | |
57 * 0b01......+------------------+
58 * | |
59 * | 0 quadrant |
60 * | |
61 * 0b00......+------------------+
62 *
63 *
64 * 3rd quadrant expanded:
65 * +------------------------------+
66 * | |
67 * | |
68 * | |
69 * +------------------------------+ Kernel IO map end (0xc010000000000000)
70 * | |
71 * | |
72 * | 1/2 of virtual map |
73 * | |
74 * | |
75 * +------------------------------+ Kernel IO map start
76 * | |
77 * | 1/4 of virtual map |
78 * | |
79 * +------------------------------+ Kernel vmemap start
80 * | |
81 * | 1/4 of virtual map |
82 * | |
83 * +------------------------------+ Kernel virt start (0xc008000000000000)
84 * | |
85 * | |
86 * | |
87 * +------------------------------+ Kernel linear (0xc.....)
88 */
89
90 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
91 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000)
92
93 /*
94 * The vmalloc space starts at the beginning of that region, and
95 * occupies a quarter of it on radix config.
96 * (we keep a quarter for the virtual memmap)
97 */
98 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
99 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2)
100 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
101 /*
102 * Defines the address of the vmemap area, in its own region on
103 * hash table CPUs.
104 */
105 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END)
106
107 #ifndef __ASSEMBLY__
108 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
109 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
110 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
111 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
112
__radix_pte_update(pte_t * ptep,unsigned long clr,unsigned long set)113 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
114 unsigned long set)
115 {
116 pte_t pte;
117 unsigned long old_pte, new_pte;
118
119 do {
120 pte = READ_ONCE(*ptep);
121 old_pte = pte_val(pte);
122 new_pte = (old_pte | set) & ~clr;
123
124 } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
125
126 return old_pte;
127 }
128
129
radix__pte_update(struct mm_struct * mm,unsigned long addr,pte_t * ptep,unsigned long clr,unsigned long set,int huge)130 static inline unsigned long radix__pte_update(struct mm_struct *mm,
131 unsigned long addr,
132 pte_t *ptep, unsigned long clr,
133 unsigned long set,
134 int huge)
135 {
136 unsigned long old_pte;
137
138 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
139
140 unsigned long new_pte;
141
142 old_pte = __radix_pte_update(ptep, ~0, 0);
143 asm volatile("ptesync" : : : "memory");
144 /*
145 * new value of pte
146 */
147 new_pte = (old_pte | set) & ~clr;
148
149 /*
150 * For now let's do heavy pid flush
151 * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
152 */
153 radix__flush_tlb_mm(mm);
154
155 __radix_pte_update(ptep, 0, new_pte);
156 } else
157 old_pte = __radix_pte_update(ptep, clr, set);
158 asm volatile("ptesync" : : : "memory");
159 if (!huge)
160 assert_pte_locked(mm, addr);
161
162 return old_pte;
163 }
164
165 /*
166 * Set the dirty and/or accessed bits atomically in a linux PTE, this
167 * function doesn't need to invalidate tlb.
168 */
radix__ptep_set_access_flags(struct mm_struct * mm,pte_t * ptep,pte_t entry)169 static inline void radix__ptep_set_access_flags(struct mm_struct *mm,
170 pte_t *ptep, pte_t entry)
171 {
172
173 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
174 _PAGE_RW | _PAGE_EXEC);
175
176 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
177
178 unsigned long old_pte, new_pte;
179
180 old_pte = __radix_pte_update(ptep, ~0, 0);
181 asm volatile("ptesync" : : : "memory");
182 /*
183 * new value of pte
184 */
185 new_pte = old_pte | set;
186
187 /*
188 * For now let's do heavy pid flush
189 * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize);
190 */
191 radix__flush_tlb_mm(mm);
192
193 __radix_pte_update(ptep, 0, new_pte);
194 } else
195 __radix_pte_update(ptep, 0, set);
196 asm volatile("ptesync" : : : "memory");
197 }
198
radix__pte_same(pte_t pte_a,pte_t pte_b)199 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
200 {
201 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
202 }
203
radix__pte_none(pte_t pte)204 static inline int radix__pte_none(pte_t pte)
205 {
206 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
207 }
208
radix__set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte,int percpu)209 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
210 pte_t *ptep, pte_t pte, int percpu)
211 {
212 *ptep = pte;
213 asm volatile("ptesync" : : : "memory");
214 }
215
radix__pmd_bad(pmd_t pmd)216 static inline int radix__pmd_bad(pmd_t pmd)
217 {
218 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
219 }
220
radix__pmd_same(pmd_t pmd_a,pmd_t pmd_b)221 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
222 {
223 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
224 }
225
radix__pud_bad(pud_t pud)226 static inline int radix__pud_bad(pud_t pud)
227 {
228 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
229 }
230
231
radix__pgd_bad(pgd_t pgd)232 static inline int radix__pgd_bad(pgd_t pgd)
233 {
234 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
235 }
236
237 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
238
radix__pmd_trans_huge(pmd_t pmd)239 static inline int radix__pmd_trans_huge(pmd_t pmd)
240 {
241 return !!(pmd_val(pmd) & _PAGE_PTE);
242 }
243
radix__pmd_mkhuge(pmd_t pmd)244 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
245 {
246 return __pmd(pmd_val(pmd) | _PAGE_PTE);
247 }
radix__pmdp_huge_split_prepare(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)248 static inline void radix__pmdp_huge_split_prepare(struct vm_area_struct *vma,
249 unsigned long address, pmd_t *pmdp)
250 {
251 /* Nothing to do for radix. */
252 return;
253 }
254
255 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
256 pmd_t *pmdp, unsigned long clr,
257 unsigned long set);
258 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
259 unsigned long address, pmd_t *pmdp);
260 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
261 pgtable_t pgtable);
262 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
263 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
264 unsigned long addr, pmd_t *pmdp);
265 extern int radix__has_transparent_hugepage(void);
266 #endif
267
268 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
269 unsigned long page_size,
270 unsigned long phys);
271 extern void radix__vmemmap_remove_mapping(unsigned long start,
272 unsigned long page_size);
273
274 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
275 pgprot_t flags, unsigned int psz);
276
radix__get_tree_size(void)277 static inline unsigned long radix__get_tree_size(void)
278 {
279 unsigned long rts_field;
280 /*
281 * We support 52 bits, hence:
282 * DD1 52-28 = 24, 0b11000
283 * Others 52-31 = 21, 0b10101
284 * RTS encoding details
285 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
286 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
287 */
288 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
289 rts_field = (0x3UL << 61);
290 else {
291 rts_field = (0x5UL << 5); /* 6 - 8 bits */
292 rts_field |= (0x2UL << 61);
293 }
294 return rts_field;
295 }
296 #endif /* __ASSEMBLY__ */
297 #endif
298