1 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 ******************************************************************************/ 16 17 #ifndef __HAL8188EPWRSEQ_H__ 18 #define __HAL8188EPWRSEQ_H__ 19 20 #include "pwrseqcmd.h" 21 22 /* 23 Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd 24 There are 6 HW Power States: 25 0: POFF--Power Off 26 1: PDN--Power Down 27 2: CARDEMU--Card Emulation 28 3: ACT--Active Mode 29 4: LPS--Low Power State 30 5: SUS--Suspend 31 32 The transision from different states are defined below 33 TRANS_CARDEMU_TO_ACT 34 TRANS_ACT_TO_CARDEMU 35 TRANS_CARDEMU_TO_SUS 36 TRANS_SUS_TO_CARDEMU 37 TRANS_CARDEMU_TO_PDN 38 TRANS_ACT_TO_LPS 39 TRANS_LPS_TO_ACT 40 41 TRANS_END 42 43 PWR SEQ Version: rtl8188E_PwrSeq_V09.h 44 */ 45 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 46 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 47 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 48 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 49 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 50 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 51 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 52 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 53 #define RTL8188E_TRANS_END_STEPS 1 54 55 56 #define RTL8188E_TRANS_CARDEMU_TO_ACT \ 57 /* format 58 * { offset, cut_msk, cmd, msk, value 59 * }, 60 * comment here 61 */ \ 62 {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 63 /* wait till 0x04[17] = 1 power ready*/ \ 64 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ 65 /* 0x02[1:0] = 0 reset BB*/ \ 66 {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 67 /*0x24[23] = 2b'01 schmit trigger */ \ 68 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ 69 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ 70 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ 71 /*0x04[12:11] = 2b'00 disable WL suspend*/ \ 72 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 73 /*0x04[8] = 1 polling until return 0*/ \ 74 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \ 75 /*wait till 0x04[8] = 0*/ \ 76 {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 77 /*LDO normal mode*/ 78 79 #define RTL8188E_TRANS_ACT_TO_CARDEMU \ 80 /* format 81 * { offset, cut_msk, cmd, msk, value 82 * }, 83 * comments here 84 */ \ 85 {0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ 86 /*0x1F[7:0] = 0 turn off RF*/ \ 87 {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 88 /*LDO Sleep mode*/ \ 89 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 90 /*0x04[9] = 1 turn off MAC by HW state machine*/ \ 91 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \ 92 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ 93 94 #define RTL8188E_TRANS_CARDEMU_TO_SUS \ 95 /* format 96 * { offset, cut_msk, cmd, msk, 97 * value }, 98 * comments here 99 */ \ 100 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 101 /* 0x04[12:11] = 2b'01enable WL suspend */ \ 102 {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \ 103 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ 104 {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 105 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ 106 {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 107 /*Set USB suspend enable local register 0xfe10[4]=1 */ 108 109 #define RTL8188E_TRANS_SUS_TO_CARDEMU \ 110 /* format 111 * { offset, cut_msk, cmd, msk, 112 * value }, 113 * comments here 114 */ \ 115 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ 116 /*0x04[12:11] = 2b'01enable WL suspend*/ 117 118 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ 119 /* format 120 * { offset, cut_msk, cmd, msk, 121 * value }, 122 * comments here 123 */ \ 124 {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 125 /*0x24[23] = 2b'01 schmit trigger */ \ 126 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 127 /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 128 {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ 129 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ 130 {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 131 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ 132 {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 133 /*Set USB suspend enable local register 0xfe10[4]=1 */ 134 135 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ 136 /* format 137 * { offset, cut_msk, cmd, msk, 138 * value }, 139 * comments here 140 */ \ 141 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ 142 /*0x04[12:11] = 2b'01enable WL suspend*/ 143 144 #define RTL8188E_TRANS_CARDEMU_TO_PDN \ 145 /* format 146 * { offset, cut_msk, cmd, msk, 147 * value }, 148 * comments here 149 */ \ 150 {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ 151 /* 0x04[16] = 0*/ \ 152 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ 153 /* 0x04[15] = 1*/ 154 155 #define RTL8188E_TRANS_PDN_TO_CARDEMU \ 156 /* format 157 * { offset, cut_msk, cmd, msk, 158 * value }, 159 * comments here 160 */ \ 161 {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ 162 /* 0x04[15] = 0*/ 163 164 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ 165 #define RTL8188E_TRANS_ACT_TO_LPS \ 166 /* format 167 * { offset, cut_msk, cmd, msk, 168 * value }, 169 * comments here 170 */ \ 171 {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ 172 {0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 173 /*Should be zero if no packet is transmitting*/ \ 174 {0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 175 /*Should be zero if no packet is transmitting*/ \ 176 {0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 177 /*Should be zero if no packet is transmitting*/ \ 178 {0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ 179 /*Should be zero if no packet is transmitting*/ \ 180 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ 181 /*CCK and OFDM are disabled,and clock are gated*/ \ 182 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ 183 /*Delay 1us*/ \ 184 {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \ 185 /*Reset MAC TRX*/ \ 186 {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \ 187 /*check if removed later*/\ 188 {0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ 189 /*Respond TxOK to scheduler*/ 190 191 192 #define RTL8188E_TRANS_LPS_TO_ACT \ 193 /* format 194 * { offset, cut_msk, cmd, msk, 195 * value }, 196 * comments here 197 */ \ 198 {0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \ 199 /*USB RPWM*/ \ 200 {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \ 201 /*Delay*/ \ 202 {0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ 203 /* 0x08[4] = 0 switch TSF to 40M */ \ 204 {0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \ 205 /* Polling 0x109[7]=0 TSF in 40M */ \ 206 {0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ 207 /* 0x29[7:6] = 2b'00 enable BB clock */ \ 208 {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 209 /* 0x101[1] = 1 */ \ 210 {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 211 /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ 212 {0x0002, PWR_CUT_ALL_MSK, \ 213 PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ 214 /* 0x02[1:0] = 2b'11 enable BB macro */ \ 215 {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ 216 217 #define RTL8188E_TRANS_END \ 218 /* format 219 * { offset, cut_msk, cmd, msk, 220 * value }, 221 * comments here 222 */ \ 223 {0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0}, 224 225 226 extern struct wl_pwr_cfg rtl8188E_power_on_flow 227 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; 228 extern struct wl_pwr_cfg rtl8188E_radio_off_flow 229 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS]; 230 extern struct wl_pwr_cfg rtl8188E_card_disable_flow 231 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 232 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 233 RTL8188E_TRANS_END_STEPS]; 234 extern struct wl_pwr_cfg rtl8188E_card_enable_flow 235 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 236 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + 237 RTL8188E_TRANS_END_STEPS]; 238 extern struct wl_pwr_cfg rtl8188E_suspend_flow[ 239 RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 240 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 241 RTL8188E_TRANS_END_STEPS]; 242 extern struct wl_pwr_cfg rtl8188E_resume_flow 243 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 244 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + 245 RTL8188E_TRANS_END_STEPS]; 246 extern struct wl_pwr_cfg rtl8188E_hwpdn_flow 247 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + 248 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS]; 249 extern struct wl_pwr_cfg rtl8188E_enter_lps_flow 250 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS]; 251 extern struct wl_pwr_cfg rtl8188E_leave_lps_flow 252 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; 253 254 #endif /* __HAL8188EPWRSEQ_H__ */ 255