1 /* 2 * Register definition file for Samsung MFC V8.x Interface (FIMV) driver 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com/ 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _REGS_MFC_V8_H 13 #define _REGS_MFC_V8_H 14 15 #include <linux/sizes.h> 16 #include "regs-mfc-v7.h" 17 18 /* Additional registers for v8 */ 19 #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104 20 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 21 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 22 #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 23 24 #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138 25 #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c 26 27 #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160 28 #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260 29 #define S5P_FIMV_D_MV_BUFFER_V8 0xf460 30 31 #define S5P_FIMV_D_NUM_MV_V8 0xf134 32 #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154 33 34 #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560 35 #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564 36 37 #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0 38 #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4 39 #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc 40 #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0 41 #define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4 42 #define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0 43 44 /* Display information register */ 45 #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600 46 #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604 47 48 /* Display status */ 49 #define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608 50 51 #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c 52 #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610 53 54 #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618 55 #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c 56 #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620 57 #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624 58 59 /* Decoded picture information register */ 60 #define S5P_FIMV_D_DECODED_STATUS_V8 0xf644 61 #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648 62 #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c 63 #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650 64 #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654 65 #define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664 66 67 /* Returned value register for specific setting */ 68 #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674 69 #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678 70 #define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8 71 72 /* SEI related information */ 73 #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc 74 75 /* Encoder Registers */ 76 #define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf794 77 #define S5P_FIMV_E_RC_CONFIG_V8 0xf798 78 #define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c 79 #define S5P_FIMV_E_RC_RPARAM_V8 0xf7a4 80 #define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a8 81 #define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac 82 #define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b4 83 #define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b8 84 85 #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c 86 #define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790 87 88 #define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c 89 #define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50 90 #define S5P_FIMV_E_H264_OPTIONS_V8 0xfb54 91 92 /* MFCv8 Context buffer sizes */ 93 #define MFC_CTX_BUF_SIZE_V8 (30 * SZ_1K) /* 30KB */ 94 #define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */ 95 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */ 96 #define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */ 97 #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */ 98 99 /* Buffer size defines */ 100 #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8) 101 102 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176) 103 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \ 104 (((w) * 576 + (h) * 128) + 4128) 105 106 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \ 107 (((w) * 592) + 2336) 108 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \ 109 (((w) * 576) + 10512 + \ 110 ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4)) 111 #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \ 112 ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \ 113 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) 114 115 /* BUffer alignment defines */ 116 #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64 117 118 /* MFCv8 variant defines */ 119 #define MAX_FW_SIZE_V8 (SZ_1M) /* 1MB */ 120 #define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */ 121 #define MFC_VERSION_V8 0x80 122 #define MFC_NUM_PORTS_V8 1 123 124 #endif /*_REGS_MFC_V8_H*/ 125