1 /* 2 * Network device driver for Cell Processor-Based Blade and Celleb platform 3 * 4 * (C) Copyright IBM Corp. 2005 5 * (C) Copyright 2006 TOSHIBA CORPORATION 6 * 7 * Authors : Utz Bacher <utz.bacher@de.ibm.com> 8 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef _SPIDER_NET_H 26 #define _SPIDER_NET_H 27 28 #define VERSION "2.0 B" 29 30 #include <linux/sungem_phy.h> 31 32 int spider_net_stop(struct net_device *netdev); 33 int spider_net_open(struct net_device *netdev); 34 35 extern const struct ethtool_ops spider_net_ethtool_ops; 36 37 extern char spider_net_driver_name[]; 38 39 #define SPIDER_NET_MAX_FRAME 2312 40 #define SPIDER_NET_MAX_MTU 2294 41 #define SPIDER_NET_MIN_MTU 64 42 43 #define SPIDER_NET_RXBUF_ALIGN 128 44 45 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256 46 #define SPIDER_NET_RX_DESCRIPTORS_MIN 16 47 #define SPIDER_NET_RX_DESCRIPTORS_MAX 512 48 49 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256 50 #define SPIDER_NET_TX_DESCRIPTORS_MIN 16 51 #define SPIDER_NET_TX_DESCRIPTORS_MAX 512 52 53 #define SPIDER_NET_TX_TIMER (HZ/5) 54 #define SPIDER_NET_ANEG_TIMER (HZ) 55 #define SPIDER_NET_ANEG_TIMEOUT 5 56 57 #define SPIDER_NET_RX_CSUM_DEFAULT 1 58 59 #define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ 60 #define SPIDER_NET_NAPI_WEIGHT 64 61 62 #define SPIDER_NET_FIRMWARE_SEQS 6 63 #define SPIDER_NET_FIRMWARE_SEQWORDS 1024 64 #define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \ 65 SPIDER_NET_FIRMWARE_SEQWORDS * \ 66 sizeof(u32)) 67 #define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin" 68 69 /** spider_net SMMIO registers */ 70 #define SPIDER_NET_GHIINT0STS 0x00000000 71 #define SPIDER_NET_GHIINT1STS 0x00000004 72 #define SPIDER_NET_GHIINT2STS 0x00000008 73 #define SPIDER_NET_GHIINT0MSK 0x00000010 74 #define SPIDER_NET_GHIINT1MSK 0x00000014 75 #define SPIDER_NET_GHIINT2MSK 0x00000018 76 77 #define SPIDER_NET_GRESUMINTNUM 0x00000020 78 #define SPIDER_NET_GREINTNUM 0x00000024 79 80 #define SPIDER_NET_GFFRMNUM 0x00000028 81 #define SPIDER_NET_GFAFRMNUM 0x0000002c 82 #define SPIDER_NET_GFBFRMNUM 0x00000030 83 #define SPIDER_NET_GFCFRMNUM 0x00000034 84 #define SPIDER_NET_GFDFRMNUM 0x00000038 85 86 /* clear them (don't use it) */ 87 #define SPIDER_NET_GFREECNNUM 0x0000003c 88 #define SPIDER_NET_GONETIMENUM 0x00000040 89 90 #define SPIDER_NET_GTOUTFRMNUM 0x00000044 91 92 #define SPIDER_NET_GTXMDSET 0x00000050 93 #define SPIDER_NET_GPCCTRL 0x00000054 94 #define SPIDER_NET_GRXMDSET 0x00000058 95 #define SPIDER_NET_GIPSECINIT 0x0000005c 96 #define SPIDER_NET_GFTRESTRT 0x00000060 97 #define SPIDER_NET_GRXDMAEN 0x00000064 98 #define SPIDER_NET_GMRWOLCTRL 0x00000068 99 #define SPIDER_NET_GPCWOPCMD 0x0000006c 100 #define SPIDER_NET_GPCROPCMD 0x00000070 101 #define SPIDER_NET_GTTFRMCNT 0x00000078 102 #define SPIDER_NET_GTESTMD 0x0000007c 103 104 #define SPIDER_NET_GSINIT 0x00000080 105 #define SPIDER_NET_GSnPRGADR 0x00000084 106 #define SPIDER_NET_GSnPRGDAT 0x00000088 107 108 #define SPIDER_NET_GMACOPEMD 0x00000100 109 #define SPIDER_NET_GMACLENLMT 0x00000108 110 #define SPIDER_NET_GMACST 0x00000110 111 #define SPIDER_NET_GMACINTEN 0x00000118 112 #define SPIDER_NET_GMACPHYCTRL 0x00000120 113 114 #define SPIDER_NET_GMACAPAUSE 0x00000154 115 #define SPIDER_NET_GMACTXPAUSE 0x00000164 116 117 #define SPIDER_NET_GMACMODE 0x000001b0 118 #define SPIDER_NET_GMACBSTLMT 0x000001b4 119 120 #define SPIDER_NET_GMACUNIMACU 0x000001c0 121 #define SPIDER_NET_GMACUNIMACL 0x000001c8 122 123 #define SPIDER_NET_GMRMHFILnR 0x00000400 124 #define SPIDER_NET_MULTICAST_HASHES 256 125 126 #define SPIDER_NET_GMRUAFILnR 0x00000500 127 #define SPIDER_NET_GMRUA0FIL15R 0x00000578 128 129 #define SPIDER_NET_GTTQMSK 0x00000934 130 131 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A, 132 * 0x00000b.. for DMA controller B, etc. */ 133 #define SPIDER_NET_GDADCHA 0x00000a00 134 #define SPIDER_NET_GDADMACCNTR 0x00000a04 135 #define SPIDER_NET_GDACTDPA 0x00000a08 136 #define SPIDER_NET_GDACTDCNT 0x00000a0c 137 #define SPIDER_NET_GDACDBADDR 0x00000a20 138 #define SPIDER_NET_GDACDBSIZE 0x00000a24 139 #define SPIDER_NET_GDACNEXTDA 0x00000a28 140 #define SPIDER_NET_GDACCOMST 0x00000a2c 141 #define SPIDER_NET_GDAWBCOMST 0x00000a30 142 #define SPIDER_NET_GDAWBRSIZE 0x00000a34 143 #define SPIDER_NET_GDAWBVSIZE 0x00000a38 144 #define SPIDER_NET_GDAWBTRST 0x00000a3c 145 #define SPIDER_NET_GDAWBTRERR 0x00000a40 146 147 /* TX DMA controller registers */ 148 #define SPIDER_NET_GDTDCHA 0x00000e00 149 #define SPIDER_NET_GDTDMACCNTR 0x00000e04 150 #define SPIDER_NET_GDTCDPA 0x00000e08 151 #define SPIDER_NET_GDTDMASEL 0x00000e14 152 153 #define SPIDER_NET_ECMODE 0x00000f00 154 /* clock and reset control register */ 155 #define SPIDER_NET_CKRCTRL 0x00000ff0 156 157 /** SCONFIG registers */ 158 #define SPIDER_NET_SCONFIG_IOACTE 0x00002810 159 160 /** interrupt mask registers */ 161 #define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7 162 #define SPIDER_NET_INT1_MASK_VALUE 0x0000fff2 163 #define SPIDER_NET_INT2_MASK_VALUE 0x000003f1 164 165 /* we rely on flagged descriptor interrupts */ 166 #define SPIDER_NET_FRAMENUM_VALUE 0x00000000 167 /* set this first, then the FRAMENUM_VALUE */ 168 #define SPIDER_NET_GFXFRAMES_VALUE 0x00000000 169 170 #define SPIDER_NET_STOP_SEQ_VALUE 0x00000000 171 #define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e 172 173 #define SPIDER_NET_PHY_CTRL_VALUE 0x00040040 174 /* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/ 175 #define SPIDER_NET_RXMODE_VALUE 0x00000011 176 /* auto retransmission in case of MAC aborts */ 177 #define SPIDER_NET_TXMODE_VALUE 0x00010000 178 #define SPIDER_NET_RESTART_VALUE 0x00000000 179 #define SPIDER_NET_WOL_VALUE 0x00001111 180 #if 0 181 #define SPIDER_NET_WOL_VALUE 0x00000000 182 #endif 183 #define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71 184 185 /* pause frames: automatic, no upper retransmission count */ 186 /* outside loopback mode: ETOMOD signal dont matter, not connected */ 187 /* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */ 188 #define SPIDER_NET_OPMODE_VALUE 0x00000067 189 /*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/ 190 #define SPIDER_NET_LENLMT_VALUE 0x00000908 191 192 #define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */ 193 #define SPIDER_NET_TXPAUSE_VALUE 0x00000000 194 195 #define SPIDER_NET_MACMODE_VALUE 0x00000001 196 #define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */ 197 198 /* DMAC control register GDMACCNTR 199 * 200 * 1(0) enable r/tx dma 201 * 0000000 fixed to 0 202 * 203 * 000000 fixed to 0 204 * 0(1) en/disable descr writeback on force end 205 * 0(1) force end 206 * 207 * 000000 fixed to 0 208 * 00 burst alignment: 128 bytes 209 * 11 burst alignment: 1024 bytes 210 * 211 * 00000 fixed to 0 212 * 0 descr writeback size 32 bytes 213 * 0(1) descr chain end interrupt enable 214 * 0(1) descr status writeback enable */ 215 216 /* to set RX_DMA_EN */ 217 #define SPIDER_NET_DMA_RX_VALUE 0x80000000 218 #define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003 219 /* to set TX_DMA_EN */ 220 #define SPIDER_NET_TX_DMA_EN 0x80000000 221 #define SPIDER_NET_GDTBSTA 0x00000300 222 #define SPIDER_NET_GDTDCEIDIS 0x00000002 223 #define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \ 224 SPIDER_NET_GDTDCEIDIS | \ 225 SPIDER_NET_GDTBSTA 226 227 #define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003 228 229 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */ 230 #define SPIDER_NET_UA_DESCR_VALUE 0x00080000 231 #define SPIDER_NET_PROMISC_VALUE 0x00080000 232 #define SPIDER_NET_NONPROMISC_VALUE 0x00000000 233 234 #define SPIDER_NET_DMASEL_VALUE 0x00000001 235 236 #define SPIDER_NET_ECMODE_VALUE 0x00000000 237 238 #define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f 239 #define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f 240 241 #define SPIDER_NET_SBIMSTATE_VALUE 0x00000000 242 #define SPIDER_NET_SBTMSTATE_VALUE 0x00000000 243 244 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used 245 * with 1 << SPIDER_NET_... */ 246 enum spider_net_int0_status { 247 SPIDER_NET_GPHYINT = 0, 248 SPIDER_NET_GMAC2INT, 249 SPIDER_NET_GMAC1INT, 250 SPIDER_NET_GIPSINT, 251 SPIDER_NET_GFIFOINT, 252 SPIDER_NET_GDMACINT, 253 SPIDER_NET_GSYSINT, 254 SPIDER_NET_GPWOPCMPINT, 255 SPIDER_NET_GPROPCMPINT, 256 SPIDER_NET_GPWFFINT, 257 SPIDER_NET_GRMDADRINT, 258 SPIDER_NET_GRMARPINT, 259 SPIDER_NET_GRMMPINT, 260 SPIDER_NET_GDTDEN0INT, 261 SPIDER_NET_GDDDEN0INT, 262 SPIDER_NET_GDCDEN0INT, 263 SPIDER_NET_GDBDEN0INT, 264 SPIDER_NET_GDADEN0INT, 265 SPIDER_NET_GDTFDCINT, 266 SPIDER_NET_GDDFDCINT, 267 SPIDER_NET_GDCFDCINT, 268 SPIDER_NET_GDBFDCINT, 269 SPIDER_NET_GDAFDCINT, 270 SPIDER_NET_GTTEDINT, 271 SPIDER_NET_GDTDCEINT, 272 SPIDER_NET_GRFDNMINT, 273 SPIDER_NET_GRFCNMINT, 274 SPIDER_NET_GRFBNMINT, 275 SPIDER_NET_GRFANMINT, 276 SPIDER_NET_GRFNMINT, 277 SPIDER_NET_G1TMCNTINT, 278 SPIDER_NET_GFREECNTINT 279 }; 280 /* GHIINT1STS bits */ 281 enum spider_net_int1_status { 282 SPIDER_NET_GTMFLLINT = 0, 283 SPIDER_NET_GRMFLLINT, 284 SPIDER_NET_GTMSHTINT, 285 SPIDER_NET_GDTINVDINT, 286 SPIDER_NET_GRFDFLLINT, 287 SPIDER_NET_GDDDCEINT, 288 SPIDER_NET_GDDINVDINT, 289 SPIDER_NET_GRFCFLLINT, 290 SPIDER_NET_GDCDCEINT, 291 SPIDER_NET_GDCINVDINT, 292 SPIDER_NET_GRFBFLLINT, 293 SPIDER_NET_GDBDCEINT, 294 SPIDER_NET_GDBINVDINT, 295 SPIDER_NET_GRFAFLLINT, 296 SPIDER_NET_GDADCEINT, 297 SPIDER_NET_GDAINVDINT, 298 SPIDER_NET_GDTRSERINT, 299 SPIDER_NET_GDDRSERINT, 300 SPIDER_NET_GDCRSERINT, 301 SPIDER_NET_GDBRSERINT, 302 SPIDER_NET_GDARSERINT, 303 SPIDER_NET_GDSERINT, 304 SPIDER_NET_GDTPTERINT, 305 SPIDER_NET_GDDPTERINT, 306 SPIDER_NET_GDCPTERINT, 307 SPIDER_NET_GDBPTERINT, 308 SPIDER_NET_GDAPTERINT 309 }; 310 /* GHIINT2STS bits */ 311 enum spider_net_int2_status { 312 SPIDER_NET_GPROPERINT = 0, 313 SPIDER_NET_GMCTCRSNGINT, 314 SPIDER_NET_GMCTLCOLINT, 315 SPIDER_NET_GMCTTMOTINT, 316 SPIDER_NET_GMCRCAERINT, 317 SPIDER_NET_GMCRCALERINT, 318 SPIDER_NET_GMCRALNERINT, 319 SPIDER_NET_GMCROVRINT, 320 SPIDER_NET_GMCRRNTINT, 321 SPIDER_NET_GMCRRXERINT, 322 SPIDER_NET_GTITCSERINT, 323 SPIDER_NET_GTIFMTERINT, 324 SPIDER_NET_GTIPKTRVKINT, 325 SPIDER_NET_GTISPINGINT, 326 SPIDER_NET_GTISADNGINT, 327 SPIDER_NET_GTISPDNGINT, 328 SPIDER_NET_GRIFMTERINT, 329 SPIDER_NET_GRIPKTRVKINT, 330 SPIDER_NET_GRISPINGINT, 331 SPIDER_NET_GRISADNGINT, 332 SPIDER_NET_GRISPDNGINT 333 }; 334 335 #define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT) 336 337 /* We rely on flagged descriptor interrupts */ 338 #define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) ) 339 340 #define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT ) 341 342 #define SPIDER_NET_ERRINT ( 0xffffffff & \ 343 (~SPIDER_NET_TXINT) & \ 344 (~SPIDER_NET_RXINT) & \ 345 (~SPIDER_NET_LINKINT) ) 346 347 #define SPIDER_NET_GPREXEC 0x80000000 348 #define SPIDER_NET_GPRDAT_MASK 0x0000ffff 349 350 #define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000 351 #define SPIDER_NET_DMAC_TXFRMTL 0x00040000 352 #define SPIDER_NET_DMAC_TCP 0x00020000 353 #define SPIDER_NET_DMAC_UDP 0x00030000 354 #define SPIDER_NET_TXDCEST 0x08000000 355 356 #define SPIDER_NET_DESCR_RXFDIS 0x00000001 357 #define SPIDER_NET_DESCR_RXDCEIS 0x00000002 358 #define SPIDER_NET_DESCR_RXDEN0IS 0x00000004 359 #define SPIDER_NET_DESCR_RXINVDIS 0x00000008 360 #define SPIDER_NET_DESCR_RXRERRIS 0x00000010 361 #define SPIDER_NET_DESCR_RXFDCIMS 0x00000100 362 #define SPIDER_NET_DESCR_RXDCEIMS 0x00000200 363 #define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400 364 #define SPIDER_NET_DESCR_RXINVDIMS 0x00000800 365 #define SPIDER_NET_DESCR_RXRERRMIS 0x00001000 366 #define SPIDER_NET_DESCR_UNUSED 0x077fe0e0 367 368 #define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000 369 #define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */ 370 #define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */ 371 #define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */ 372 #define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */ 373 #define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */ 374 #define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */ 375 #define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000 376 #define SPIDER_NET_DESCR_TXDESFLG 0x00800000 377 378 #define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \ 379 SPIDER_NET_DESCR_RXRERRIS | \ 380 SPIDER_NET_DESCR_RXDEN0IMS | \ 381 SPIDER_NET_DESCR_RXINVDIMS | \ 382 SPIDER_NET_DESCR_RXRERRMIS | \ 383 SPIDER_NET_DESCR_UNUSED) 384 385 /* Descriptor, as defined by the hardware */ 386 struct spider_net_hw_descr { 387 u32 buf_addr; 388 u32 buf_size; 389 u32 next_descr_addr; 390 u32 dmac_cmd_status; 391 u32 result_size; 392 u32 valid_size; /* all zeroes for tx */ 393 u32 data_status; 394 u32 data_error; /* all zeroes for tx */ 395 } __attribute__((aligned(32))); 396 397 struct spider_net_descr { 398 struct spider_net_hw_descr *hwdescr; 399 struct sk_buff *skb; 400 u32 bus_addr; 401 struct spider_net_descr *next; 402 struct spider_net_descr *prev; 403 }; 404 405 struct spider_net_descr_chain { 406 spinlock_t lock; 407 struct spider_net_descr *head; 408 struct spider_net_descr *tail; 409 struct spider_net_descr *ring; 410 int num_desc; 411 struct spider_net_hw_descr *hwring; 412 dma_addr_t dma_addr; 413 }; 414 415 /* descriptor data_status bits */ 416 #define SPIDER_NET_RX_IPCHK 29 417 #define SPIDER_NET_RX_TCPCHK 28 418 #define SPIDER_NET_VLAN_PACKET 21 419 #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \ 420 (1 << SPIDER_NET_RX_TCPCHK) ) 421 422 /* descriptor data_error bits */ 423 #define SPIDER_NET_RX_IPCHKERR 27 424 #define SPIDER_NET_RX_RXTCPCHKERR 28 425 426 #define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR) 427 428 /* the cases we don't pass the packet to the stack. 429 * 701b8000 would be correct, but every packets gets that flag */ 430 #define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000 431 432 #define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \ 433 NETIF_MSG_PROBE | \ 434 NETIF_MSG_LINK | \ 435 NETIF_MSG_TIMER | \ 436 NETIF_MSG_IFDOWN | \ 437 NETIF_MSG_IFUP | \ 438 NETIF_MSG_RX_ERR | \ 439 NETIF_MSG_TX_ERR | \ 440 NETIF_MSG_TX_QUEUED | \ 441 NETIF_MSG_INTR | \ 442 NETIF_MSG_TX_DONE | \ 443 NETIF_MSG_RX_STATUS | \ 444 NETIF_MSG_PKTDATA | \ 445 NETIF_MSG_HW | \ 446 NETIF_MSG_WOL ) 447 448 struct spider_net_extra_stats { 449 unsigned long rx_desc_error; 450 unsigned long tx_timeouts; 451 unsigned long alloc_rx_skb_error; 452 unsigned long rx_iommu_map_error; 453 unsigned long tx_iommu_map_error; 454 unsigned long rx_desc_unk_state; 455 }; 456 457 struct spider_net_card { 458 struct net_device *netdev; 459 struct pci_dev *pdev; 460 struct mii_phy phy; 461 462 struct napi_struct napi; 463 464 int medium; 465 466 void __iomem *regs; 467 468 struct spider_net_descr_chain tx_chain; 469 struct spider_net_descr_chain rx_chain; 470 struct spider_net_descr *low_watermark; 471 472 int aneg_count; 473 struct timer_list aneg_timer; 474 struct timer_list tx_timer; 475 struct work_struct tx_timeout_task; 476 atomic_t tx_timeout_task_counter; 477 wait_queue_head_t waitq; 478 int num_rx_ints; 479 int ignore_rx_ramfull; 480 481 /* for ethtool */ 482 int msg_enable; 483 struct spider_net_extra_stats spider_stats; 484 485 /* Must be last item in struct */ 486 struct spider_net_descr darray[0]; 487 }; 488 489 #endif 490