1 /* 2 * Intel SST Haswell/Broadwell IPC Support 3 * 4 * Copyright (C) 2013, Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef __SST_HASWELL_IPC_H 18 #define __SST_HASWELL_IPC_H 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/platform_device.h> 23 #include <sound/asound.h> 24 25 #define SST_HSW_NO_CHANNELS 4 26 #define SST_HSW_MAX_DX_REGIONS 14 27 #define SST_HSW_DX_CONTEXT_SIZE (640 * 1024) 28 #define SST_HSW_CHANNELS_ALL 0xffffffff 29 30 #define SST_HSW_FW_LOG_CONFIG_DWORDS 12 31 #define SST_HSW_GLOBAL_LOG 15 32 33 /** 34 * Upfront defined maximum message size that is 35 * expected by the in/out communication pipes in FW. 36 */ 37 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400 38 #define SST_HSW_MAX_INFO_SIZE 64 39 #define SST_HSW_BUILD_HASH_LENGTH 40 40 #define SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE 500 41 #define WAVES_PARAM_COUNT 128 42 #define WAVES_PARAM_LINES 160 43 44 struct sst_hsw; 45 struct sst_hsw_stream; 46 struct sst_hsw_log_stream; 47 struct sst_pdata; 48 struct sst_module; 49 struct sst_module_runtime; 50 extern struct sst_ops haswell_ops; 51 52 /* Stream Allocate Path ID */ 53 enum sst_hsw_stream_path_id { 54 SST_HSW_STREAM_PATH_SSP0_OUT = 0, 55 SST_HSW_STREAM_PATH_SSP0_IN = 1, 56 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2, 57 }; 58 59 /* Stream Allocate Stream Type */ 60 enum sst_hsw_stream_type { 61 SST_HSW_STREAM_TYPE_RENDER = 0, 62 SST_HSW_STREAM_TYPE_SYSTEM = 1, 63 SST_HSW_STREAM_TYPE_CAPTURE = 2, 64 SST_HSW_STREAM_TYPE_LOOPBACK = 3, 65 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4, 66 }; 67 68 /* Stream Allocate Stream Format */ 69 enum sst_hsw_stream_format { 70 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0, 71 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1, 72 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2, 73 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3, 74 }; 75 76 /* Device ID */ 77 enum sst_hsw_device_id { 78 SST_HSW_DEVICE_SSP_0 = 0, 79 SST_HSW_DEVICE_SSP_1 = 1, 80 }; 81 82 /* Device Master Clock Frequency */ 83 enum sst_hsw_device_mclk { 84 SST_HSW_DEVICE_MCLK_OFF = 0, 85 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1, 86 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2, 87 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3, 88 }; 89 90 /* Device Clock Master */ 91 enum sst_hsw_device_mode { 92 SST_HSW_DEVICE_CLOCK_SLAVE = 0, 93 SST_HSW_DEVICE_CLOCK_MASTER = 1, 94 SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2, 95 }; 96 97 /* DX Power State */ 98 enum sst_hsw_dx_state { 99 SST_HSW_DX_STATE_D0 = 0, 100 SST_HSW_DX_STATE_D1 = 1, 101 SST_HSW_DX_STATE_D3 = 3, 102 SST_HSW_DX_STATE_MAX = 3, 103 }; 104 105 /* Audio stream stage IDs */ 106 enum sst_hsw_fx_stage_id { 107 SST_HSW_STAGE_ID_WAVES = 0, 108 SST_HSW_STAGE_ID_DTS = 1, 109 SST_HSW_STAGE_ID_DOLBY = 2, 110 SST_HSW_STAGE_ID_BOOST = 3, 111 SST_HSW_STAGE_ID_MAX_FX_ID 112 }; 113 114 /* DX State Type */ 115 enum sst_hsw_dx_type { 116 SST_HSW_DX_TYPE_FW_IMAGE = 0, 117 SST_HSW_DX_TYPE_MEMORY_DUMP = 1 118 }; 119 120 /* Volume Curve Type*/ 121 enum sst_hsw_volume_curve { 122 SST_HSW_VOLUME_CURVE_NONE = 0, 123 SST_HSW_VOLUME_CURVE_FADE = 1 124 }; 125 126 /* Sample ordering */ 127 enum sst_hsw_interleaving { 128 SST_HSW_INTERLEAVING_PER_CHANNEL = 0, 129 SST_HSW_INTERLEAVING_PER_SAMPLE = 1, 130 }; 131 132 /* Channel indices */ 133 enum sst_hsw_channel_index { 134 SST_HSW_CHANNEL_LEFT = 0, 135 SST_HSW_CHANNEL_CENTER = 1, 136 SST_HSW_CHANNEL_RIGHT = 2, 137 SST_HSW_CHANNEL_LEFT_SURROUND = 3, 138 SST_HSW_CHANNEL_CENTER_SURROUND = 3, 139 SST_HSW_CHANNEL_RIGHT_SURROUND = 4, 140 SST_HSW_CHANNEL_LFE = 7, 141 SST_HSW_CHANNEL_INVALID = 0xF, 142 }; 143 144 /* List of supported channel maps. */ 145 enum sst_hsw_channel_config { 146 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */ 147 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */ 148 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */ 149 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */ 150 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */ 151 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */ 152 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */ 153 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */ 154 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */ 155 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */ 156 SST_HSW_CHANNEL_CONFIG_INVALID, 157 }; 158 159 /* List of supported bit depths. */ 160 enum sst_hsw_bitdepth { 161 SST_HSW_DEPTH_8BIT = 8, 162 SST_HSW_DEPTH_16BIT = 16, 163 SST_HSW_DEPTH_24BIT = 24, /* Default. */ 164 SST_HSW_DEPTH_32BIT = 32, 165 SST_HSW_DEPTH_INVALID = 33, 166 }; 167 168 enum sst_hsw_module_id { 169 SST_HSW_MODULE_BASE_FW = 0x0, 170 SST_HSW_MODULE_MP3 = 0x1, 171 SST_HSW_MODULE_AAC_5_1 = 0x2, 172 SST_HSW_MODULE_AAC_2_0 = 0x3, 173 SST_HSW_MODULE_SRC = 0x4, 174 SST_HSW_MODULE_WAVES = 0x5, 175 SST_HSW_MODULE_DOLBY = 0x6, 176 SST_HSW_MODULE_BOOST = 0x7, 177 SST_HSW_MODULE_LPAL = 0x8, 178 SST_HSW_MODULE_DTS = 0x9, 179 SST_HSW_MODULE_PCM_CAPTURE = 0xA, 180 SST_HSW_MODULE_PCM_SYSTEM = 0xB, 181 SST_HSW_MODULE_PCM_REFERENCE = 0xC, 182 SST_HSW_MODULE_PCM = 0xD, 183 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE, 184 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF, 185 SST_HSW_MAX_MODULE_ID, 186 }; 187 188 enum sst_hsw_performance_action { 189 SST_HSW_PERF_START = 0, 190 SST_HSW_PERF_STOP = 1, 191 }; 192 193 struct sst_hsw_transfer_info { 194 uint32_t destination; /* destination address */ 195 uint32_t reverse:1; /* if 1 data flows from destination */ 196 uint32_t size:31; /* transfer size in bytes.*/ 197 uint16_t first_page_offset; /* offset to data in the first page. */ 198 uint8_t packed_pages; /* page addresses. Each occupies 20 bits */ 199 } __attribute__((packed)); 200 201 struct sst_hsw_transfer_list { 202 uint32_t transfers_count; 203 struct sst_hsw_transfer_info transfers; 204 } __attribute__((packed)); 205 206 struct sst_hsw_transfer_parameter { 207 uint32_t parameter_id; 208 uint32_t data_size; 209 union { 210 uint8_t data[1]; 211 struct sst_hsw_transfer_list transfer_list; 212 }; 213 } __attribute__((packed)); 214 215 /* SST firmware module info */ 216 struct sst_hsw_module_info { 217 u8 name[SST_HSW_MAX_INFO_SIZE]; 218 u8 version[SST_HSW_MAX_INFO_SIZE]; 219 } __attribute__((packed)); 220 221 /* Module entry point */ 222 struct sst_hsw_module_entry { 223 enum sst_hsw_module_id module_id; 224 u32 entry_point; 225 } __attribute__((packed)); 226 227 /* Module map - alignement matches DSP */ 228 struct sst_hsw_module_map { 229 u8 module_entries_count; 230 struct sst_hsw_module_entry module_entries[1]; 231 } __attribute__((packed)); 232 233 struct sst_hsw_memory_info { 234 u32 offset; 235 u32 size; 236 } __attribute__((packed)); 237 238 struct sst_hsw_fx_enable { 239 struct sst_hsw_module_map module_map; 240 struct sst_hsw_memory_info persistent_mem; 241 } __attribute__((packed)); 242 243 struct sst_hsw_ipc_module_config { 244 struct sst_hsw_module_map map; 245 struct sst_hsw_memory_info persistent_mem; 246 struct sst_hsw_memory_info scratch_mem; 247 } __attribute__((packed)); 248 249 struct sst_hsw_get_fx_param { 250 u32 parameter_id; 251 u32 param_size; 252 } __attribute__((packed)); 253 254 struct sst_hsw_perf_action { 255 u32 action; 256 } __attribute__((packed)); 257 258 struct sst_hsw_perf_data { 259 u64 timestamp; 260 u64 cycles; 261 u64 datatime; 262 } __attribute__((packed)); 263 264 /* FW version */ 265 struct sst_hsw_ipc_fw_version { 266 u8 build; 267 u8 minor; 268 u8 major; 269 u8 type; 270 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH]; 271 u32 fw_log_providers_hash; 272 } __attribute__((packed)); 273 274 /* Stream ring info */ 275 struct sst_hsw_ipc_stream_ring { 276 u32 ring_pt_address; 277 u32 num_pages; 278 u32 ring_size; 279 u32 ring_offset; 280 u32 ring_first_pfn; 281 } __attribute__((packed)); 282 283 /* Debug Dump Log Enable Request */ 284 struct sst_hsw_ipc_debug_log_enable_req { 285 struct sst_hsw_ipc_stream_ring ringinfo; 286 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS]; 287 } __attribute__((packed)); 288 289 /* Debug Dump Log Reply */ 290 struct sst_hsw_ipc_debug_log_reply { 291 u32 log_buffer_begining; 292 u32 log_buffer_size; 293 } __attribute__((packed)); 294 295 /* Stream glitch position */ 296 struct sst_hsw_ipc_stream_glitch_position { 297 u32 glitch_type; 298 u32 present_pos; 299 u32 write_pos; 300 } __attribute__((packed)); 301 302 /* Stream get position */ 303 struct sst_hsw_ipc_stream_get_position { 304 u32 position; 305 u32 fw_cycle_count; 306 } __attribute__((packed)); 307 308 /* Stream set position */ 309 struct sst_hsw_ipc_stream_set_position { 310 u32 position; 311 u32 end_of_buffer; 312 } __attribute__((packed)); 313 314 /* Stream Free Request */ 315 struct sst_hsw_ipc_stream_free_req { 316 u8 stream_id; 317 u8 reserved[3]; 318 } __attribute__((packed)); 319 320 /* Set Volume Request */ 321 struct sst_hsw_ipc_volume_req { 322 u32 channel; 323 u32 target_volume; 324 u64 curve_duration; 325 u32 curve_type; 326 } __attribute__((packed)); 327 328 /* Device Configuration Request */ 329 struct sst_hsw_ipc_device_config_req { 330 u32 ssp_interface; 331 u32 clock_frequency; 332 u32 mode; 333 u16 clock_divider; 334 u8 channels; 335 u8 reserved; 336 } __attribute__((packed)); 337 338 /* Audio Data formats */ 339 struct sst_hsw_audio_data_format_ipc { 340 u32 frequency; 341 u32 bitdepth; 342 u32 map; 343 u32 config; 344 u32 style; 345 u8 ch_num; 346 u8 valid_bit; 347 u8 reserved[2]; 348 } __attribute__((packed)); 349 350 /* Stream Allocate Request */ 351 struct sst_hsw_ipc_stream_alloc_req { 352 u8 path_id; 353 u8 stream_type; 354 u8 format_id; 355 u8 reserved; 356 struct sst_hsw_audio_data_format_ipc format; 357 struct sst_hsw_ipc_stream_ring ringinfo; 358 struct sst_hsw_module_map map; 359 struct sst_hsw_memory_info persistent_mem; 360 struct sst_hsw_memory_info scratch_mem; 361 u32 number_of_notifications; 362 } __attribute__((packed)); 363 364 /* Stream Allocate Reply */ 365 struct sst_hsw_ipc_stream_alloc_reply { 366 u32 stream_hw_id; 367 u32 mixer_hw_id; // returns rate ???? 368 u32 read_position_register_address; 369 u32 presentation_position_register_address; 370 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS]; 371 u32 volume_register_address[SST_HSW_NO_CHANNELS]; 372 } __attribute__((packed)); 373 374 /* Get Mixer Stream Info */ 375 struct sst_hsw_ipc_stream_info_reply { 376 u32 mixer_hw_id; 377 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS]; 378 u32 volume_register_address[SST_HSW_NO_CHANNELS]; 379 } __attribute__((packed)); 380 381 /* DX State Request */ 382 struct sst_hsw_ipc_dx_req { 383 u8 state; 384 u8 reserved[3]; 385 } __attribute__((packed)); 386 387 /* DX State Reply Memory Info Item */ 388 struct sst_hsw_ipc_dx_memory_item { 389 u32 offset; 390 u32 size; 391 u32 source; 392 } __attribute__((packed)); 393 394 /* DX State Reply */ 395 struct sst_hsw_ipc_dx_reply { 396 u32 entries_no; 397 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS]; 398 } __attribute__((packed)); 399 400 struct sst_hsw_ipc_fw_version; 401 402 /* SST Init & Free */ 403 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length, 404 u32 fw_offset); 405 void sst_hsw_free(struct sst_hsw *hsw); 406 int sst_hsw_fw_get_version(struct sst_hsw *hsw, 407 struct sst_hsw_ipc_fw_version *version); 408 u32 create_channel_map(enum sst_hsw_channel_config config); 409 410 /* Stream Mixer Controls - */ 411 int sst_hsw_stream_set_volume(struct sst_hsw *hsw, 412 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume); 413 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, 414 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume); 415 416 /* Global Mixer Controls - */ 417 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, 418 u32 volume); 419 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, 420 u32 *volume); 421 422 /* Stream API */ 423 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id, 424 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data), 425 void *data); 426 427 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 428 429 /* Stream Configuration */ 430 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 431 enum sst_hsw_stream_path_id path_id, 432 enum sst_hsw_stream_type stream_type, 433 enum sst_hsw_stream_format format_id); 434 435 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 436 u32 ring_pt_address, u32 num_pages, 437 u32 ring_size, u32 ring_offset, u32 ring_first_pfn); 438 439 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 440 441 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 442 u32 bits); 443 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 444 int rate); 445 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 446 enum sst_hsw_bitdepth bits); 447 int sst_hsw_stream_set_channels(struct sst_hsw *hsw, 448 struct sst_hsw_stream *stream, int channels); 449 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw, 450 struct sst_hsw_stream *stream, u32 map, 451 enum sst_hsw_channel_config config); 452 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 453 enum sst_hsw_interleaving style); 454 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw, 455 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime); 456 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw, 457 struct sst_hsw_stream *stream, u32 offset, u32 size); 458 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw, 459 struct sst_hsw_stream *stream, u32 offset, u32 size); 460 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw, 461 struct sst_hsw_stream *stream); 462 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw, 463 struct sst_hsw_stream *stream, snd_pcm_uframes_t val); 464 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw, 465 struct sst_hsw_stream *stream); 466 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw, 467 struct sst_hsw_stream *stream, bool val); 468 int sst_hsw_mixer_get_info(struct sst_hsw *hsw); 469 470 /* Stream ALSA trigger operations */ 471 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 472 int wait); 473 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 474 int wait); 475 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 476 477 /* Stream pointer positions */ 478 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw, 479 struct sst_hsw_stream *stream, u32 *position); 480 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw, 481 struct sst_hsw_stream *stream, u32 *position); 482 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw, 483 struct sst_hsw_stream *stream); 484 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw, 485 struct sst_hsw_stream *stream); 486 487 /* HW port config */ 488 int sst_hsw_device_set_config(struct sst_hsw *hsw, 489 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk, 490 enum sst_hsw_device_mode mode, u32 clock_divider); 491 492 /* DX Config */ 493 int sst_hsw_dx_set_state(struct sst_hsw *hsw, 494 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx); 495 496 /* init */ 497 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata); 498 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata); 499 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw); 500 501 /* fw module function */ 502 void sst_hsw_init_module_state(struct sst_hsw *hsw); 503 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id); 504 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id); 505 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id); 506 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id); 507 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id); 508 void sst_hsw_reset_param_buf(struct sst_hsw *hsw); 509 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf); 510 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf); 511 int sst_hsw_launch_param_buf(struct sst_hsw *hsw); 512 513 int sst_hsw_module_load(struct sst_hsw *hsw, 514 u32 module_id, u32 instance_id, char *name); 515 int sst_hsw_module_enable(struct sst_hsw *hsw, 516 u32 module_id, u32 instance_id); 517 int sst_hsw_module_disable(struct sst_hsw *hsw, 518 u32 module_id, u32 instance_id); 519 int sst_hsw_module_set_param(struct sst_hsw *hsw, 520 u32 module_id, u32 instance_id, u32 parameter_id, 521 u32 param_size, char *param); 522 523 /* runtime module management */ 524 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw, 525 int mod_id, int offset); 526 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime); 527 528 /* PM */ 529 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw); 530 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw); 531 int sst_hsw_dsp_load(struct sst_hsw *hsw); 532 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw); 533 534 #endif 535