1 /*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #ifndef __COMMON_H__
26 #define __COMMON_H__
27
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/stmmac.h>
31 #include <linux/phy.h>
32 #include <linux/module.h>
33 #if IS_ENABLED(CONFIG_VLAN_8021Q)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
36 #endif
37
38 #include "descs.h"
39 #include "mmc.h"
40
41 /* Synopsys Core versions */
42 #define DWMAC_CORE_3_40 0x34
43 #define DWMAC_CORE_3_50 0x35
44 #define DWMAC_CORE_4_00 0x40
45 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
46
47 #define DMA_TX_SIZE 512
48 #define DMA_RX_SIZE 512
49 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
50
51 #undef FRAME_FILTER_DEBUG
52 /* #define FRAME_FILTER_DEBUG */
53
54 /* Extra statistic and debug information exposed by ethtool */
55 struct stmmac_extra_stats {
56 /* Transmit errors */
57 unsigned long tx_underflow ____cacheline_aligned;
58 unsigned long tx_carrier;
59 unsigned long tx_losscarrier;
60 unsigned long vlan_tag;
61 unsigned long tx_deferred;
62 unsigned long tx_vlan;
63 unsigned long tx_jabber;
64 unsigned long tx_frame_flushed;
65 unsigned long tx_payload_error;
66 unsigned long tx_ip_header_error;
67 /* Receive errors */
68 unsigned long rx_desc;
69 unsigned long sa_filter_fail;
70 unsigned long overflow_error;
71 unsigned long ipc_csum_error;
72 unsigned long rx_collision;
73 unsigned long rx_crc;
74 unsigned long dribbling_bit;
75 unsigned long rx_length;
76 unsigned long rx_mii;
77 unsigned long rx_multicast;
78 unsigned long rx_gmac_overflow;
79 unsigned long rx_watchdog;
80 unsigned long da_rx_filter_fail;
81 unsigned long sa_rx_filter_fail;
82 unsigned long rx_missed_cntr;
83 unsigned long rx_overflow_cntr;
84 unsigned long rx_vlan;
85 /* Tx/Rx IRQ error info */
86 unsigned long tx_undeflow_irq;
87 unsigned long tx_process_stopped_irq;
88 unsigned long tx_jabber_irq;
89 unsigned long rx_overflow_irq;
90 unsigned long rx_buf_unav_irq;
91 unsigned long rx_process_stopped_irq;
92 unsigned long rx_watchdog_irq;
93 unsigned long tx_early_irq;
94 unsigned long fatal_bus_error_irq;
95 /* Tx/Rx IRQ Events */
96 unsigned long rx_early_irq;
97 unsigned long threshold;
98 unsigned long tx_pkt_n;
99 unsigned long rx_pkt_n;
100 unsigned long normal_irq_n;
101 unsigned long rx_normal_irq_n;
102 unsigned long napi_poll;
103 unsigned long tx_normal_irq_n;
104 unsigned long tx_clean;
105 unsigned long tx_set_ic_bit;
106 unsigned long irq_receive_pmt_irq_n;
107 /* MMC info */
108 unsigned long mmc_tx_irq_n;
109 unsigned long mmc_rx_irq_n;
110 unsigned long mmc_rx_csum_offload_irq_n;
111 /* EEE */
112 unsigned long irq_tx_path_in_lpi_mode_n;
113 unsigned long irq_tx_path_exit_lpi_mode_n;
114 unsigned long irq_rx_path_in_lpi_mode_n;
115 unsigned long irq_rx_path_exit_lpi_mode_n;
116 unsigned long phy_eee_wakeup_error_n;
117 /* Extended RDES status */
118 unsigned long ip_hdr_err;
119 unsigned long ip_payload_err;
120 unsigned long ip_csum_bypassed;
121 unsigned long ipv4_pkt_rcvd;
122 unsigned long ipv6_pkt_rcvd;
123 unsigned long no_ptp_rx_msg_type_ext;
124 unsigned long ptp_rx_msg_type_sync;
125 unsigned long ptp_rx_msg_type_follow_up;
126 unsigned long ptp_rx_msg_type_delay_req;
127 unsigned long ptp_rx_msg_type_delay_resp;
128 unsigned long ptp_rx_msg_type_pdelay_req;
129 unsigned long ptp_rx_msg_type_pdelay_resp;
130 unsigned long ptp_rx_msg_type_pdelay_follow_up;
131 unsigned long ptp_rx_msg_type_announce;
132 unsigned long ptp_rx_msg_type_management;
133 unsigned long ptp_rx_msg_pkt_reserved_type;
134 unsigned long ptp_frame_type;
135 unsigned long ptp_ver;
136 unsigned long timestamp_dropped;
137 unsigned long av_pkt_rcvd;
138 unsigned long av_tagged_pkt_rcvd;
139 unsigned long vlan_tag_priority_val;
140 unsigned long l3_filter_match;
141 unsigned long l4_filter_match;
142 unsigned long l3_l4_filter_no_match;
143 /* PCS */
144 unsigned long irq_pcs_ane_n;
145 unsigned long irq_pcs_link_n;
146 unsigned long irq_rgmii_n;
147 unsigned long pcs_link;
148 unsigned long pcs_duplex;
149 unsigned long pcs_speed;
150 /* debug register */
151 unsigned long mtl_tx_status_fifo_full;
152 unsigned long mtl_tx_fifo_not_empty;
153 unsigned long mmtl_fifo_ctrl;
154 unsigned long mtl_tx_fifo_read_ctrl_write;
155 unsigned long mtl_tx_fifo_read_ctrl_wait;
156 unsigned long mtl_tx_fifo_read_ctrl_read;
157 unsigned long mtl_tx_fifo_read_ctrl_idle;
158 unsigned long mac_tx_in_pause;
159 unsigned long mac_tx_frame_ctrl_xfer;
160 unsigned long mac_tx_frame_ctrl_idle;
161 unsigned long mac_tx_frame_ctrl_wait;
162 unsigned long mac_tx_frame_ctrl_pause;
163 unsigned long mac_gmii_tx_proto_engine;
164 unsigned long mtl_rx_fifo_fill_level_full;
165 unsigned long mtl_rx_fifo_fill_above_thresh;
166 unsigned long mtl_rx_fifo_fill_below_thresh;
167 unsigned long mtl_rx_fifo_fill_level_empty;
168 unsigned long mtl_rx_fifo_read_ctrl_flush;
169 unsigned long mtl_rx_fifo_read_ctrl_read_data;
170 unsigned long mtl_rx_fifo_read_ctrl_status;
171 unsigned long mtl_rx_fifo_read_ctrl_idle;
172 unsigned long mtl_rx_fifo_ctrl_active;
173 unsigned long mac_rx_frame_ctrl_fifo;
174 unsigned long mac_gmii_rx_proto_engine;
175 /* TSO */
176 unsigned long tx_tso_frames;
177 unsigned long tx_tso_nfrags;
178 };
179
180 /* CSR Frequency Access Defines*/
181 #define CSR_F_35M 35000000
182 #define CSR_F_60M 60000000
183 #define CSR_F_100M 100000000
184 #define CSR_F_150M 150000000
185 #define CSR_F_250M 250000000
186 #define CSR_F_300M 300000000
187
188 #define MAC_CSR_H_FRQ_MASK 0x20
189
190 #define HASH_TABLE_SIZE 64
191 #define PAUSE_TIME 0xffff
192
193 /* Flow Control defines */
194 #define FLOW_OFF 0
195 #define FLOW_RX 1
196 #define FLOW_TX 2
197 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
198
199 /* PCS defines */
200 #define STMMAC_PCS_RGMII (1 << 0)
201 #define STMMAC_PCS_SGMII (1 << 1)
202 #define STMMAC_PCS_TBI (1 << 2)
203 #define STMMAC_PCS_RTBI (1 << 3)
204
205 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
206
207 /* DAM HW feature register fields */
208 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
209 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
210 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
211 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
212 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
213 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
214 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
215 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
216 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
217 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
218 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
219 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
220 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
221 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
222 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
223 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
224 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
225 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
226 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
227 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
228 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
229 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
230 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
231 /* Timestamping with Internal System Time */
232 #define DMA_HW_FEAT_INTTSEN 0x02000000
233 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
234 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
235 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
236 #define DEFAULT_DMA_PBL 8
237
238 /* PCS status and mask defines */
239 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
240 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
241 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
242
243 /* Max/Min RI Watchdog Timer count value */
244 #define MAX_DMA_RIWT 0xff
245 #define MIN_DMA_RIWT 0x20
246 /* Tx coalesce parameters */
247 #define STMMAC_COAL_TX_TIMER 40000
248 #define STMMAC_MAX_COAL_TX_TICK 100000
249 #define STMMAC_TX_MAX_FRAMES 256
250 #define STMMAC_TX_FRAMES 64
251
252 /* Rx IPC status */
253 enum rx_frame_status {
254 good_frame = 0x0,
255 discard_frame = 0x1,
256 csum_none = 0x2,
257 llc_snap = 0x4,
258 dma_own = 0x8,
259 rx_not_ls = 0x10,
260 };
261
262 /* Tx status */
263 enum tx_frame_status {
264 tx_done = 0x0,
265 tx_not_ls = 0x1,
266 tx_err = 0x2,
267 tx_dma_own = 0x4,
268 };
269
270 enum dma_irq_status {
271 tx_hard_error = 0x1,
272 tx_hard_error_bump_tc = 0x2,
273 handle_rx = 0x4,
274 handle_tx = 0x8,
275 };
276
277 /* EEE and LPI defines */
278 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
279 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
280 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
281 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
282
283 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
284
285 /* Physical Coding Sublayer */
286 struct rgmii_adv {
287 unsigned int pause;
288 unsigned int duplex;
289 unsigned int lp_pause;
290 unsigned int lp_duplex;
291 };
292
293 #define STMMAC_PCS_PAUSE 1
294 #define STMMAC_PCS_ASYM_PAUSE 2
295
296 /* DMA HW capabilities */
297 struct dma_features {
298 unsigned int mbps_10_100;
299 unsigned int mbps_1000;
300 unsigned int half_duplex;
301 unsigned int hash_filter;
302 unsigned int multi_addr;
303 unsigned int pcs;
304 unsigned int sma_mdio;
305 unsigned int pmt_remote_wake_up;
306 unsigned int pmt_magic_frame;
307 unsigned int rmon;
308 /* IEEE 1588-2002 */
309 unsigned int time_stamp;
310 /* IEEE 1588-2008 */
311 unsigned int atime_stamp;
312 /* 802.3az - Energy-Efficient Ethernet (EEE) */
313 unsigned int eee;
314 unsigned int av;
315 unsigned int tsoen;
316 /* TX and RX csum */
317 unsigned int tx_coe;
318 unsigned int rx_coe;
319 unsigned int rx_coe_type1;
320 unsigned int rx_coe_type2;
321 unsigned int rxfifo_over_2048;
322 /* TX and RX number of channels */
323 unsigned int number_rx_channel;
324 unsigned int number_tx_channel;
325 /* Alternate (enhanced) DESC mode */
326 unsigned int enh_desc;
327 };
328
329 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
330 #define BUF_SIZE_16KiB 16384
331 #define BUF_SIZE_8KiB 8192
332 #define BUF_SIZE_4KiB 4096
333 #define BUF_SIZE_2KiB 2048
334
335 /* Power Down and WOL */
336 #define PMT_NOT_SUPPORTED 0
337 #define PMT_SUPPORTED 1
338
339 /* Common MAC defines */
340 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
341 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
342 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
343
344 /* Default LPI timers */
345 #define STMMAC_DEFAULT_LIT_LS 0x3E8
346 #define STMMAC_DEFAULT_TWT_LS 0x1E
347
348 #define STMMAC_CHAIN_MODE 0x1
349 #define STMMAC_RING_MODE 0x2
350
351 #define JUMBO_LEN 9000
352
353 /* Descriptors helpers */
354 struct stmmac_desc_ops {
355 /* DMA RX descriptor ring initialization */
356 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
357 int end);
358 /* DMA TX descriptor ring initialization */
359 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
360
361 /* Invoked by the xmit function to prepare the tx descriptor */
362 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
363 bool csum_flag, int mode, bool tx_own,
364 bool ls);
365 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
366 int len2, bool tx_own, bool ls,
367 unsigned int tcphdrlen,
368 unsigned int tcppayloadlen);
369 /* Set/get the owner of the descriptor */
370 void (*set_tx_owner) (struct dma_desc *p);
371 int (*get_tx_owner) (struct dma_desc *p);
372 /* Clean the tx descriptor as soon as the tx irq is received */
373 void (*release_tx_desc) (struct dma_desc *p, int mode);
374 /* Clear interrupt on tx frame completion. When this bit is
375 * set an interrupt happens as soon as the frame is transmitted */
376 void (*set_tx_ic)(struct dma_desc *p);
377 /* Last tx segment reports the transmit status */
378 int (*get_tx_ls) (struct dma_desc *p);
379 /* Return the transmit status looking at the TDES1 */
380 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
381 struct dma_desc *p, void __iomem *ioaddr);
382 /* Get the buffer size from the descriptor */
383 int (*get_tx_len) (struct dma_desc *p);
384 /* Handle extra events on specific interrupts hw dependent */
385 void (*set_rx_owner) (struct dma_desc *p);
386 /* Get the receive frame size */
387 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
388 /* Return the reception status looking at the RDES1 */
389 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
390 struct dma_desc *p);
391 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
392 struct dma_extended_desc *p);
393 /* Set tx timestamp enable bit */
394 void (*enable_tx_timestamp) (struct dma_desc *p);
395 /* get tx timestamp status */
396 int (*get_tx_timestamp_status) (struct dma_desc *p);
397 /* get timestamp value */
398 u64(*get_timestamp) (void *desc, u32 ats);
399 /* get rx timestamp status */
400 int (*get_rx_timestamp_status) (void *desc, u32 ats);
401 /* Display ring */
402 void (*display_ring)(void *head, unsigned int size, bool rx);
403 /* set MSS via context descriptor */
404 void (*set_mss)(struct dma_desc *p, unsigned int mss);
405 };
406
407 extern const struct stmmac_desc_ops enh_desc_ops;
408 extern const struct stmmac_desc_ops ndesc_ops;
409
410 /* Specific DMA helpers */
411 struct stmmac_dma_ops {
412 /* DMA core initialization */
413 int (*reset)(void __iomem *ioaddr);
414 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
415 int aal, u32 dma_tx, u32 dma_rx, int atds);
416 /* Configure the AXI Bus Mode Register */
417 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
418 /* Dump DMA registers */
419 void (*dump_regs) (void __iomem *ioaddr);
420 /* Set tx/rx threshold in the csr6 register
421 * An invalid value enables the store-and-forward mode */
422 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
423 int rxfifosz);
424 /* To track extra statistic (if supported) */
425 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
426 void __iomem *ioaddr);
427 void (*enable_dma_transmission) (void __iomem *ioaddr);
428 void (*enable_dma_irq) (void __iomem *ioaddr);
429 void (*disable_dma_irq) (void __iomem *ioaddr);
430 void (*start_tx) (void __iomem *ioaddr);
431 void (*stop_tx) (void __iomem *ioaddr);
432 void (*start_rx) (void __iomem *ioaddr);
433 void (*stop_rx) (void __iomem *ioaddr);
434 int (*dma_interrupt) (void __iomem *ioaddr,
435 struct stmmac_extra_stats *x);
436 /* If supported then get the optional core features */
437 void (*get_hw_feature)(void __iomem *ioaddr,
438 struct dma_features *dma_cap);
439 /* Program the HW RX Watchdog */
440 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
441 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
442 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
443 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
444 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
445 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
446 };
447
448 struct mac_device_info;
449
450 /* Helpers to program the MAC core */
451 struct stmmac_ops {
452 /* MAC core initialization */
453 void (*core_init)(struct mac_device_info *hw, int mtu);
454 /* Enable and verify that the IPC module is supported */
455 int (*rx_ipc)(struct mac_device_info *hw);
456 /* Dump MAC registers */
457 void (*dump_regs)(struct mac_device_info *hw);
458 /* Handle extra events on specific interrupts hw dependent */
459 int (*host_irq_status)(struct mac_device_info *hw,
460 struct stmmac_extra_stats *x);
461 /* Multicast filter setting */
462 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
463 /* Flow control setting */
464 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
465 unsigned int fc, unsigned int pause_time);
466 /* Set power management mode (e.g. magic frame) */
467 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
468 /* Set/Get Unicast MAC addresses */
469 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
470 unsigned int reg_n);
471 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
472 unsigned int reg_n);
473 void (*set_eee_mode)(struct mac_device_info *hw);
474 void (*reset_eee_mode)(struct mac_device_info *hw);
475 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
476 void (*set_eee_pls)(struct mac_device_info *hw, int link);
477 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
478 /* PCS calls */
479 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
480 bool loopback);
481 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
482 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
483 };
484
485 /* PTP and HW Timer helpers */
486 struct stmmac_hwtimestamp {
487 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
488 u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
489 int gmac4);
490 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
491 int (*config_addend) (void __iomem *ioaddr, u32 addend);
492 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
493 int add_sub, int gmac4);
494 u64(*get_systime) (void __iomem *ioaddr);
495 };
496
497 extern const struct stmmac_hwtimestamp stmmac_ptp;
498 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
499
500 struct mac_link {
501 int port;
502 int duplex;
503 int speed;
504 };
505
506 struct mii_regs {
507 unsigned int addr; /* MII Address */
508 unsigned int data; /* MII Data */
509 };
510
511 /* Helpers to manage the descriptors for chain and ring modes */
512 struct stmmac_mode_ops {
513 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
514 unsigned int extend_desc);
515 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
516 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
517 int (*set_16kib_bfsize)(int mtu);
518 void (*init_desc3)(struct dma_desc *p);
519 void (*refill_desc3) (void *priv, struct dma_desc *p);
520 void (*clean_desc3) (void *priv, struct dma_desc *p);
521 };
522
523 struct mac_device_info {
524 const struct stmmac_ops *mac;
525 const struct stmmac_desc_ops *desc;
526 const struct stmmac_dma_ops *dma;
527 const struct stmmac_mode_ops *mode;
528 const struct stmmac_hwtimestamp *ptp;
529 struct mii_regs mii; /* MII register Addresses */
530 struct mac_link link;
531 void __iomem *pcsr; /* vpointer to device CSRs */
532 int multicast_filter_bins;
533 int unicast_filter_entries;
534 int mcast_bits_log2;
535 unsigned int rx_csum;
536 unsigned int pcs;
537 unsigned int pmt;
538 unsigned int ps;
539 };
540
541 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
542 int perfect_uc_entries,
543 int *synopsys_id);
544 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
545 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
546 int perfect_uc_entries, int *synopsys_id);
547
548 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
549 unsigned int high, unsigned int low);
550 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
551 unsigned int high, unsigned int low);
552 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
553
554 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
555 unsigned int high, unsigned int low);
556 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
557 unsigned int high, unsigned int low);
558 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
559
560 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
561
562 extern const struct stmmac_mode_ops ring_mode_ops;
563 extern const struct stmmac_mode_ops chain_mode_ops;
564 extern const struct stmmac_desc_ops dwmac4_desc_ops;
565
566 /**
567 * stmmac_get_synopsys_id - return the SYINID.
568 * @priv: driver private structure
569 * Description: this simple function is to decode and return the SYINID
570 * starting from the HW core register.
571 */
stmmac_get_synopsys_id(u32 hwid)572 static inline u32 stmmac_get_synopsys_id(u32 hwid)
573 {
574 /* Check Synopsys Id (not available on old chips) */
575 if (likely(hwid)) {
576 u32 uid = ((hwid & 0x0000ff00) >> 8);
577 u32 synid = (hwid & 0x000000ff);
578
579 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
580 uid, synid);
581
582 return synid;
583 }
584 return 0;
585 }
586 #endif /* __COMMON_H__ */
587