1 /* 2 * Header file for Analogix DP (Display Port) core interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #ifndef _ANALOGIX_DP_CORE_H 14 #define _ANALOGIX_DP_CORE_H 15 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_dp_helper.h> 18 19 #define DP_TIMEOUT_LOOP_COUNT 100 20 #define MAX_CR_LOOP 5 21 #define MAX_EQ_LOOP 5 22 23 /* DP_MAX_LANE_COUNT */ 24 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 25 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 26 27 /* DP_LANE_COUNT_SET */ 28 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 29 30 /* DP_TRAINING_LANE0_SET */ 31 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 32 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 33 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 34 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 35 36 enum link_lane_count_type { 37 LANE_COUNT1 = 1, 38 LANE_COUNT2 = 2, 39 LANE_COUNT4 = 4 40 }; 41 42 enum link_training_state { 43 START, 44 CLOCK_RECOVERY, 45 EQUALIZER_TRAINING, 46 FINISHED, 47 FAILED 48 }; 49 50 enum voltage_swing_level { 51 VOLTAGE_LEVEL_0, 52 VOLTAGE_LEVEL_1, 53 VOLTAGE_LEVEL_2, 54 VOLTAGE_LEVEL_3, 55 }; 56 57 enum pre_emphasis_level { 58 PRE_EMPHASIS_LEVEL_0, 59 PRE_EMPHASIS_LEVEL_1, 60 PRE_EMPHASIS_LEVEL_2, 61 PRE_EMPHASIS_LEVEL_3, 62 }; 63 64 enum pattern_set { 65 PRBS7, 66 D10_2, 67 TRAINING_PTN1, 68 TRAINING_PTN2, 69 DP_NONE 70 }; 71 72 enum color_space { 73 COLOR_RGB, 74 COLOR_YCBCR422, 75 COLOR_YCBCR444 76 }; 77 78 enum color_depth { 79 COLOR_6, 80 COLOR_8, 81 COLOR_10, 82 COLOR_12 83 }; 84 85 enum color_coefficient { 86 COLOR_YCBCR601, 87 COLOR_YCBCR709 88 }; 89 90 enum dynamic_range { 91 VESA, 92 CEA 93 }; 94 95 enum pll_status { 96 PLL_UNLOCKED, 97 PLL_LOCKED 98 }; 99 100 enum clock_recovery_m_value_type { 101 CALCULATED_M, 102 REGISTER_M 103 }; 104 105 enum video_timing_recognition_type { 106 VIDEO_TIMING_FROM_CAPTURE, 107 VIDEO_TIMING_FROM_REGISTER 108 }; 109 110 enum analog_power_block { 111 AUX_BLOCK, 112 CH0_BLOCK, 113 CH1_BLOCK, 114 CH2_BLOCK, 115 CH3_BLOCK, 116 ANALOG_TOTAL, 117 POWER_ALL 118 }; 119 120 enum dp_irq_type { 121 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 122 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 123 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 124 DP_IRQ_TYPE_UNKNOWN = BIT(3), 125 }; 126 127 struct video_info { 128 char *name; 129 130 bool h_sync_polarity; 131 bool v_sync_polarity; 132 bool interlaced; 133 134 enum color_space color_space; 135 enum dynamic_range dynamic_range; 136 enum color_coefficient ycbcr_coeff; 137 enum color_depth color_depth; 138 139 int max_link_rate; 140 enum link_lane_count_type max_lane_count; 141 }; 142 143 struct link_train { 144 int eq_loop; 145 int cr_loop[4]; 146 147 u8 link_rate; 148 u8 lane_count; 149 u8 training_lane[4]; 150 151 enum link_training_state lt_state; 152 }; 153 154 struct analogix_dp_device { 155 struct drm_encoder *encoder; 156 struct device *dev; 157 struct drm_device *drm_dev; 158 struct drm_connector connector; 159 struct drm_bridge *bridge; 160 struct drm_dp_aux aux; 161 struct clk *clock; 162 unsigned int irq; 163 void __iomem *reg_base; 164 165 struct video_info video_info; 166 struct link_train link_train; 167 struct phy *phy; 168 int dpms_mode; 169 int hpd_gpio; 170 bool force_hpd; 171 bool psr_support; 172 173 struct mutex panel_lock; 174 bool panel_is_modeset; 175 176 struct analogix_dp_plat_data *plat_data; 177 }; 178 179 /* analogix_dp_reg.c */ 180 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 181 void analogix_dp_stop_video(struct analogix_dp_device *dp); 182 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 183 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 184 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 185 void analogix_dp_reset(struct analogix_dp_device *dp); 186 void analogix_dp_swreset(struct analogix_dp_device *dp); 187 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 188 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 189 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 190 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 191 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 192 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 193 enum analog_power_block block, 194 bool enable); 195 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 196 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 197 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 198 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 199 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 200 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 201 void analogix_dp_init_aux(struct analogix_dp_device *dp); 202 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 203 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 204 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 205 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 206 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 207 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 208 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 209 bool enable); 210 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 211 enum pattern_set pattern); 212 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 213 u32 level); 214 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 215 u32 level); 216 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 217 u32 level); 218 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 219 u32 level); 220 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 221 u32 training_lane); 222 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 223 u32 training_lane); 224 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 225 u32 training_lane); 226 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 227 u32 training_lane); 228 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); 229 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); 230 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); 231 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); 232 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 233 void analogix_dp_init_video(struct analogix_dp_device *dp); 234 235 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 236 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 237 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 238 enum clock_recovery_m_value_type type, 239 u32 m_value, 240 u32 n_value); 241 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 242 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 243 bool enable); 244 void analogix_dp_start_video(struct analogix_dp_device *dp); 245 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 246 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 247 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 248 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 249 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); 250 void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 251 struct edp_vsc_psr *vsc); 252 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, 253 struct drm_dp_aux_msg *msg); 254 255 #endif /* _ANALOGIX_DP_CORE_H */ 256