1 /* 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the Broadcom 9 * license below: 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* #define MAC_SPLIT_MODE */ 35 36 #define MAC_SPACING 0x400 37 #define XGMAC_SPACING 0x400 38 39 /* PE-MCXMAC register and bit field definitions */ 40 #define R_MAC_CONFIG_1 0x00 41 #define O_MAC_CONFIG_1__srst 31 42 #define O_MAC_CONFIG_1__simr 30 43 #define O_MAC_CONFIG_1__hrrmc 18 44 #define W_MAC_CONFIG_1__hrtmc 2 45 #define O_MAC_CONFIG_1__hrrfn 16 46 #define W_MAC_CONFIG_1__hrtfn 2 47 #define O_MAC_CONFIG_1__intlb 8 48 #define O_MAC_CONFIG_1__rxfc 5 49 #define O_MAC_CONFIG_1__txfc 4 50 #define O_MAC_CONFIG_1__srxen 3 51 #define O_MAC_CONFIG_1__rxen 2 52 #define O_MAC_CONFIG_1__stxen 1 53 #define O_MAC_CONFIG_1__txen 0 54 #define R_MAC_CONFIG_2 0x01 55 #define O_MAC_CONFIG_2__prlen 12 56 #define W_MAC_CONFIG_2__prlen 4 57 #define O_MAC_CONFIG_2__speed 8 58 #define W_MAC_CONFIG_2__speed 2 59 #define O_MAC_CONFIG_2__hugen 5 60 #define O_MAC_CONFIG_2__flchk 4 61 #define O_MAC_CONFIG_2__crce 1 62 #define O_MAC_CONFIG_2__fulld 0 63 #define R_IPG_IFG 0x02 64 #define O_IPG_IFG__ipgr1 24 65 #define W_IPG_IFG__ipgr1 7 66 #define O_IPG_IFG__ipgr2 16 67 #define W_IPG_IFG__ipgr2 7 68 #define O_IPG_IFG__mifg 8 69 #define W_IPG_IFG__mifg 8 70 #define O_IPG_IFG__ipgt 0 71 #define W_IPG_IFG__ipgt 7 72 #define R_HALF_DUPLEX 0x03 73 #define O_HALF_DUPLEX__abebt 24 74 #define W_HALF_DUPLEX__abebt 4 75 #define O_HALF_DUPLEX__abebe 19 76 #define O_HALF_DUPLEX__bpnb 18 77 #define O_HALF_DUPLEX__nobo 17 78 #define O_HALF_DUPLEX__edxsdfr 16 79 #define O_HALF_DUPLEX__retry 12 80 #define W_HALF_DUPLEX__retry 4 81 #define O_HALF_DUPLEX__lcol 0 82 #define W_HALF_DUPLEX__lcol 10 83 #define R_MAXIMUM_FRAME_LENGTH 0x04 84 #define O_MAXIMUM_FRAME_LENGTH__maxf 0 85 #define W_MAXIMUM_FRAME_LENGTH__maxf 16 86 #define R_TEST 0x07 87 #define O_TEST__mbof 3 88 #define O_TEST__rthdf 2 89 #define O_TEST__tpause 1 90 #define O_TEST__sstct 0 91 #define R_MII_MGMT_CONFIG 0x08 92 #define O_MII_MGMT_CONFIG__scinc 5 93 #define O_MII_MGMT_CONFIG__spre 4 94 #define O_MII_MGMT_CONFIG__clks 3 95 #define W_MII_MGMT_CONFIG__clks 3 96 #define R_MII_MGMT_COMMAND 0x09 97 #define O_MII_MGMT_COMMAND__scan 1 98 #define O_MII_MGMT_COMMAND__rstat 0 99 #define R_MII_MGMT_ADDRESS 0x0A 100 #define O_MII_MGMT_ADDRESS__fiad 8 101 #define W_MII_MGMT_ADDRESS__fiad 5 102 #define O_MII_MGMT_ADDRESS__fgad 5 103 #define W_MII_MGMT_ADDRESS__fgad 0 104 #define R_MII_MGMT_WRITE_DATA 0x0B 105 #define O_MII_MGMT_WRITE_DATA__ctld 0 106 #define W_MII_MGMT_WRITE_DATA__ctld 16 107 #define R_MII_MGMT_STATUS 0x0C 108 #define R_MII_MGMT_INDICATORS 0x0D 109 #define O_MII_MGMT_INDICATORS__nvalid 2 110 #define O_MII_MGMT_INDICATORS__scan 1 111 #define O_MII_MGMT_INDICATORS__busy 0 112 #define R_INTERFACE_CONTROL 0x0E 113 #define O_INTERFACE_CONTROL__hrstint 31 114 #define O_INTERFACE_CONTROL__tbimode 27 115 #define O_INTERFACE_CONTROL__ghdmode 26 116 #define O_INTERFACE_CONTROL__lhdmode 25 117 #define O_INTERFACE_CONTROL__phymod 24 118 #define O_INTERFACE_CONTROL__hrrmi 23 119 #define O_INTERFACE_CONTROL__rspd 16 120 #define O_INTERFACE_CONTROL__hr100 15 121 #define O_INTERFACE_CONTROL__frcq 10 122 #define O_INTERFACE_CONTROL__nocfr 9 123 #define O_INTERFACE_CONTROL__dlfct 8 124 #define O_INTERFACE_CONTROL__enjab 0 125 #define R_INTERFACE_STATUS 0x0F 126 #define O_INTERFACE_STATUS__xsdfr 9 127 #define O_INTERFACE_STATUS__ssrr 8 128 #define W_INTERFACE_STATUS__ssrr 5 129 #define O_INTERFACE_STATUS__miilf 3 130 #define O_INTERFACE_STATUS__locar 2 131 #define O_INTERFACE_STATUS__sqerr 1 132 #define O_INTERFACE_STATUS__jabber 0 133 #define R_STATION_ADDRESS_LS 0x10 134 #define R_STATION_ADDRESS_MS 0x11 135 136 /* A-XGMAC register and bit field definitions */ 137 #define R_XGMAC_CONFIG_0 0x00 138 #define O_XGMAC_CONFIG_0__hstmacrst 31 139 #define O_XGMAC_CONFIG_0__hstrstrctl 23 140 #define O_XGMAC_CONFIG_0__hstrstrfn 22 141 #define O_XGMAC_CONFIG_0__hstrsttctl 18 142 #define O_XGMAC_CONFIG_0__hstrsttfn 17 143 #define O_XGMAC_CONFIG_0__hstrstmiim 16 144 #define O_XGMAC_CONFIG_0__hstloopback 8 145 #define R_XGMAC_CONFIG_1 0x01 146 #define O_XGMAC_CONFIG_1__hsttctlen 31 147 #define O_XGMAC_CONFIG_1__hsttfen 30 148 #define O_XGMAC_CONFIG_1__hstrctlen 29 149 #define O_XGMAC_CONFIG_1__hstrfen 28 150 #define O_XGMAC_CONFIG_1__tfen 26 151 #define O_XGMAC_CONFIG_1__rfen 24 152 #define O_XGMAC_CONFIG_1__hstrctlshrtp 12 153 #define O_XGMAC_CONFIG_1__hstdlyfcstx 10 154 #define W_XGMAC_CONFIG_1__hstdlyfcstx 2 155 #define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 156 #define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 157 #define O_XGMAC_CONFIG_1__hstppen 7 158 #define O_XGMAC_CONFIG_1__hstbytswp 6 159 #define O_XGMAC_CONFIG_1__hstdrplt64 5 160 #define O_XGMAC_CONFIG_1__hstprmscrx 4 161 #define O_XGMAC_CONFIG_1__hstlenchk 3 162 #define O_XGMAC_CONFIG_1__hstgenfcs 2 163 #define O_XGMAC_CONFIG_1__hstpadmode 0 164 #define W_XGMAC_CONFIG_1__hstpadmode 2 165 #define R_XGMAC_CONFIG_2 0x02 166 #define O_XGMAC_CONFIG_2__hsttctlfrcp 31 167 #define O_XGMAC_CONFIG_2__hstmlnkflth 27 168 #define O_XGMAC_CONFIG_2__hstalnkflth 26 169 #define O_XGMAC_CONFIG_2__rflnkflt 24 170 #define W_XGMAC_CONFIG_2__rflnkflt 2 171 #define O_XGMAC_CONFIG_2__hstipgextmod 16 172 #define W_XGMAC_CONFIG_2__hstipgextmod 5 173 #define O_XGMAC_CONFIG_2__hstrctlfrcp 15 174 #define O_XGMAC_CONFIG_2__hstipgexten 5 175 #define O_XGMAC_CONFIG_2__hstmipgext 0 176 #define W_XGMAC_CONFIG_2__hstmipgext 5 177 #define R_XGMAC_CONFIG_3 0x03 178 #define O_XGMAC_CONFIG_3__hstfltrfrm 31 179 #define W_XGMAC_CONFIG_3__hstfltrfrm 16 180 #define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 181 #define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 182 #define R_XGMAC_STATION_ADDRESS_LS 0x04 183 #define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 184 #define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 185 #define R_XGMAC_STATION_ADDRESS_MS 0x05 186 #define R_XGMAC_MAX_FRAME_LEN 0x08 187 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 188 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 189 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 190 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 191 #define R_XGMAC_REV_LEVEL 0x0B 192 #define O_XGMAC_REV_LEVEL__revlvl 0 193 #define W_XGMAC_REV_LEVEL__revlvl 15 194 #define R_XGMAC_MIIM_COMMAND 0x10 195 #define O_XGMAC_MIIM_COMMAND__hstldcmd 3 196 #define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 197 #define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 198 #define R_XGMAC_MIIM_FILED 0x11 199 #define O_XGMAC_MIIM_FILED__hststfield 30 200 #define W_XGMAC_MIIM_FILED__hststfield 2 201 #define O_XGMAC_MIIM_FILED__hstopfield 28 202 #define W_XGMAC_MIIM_FILED__hstopfield 2 203 #define O_XGMAC_MIIM_FILED__hstphyadx 23 204 #define W_XGMAC_MIIM_FILED__hstphyadx 5 205 #define O_XGMAC_MIIM_FILED__hstregadx 18 206 #define W_XGMAC_MIIM_FILED__hstregadx 5 207 #define O_XGMAC_MIIM_FILED__hsttafield 16 208 #define W_XGMAC_MIIM_FILED__hsttafield 2 209 #define O_XGMAC_MIIM_FILED__miimrddat 0 210 #define W_XGMAC_MIIM_FILED__miimrddat 16 211 #define R_XGMAC_MIIM_CONFIG 0x12 212 #define O_XGMAC_MIIM_CONFIG__hstnopram 7 213 #define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 214 #define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 215 #define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 216 #define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 217 #define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 218 #define R_XGMAC_MIIM_INDICATOR 0x14 219 #define O_XGMAC_MIIM_INDICATOR__miimphylf 4 220 #define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 221 #define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 222 #define O_XGMAC_MIIM_INDICATOR__miimmon 1 223 #define O_XGMAC_MIIM_INDICATOR__miimbusy 0 224 225 /* GMAC stats registers */ 226 #define R_RBYT 0x27 227 #define R_RPKT 0x28 228 #define R_RFCS 0x29 229 #define R_RMCA 0x2A 230 #define R_RBCA 0x2B 231 #define R_RXCF 0x2C 232 #define R_RXPF 0x2D 233 #define R_RXUO 0x2E 234 #define R_RALN 0x2F 235 #define R_RFLR 0x30 236 #define R_RCDE 0x31 237 #define R_RCSE 0x32 238 #define R_RUND 0x33 239 #define R_ROVR 0x34 240 #define R_TBYT 0x38 241 #define R_TPKT 0x39 242 #define R_TMCA 0x3A 243 #define R_TBCA 0x3B 244 #define R_TXPF 0x3C 245 #define R_TDFR 0x3D 246 #define R_TEDF 0x3E 247 #define R_TSCL 0x3F 248 #define R_TMCL 0x40 249 #define R_TLCL 0x41 250 #define R_TXCL 0x42 251 #define R_TNCL 0x43 252 #define R_TJBR 0x46 253 #define R_TFCS 0x47 254 #define R_TXCF 0x48 255 #define R_TOVR 0x49 256 #define R_TUND 0x4A 257 #define R_TFRG 0x4B 258 259 /* Glue logic register and bit field definitions */ 260 #define R_MAC_ADDR0 0x50 261 #define R_MAC_ADDR1 0x52 262 #define R_MAC_ADDR2 0x54 263 #define R_MAC_ADDR3 0x56 264 #define R_MAC_ADDR_MASK2 0x58 265 #define R_MAC_ADDR_MASK3 0x5A 266 #define R_MAC_FILTER_CONFIG 0x5C 267 #define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 268 #define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 269 #define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 270 #define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 271 #define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 272 #define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 273 #define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 274 #define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 275 #define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 276 #define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 277 #define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 278 #define R_HASH_TABLE_VECTOR 0x30 279 #define R_TX_CONTROL 0x0A0 280 #define O_TX_CONTROL__TX15HALT 31 281 #define O_TX_CONTROL__TX14HALT 30 282 #define O_TX_CONTROL__TX13HALT 29 283 #define O_TX_CONTROL__TX12HALT 28 284 #define O_TX_CONTROL__TX11HALT 27 285 #define O_TX_CONTROL__TX10HALT 26 286 #define O_TX_CONTROL__TX9HALT 25 287 #define O_TX_CONTROL__TX8HALT 24 288 #define O_TX_CONTROL__TX7HALT 23 289 #define O_TX_CONTROL__TX6HALT 22 290 #define O_TX_CONTROL__TX5HALT 21 291 #define O_TX_CONTROL__TX4HALT 20 292 #define O_TX_CONTROL__TX3HALT 19 293 #define O_TX_CONTROL__TX2HALT 18 294 #define O_TX_CONTROL__TX1HALT 17 295 #define O_TX_CONTROL__TX0HALT 16 296 #define O_TX_CONTROL__TXIDLE 15 297 #define O_TX_CONTROL__TXENABLE 14 298 #define O_TX_CONTROL__TXTHRESHOLD 0 299 #define W_TX_CONTROL__TXTHRESHOLD 14 300 #define R_RX_CONTROL 0x0A1 301 #define O_RX_CONTROL__RGMII 10 302 #define O_RX_CONTROL__SOFTRESET 2 303 #define O_RX_CONTROL__RXHALT 1 304 #define O_RX_CONTROL__RXENABLE 0 305 #define R_DESC_PACK_CTRL 0x0A2 306 #define O_DESC_PACK_CTRL__BYTEOFFSET 17 307 #define W_DESC_PACK_CTRL__BYTEOFFSET 3 308 #define O_DESC_PACK_CTRL__PREPADENABLE 16 309 #define O_DESC_PACK_CTRL__MAXENTRY 14 310 #define W_DESC_PACK_CTRL__MAXENTRY 2 311 #define O_DESC_PACK_CTRL__REGULARSIZE 0 312 #define W_DESC_PACK_CTRL__REGULARSIZE 14 313 #define R_STATCTRL 0x0A3 314 #define O_STATCTRL__OVERFLOWEN 4 315 #define O_STATCTRL__GIG 3 316 #define O_STATCTRL__STEN 2 317 #define O_STATCTRL__CLRCNT 1 318 #define O_STATCTRL__AUTOZ 0 319 #define R_L2ALLOCCTRL 0x0A4 320 #define O_L2ALLOCCTRL__TXL2ALLOCATE 9 321 #define W_L2ALLOCCTRL__TXL2ALLOCATE 9 322 #define O_L2ALLOCCTRL__RXL2ALLOCATE 0 323 #define W_L2ALLOCCTRL__RXL2ALLOCATE 9 324 #define R_INTMASK 0x0A5 325 #define O_INTMASK__SPI4TXERROR 28 326 #define O_INTMASK__SPI4RXERROR 27 327 #define O_INTMASK__RGMIIHALFDUPCOLLISION 27 328 #define O_INTMASK__ABORT 26 329 #define O_INTMASK__UNDERRUN 25 330 #define O_INTMASK__DISCARDPACKET 24 331 #define O_INTMASK__ASYNCFIFOFULL 23 332 #define O_INTMASK__TAGFULL 22 333 #define O_INTMASK__CLASS3FULL 21 334 #define O_INTMASK__C3EARLYFULL 20 335 #define O_INTMASK__CLASS2FULL 19 336 #define O_INTMASK__C2EARLYFULL 18 337 #define O_INTMASK__CLASS1FULL 17 338 #define O_INTMASK__C1EARLYFULL 16 339 #define O_INTMASK__CLASS0FULL 15 340 #define O_INTMASK__C0EARLYFULL 14 341 #define O_INTMASK__RXDATAFULL 13 342 #define O_INTMASK__RXEARLYFULL 12 343 #define O_INTMASK__RFREEEMPTY 9 344 #define O_INTMASK__RFEARLYEMPTY 8 345 #define O_INTMASK__P2PSPILLECC 7 346 #define O_INTMASK__FREEDESCFULL 5 347 #define O_INTMASK__FREEEARLYFULL 4 348 #define O_INTMASK__TXFETCHERROR 3 349 #define O_INTMASK__STATCARRY 2 350 #define O_INTMASK__MDINT 1 351 #define O_INTMASK__TXILLEGAL 0 352 #define R_INTREG 0x0A6 353 #define O_INTREG__SPI4TXERROR 28 354 #define O_INTREG__SPI4RXERROR 27 355 #define O_INTREG__RGMIIHALFDUPCOLLISION 27 356 #define O_INTREG__ABORT 26 357 #define O_INTREG__UNDERRUN 25 358 #define O_INTREG__DISCARDPACKET 24 359 #define O_INTREG__ASYNCFIFOFULL 23 360 #define O_INTREG__TAGFULL 22 361 #define O_INTREG__CLASS3FULL 21 362 #define O_INTREG__C3EARLYFULL 20 363 #define O_INTREG__CLASS2FULL 19 364 #define O_INTREG__C2EARLYFULL 18 365 #define O_INTREG__CLASS1FULL 17 366 #define O_INTREG__C1EARLYFULL 16 367 #define O_INTREG__CLASS0FULL 15 368 #define O_INTREG__C0EARLYFULL 14 369 #define O_INTREG__RXDATAFULL 13 370 #define O_INTREG__RXEARLYFULL 12 371 #define O_INTREG__RFREEEMPTY 9 372 #define O_INTREG__RFEARLYEMPTY 8 373 #define O_INTREG__P2PSPILLECC 7 374 #define O_INTREG__FREEDESCFULL 5 375 #define O_INTREG__FREEEARLYFULL 4 376 #define O_INTREG__TXFETCHERROR 3 377 #define O_INTREG__STATCARRY 2 378 #define O_INTREG__MDINT 1 379 #define O_INTREG__TXILLEGAL 0 380 #define R_TXRETRY 0x0A7 381 #define O_TXRETRY__COLLISIONRETRY 6 382 #define O_TXRETRY__BUSERRORRETRY 5 383 #define O_TXRETRY__UNDERRUNRETRY 4 384 #define O_TXRETRY__RETRIES 0 385 #define W_TXRETRY__RETRIES 4 386 #define R_CORECONTROL 0x0A8 387 #define O_CORECONTROL__ERRORTHREAD 4 388 #define W_CORECONTROL__ERRORTHREAD 7 389 #define O_CORECONTROL__SHUTDOWN 2 390 #define O_CORECONTROL__SPEED 0 391 #define W_CORECONTROL__SPEED 2 392 #define R_BYTEOFFSET0 0x0A9 393 #define R_BYTEOFFSET1 0x0AA 394 #define R_L2TYPE_0 0x0F0 395 #define O_L2TYPE__EXTRAHDRPROTOSIZE 26 396 #define W_L2TYPE__EXTRAHDRPROTOSIZE 5 397 #define O_L2TYPE__EXTRAHDRPROTOOFFSET 20 398 #define W_L2TYPE__EXTRAHDRPROTOOFFSET 6 399 #define O_L2TYPE__EXTRAHEADERSIZE 14 400 #define W_L2TYPE__EXTRAHEADERSIZE 6 401 #define O_L2TYPE__PROTOOFFSET 8 402 #define W_L2TYPE__PROTOOFFSET 6 403 #define O_L2TYPE__L2HDROFFSET 2 404 #define W_L2TYPE__L2HDROFFSET 6 405 #define O_L2TYPE__L2PROTO 0 406 #define W_L2TYPE__L2PROTO 2 407 #define R_L2TYPE_1 0xF0 408 #define R_L2TYPE_2 0xF0 409 #define R_L2TYPE_3 0xF0 410 #define R_PARSERCONFIGREG 0x100 411 #define O_PARSERCONFIGREG__CRCHASHPOLY 8 412 #define W_PARSERCONFIGREG__CRCHASHPOLY 7 413 #define O_PARSERCONFIGREG__PREPADOFFSET 4 414 #define W_PARSERCONFIGREG__PREPADOFFSET 4 415 #define O_PARSERCONFIGREG__USECAM 2 416 #define O_PARSERCONFIGREG__USEHASH 1 417 #define O_PARSERCONFIGREG__USEPROTO 0 418 #define R_L3CTABLE 0x140 419 #define O_L3CTABLE__OFFSET0 25 420 #define W_L3CTABLE__OFFSET0 7 421 #define O_L3CTABLE__LEN0 21 422 #define W_L3CTABLE__LEN0 4 423 #define O_L3CTABLE__OFFSET1 14 424 #define W_L3CTABLE__OFFSET1 7 425 #define O_L3CTABLE__LEN1 10 426 #define W_L3CTABLE__LEN1 4 427 #define O_L3CTABLE__OFFSET2 4 428 #define W_L3CTABLE__OFFSET2 6 429 #define O_L3CTABLE__LEN2 0 430 #define W_L3CTABLE__LEN2 4 431 #define O_L3CTABLE__L3HDROFFSET 26 432 #define W_L3CTABLE__L3HDROFFSET 6 433 #define O_L3CTABLE__L4PROTOOFFSET 20 434 #define W_L3CTABLE__L4PROTOOFFSET 6 435 #define O_L3CTABLE__IPCHKSUMCOMPUTE 19 436 #define O_L3CTABLE__L4CLASSIFY 18 437 #define O_L3CTABLE__L2PROTO 16 438 #define W_L3CTABLE__L2PROTO 2 439 #define O_L3CTABLE__L3PROTOKEY 0 440 #define W_L3CTABLE__L3PROTOKEY 16 441 #define R_L4CTABLE 0x160 442 #define O_L4CTABLE__OFFSET0 21 443 #define W_L4CTABLE__OFFSET0 6 444 #define O_L4CTABLE__LEN0 17 445 #define W_L4CTABLE__LEN0 4 446 #define O_L4CTABLE__OFFSET1 11 447 #define W_L4CTABLE__OFFSET1 6 448 #define O_L4CTABLE__LEN1 7 449 #define W_L4CTABLE__LEN1 4 450 #define O_L4CTABLE__TCPCHKSUMENABLE 0 451 #define R_CAM4X128TABLE 0x172 452 #define O_CAM4X128TABLE__CLASSID 7 453 #define W_CAM4X128TABLE__CLASSID 2 454 #define O_CAM4X128TABLE__BUCKETID 1 455 #define W_CAM4X128TABLE__BUCKETID 6 456 #define O_CAM4X128TABLE__USEBUCKET 0 457 #define R_CAM4X128KEY 0x180 458 #define R_TRANSLATETABLE 0x1A0 459 #define R_DMACR0 0x200 460 #define O_DMACR0__DATA0WRMAXCR 27 461 #define W_DMACR0__DATA0WRMAXCR 3 462 #define O_DMACR0__DATA0RDMAXCR 24 463 #define W_DMACR0__DATA0RDMAXCR 3 464 #define O_DMACR0__DATA1WRMAXCR 21 465 #define W_DMACR0__DATA1WRMAXCR 3 466 #define O_DMACR0__DATA1RDMAXCR 18 467 #define W_DMACR0__DATA1RDMAXCR 3 468 #define O_DMACR0__DATA2WRMAXCR 15 469 #define W_DMACR0__DATA2WRMAXCR 3 470 #define O_DMACR0__DATA2RDMAXCR 12 471 #define W_DMACR0__DATA2RDMAXCR 3 472 #define O_DMACR0__DATA3WRMAXCR 9 473 #define W_DMACR0__DATA3WRMAXCR 3 474 #define O_DMACR0__DATA3RDMAXCR 6 475 #define W_DMACR0__DATA3RDMAXCR 3 476 #define O_DMACR0__DATA4WRMAXCR 3 477 #define W_DMACR0__DATA4WRMAXCR 3 478 #define O_DMACR0__DATA4RDMAXCR 0 479 #define W_DMACR0__DATA4RDMAXCR 3 480 #define R_DMACR1 0x201 481 #define O_DMACR1__DATA5WRMAXCR 27 482 #define W_DMACR1__DATA5WRMAXCR 3 483 #define O_DMACR1__DATA5RDMAXCR 24 484 #define W_DMACR1__DATA5RDMAXCR 3 485 #define O_DMACR1__DATA6WRMAXCR 21 486 #define W_DMACR1__DATA6WRMAXCR 3 487 #define O_DMACR1__DATA6RDMAXCR 18 488 #define W_DMACR1__DATA6RDMAXCR 3 489 #define O_DMACR1__DATA7WRMAXCR 15 490 #define W_DMACR1__DATA7WRMAXCR 3 491 #define O_DMACR1__DATA7RDMAXCR 12 492 #define W_DMACR1__DATA7RDMAXCR 3 493 #define O_DMACR1__DATA8WRMAXCR 9 494 #define W_DMACR1__DATA8WRMAXCR 3 495 #define O_DMACR1__DATA8RDMAXCR 6 496 #define W_DMACR1__DATA8RDMAXCR 3 497 #define O_DMACR1__DATA9WRMAXCR 3 498 #define W_DMACR1__DATA9WRMAXCR 3 499 #define O_DMACR1__DATA9RDMAXCR 0 500 #define W_DMACR1__DATA9RDMAXCR 3 501 #define R_DMACR2 0x202 502 #define O_DMACR2__DATA10WRMAXCR 27 503 #define W_DMACR2__DATA10WRMAXCR 3 504 #define O_DMACR2__DATA10RDMAXCR 24 505 #define W_DMACR2__DATA10RDMAXCR 3 506 #define O_DMACR2__DATA11WRMAXCR 21 507 #define W_DMACR2__DATA11WRMAXCR 3 508 #define O_DMACR2__DATA11RDMAXCR 18 509 #define W_DMACR2__DATA11RDMAXCR 3 510 #define O_DMACR2__DATA12WRMAXCR 15 511 #define W_DMACR2__DATA12WRMAXCR 3 512 #define O_DMACR2__DATA12RDMAXCR 12 513 #define W_DMACR2__DATA12RDMAXCR 3 514 #define O_DMACR2__DATA13WRMAXCR 9 515 #define W_DMACR2__DATA13WRMAXCR 3 516 #define O_DMACR2__DATA13RDMAXCR 6 517 #define W_DMACR2__DATA13RDMAXCR 3 518 #define O_DMACR2__DATA14WRMAXCR 3 519 #define W_DMACR2__DATA14WRMAXCR 3 520 #define O_DMACR2__DATA14RDMAXCR 0 521 #define W_DMACR2__DATA14RDMAXCR 3 522 #define R_DMACR3 0x203 523 #define O_DMACR3__DATA15WRMAXCR 27 524 #define W_DMACR3__DATA15WRMAXCR 3 525 #define O_DMACR3__DATA15RDMAXCR 24 526 #define W_DMACR3__DATA15RDMAXCR 3 527 #define O_DMACR3__SPCLASSWRMAXCR 21 528 #define W_DMACR3__SPCLASSWRMAXCR 3 529 #define O_DMACR3__SPCLASSRDMAXCR 18 530 #define W_DMACR3__SPCLASSRDMAXCR 3 531 #define O_DMACR3__JUMFRINWRMAXCR 15 532 #define W_DMACR3__JUMFRINWRMAXCR 3 533 #define O_DMACR3__JUMFRINRDMAXCR 12 534 #define W_DMACR3__JUMFRINRDMAXCR 3 535 #define O_DMACR3__REGFRINWRMAXCR 9 536 #define W_DMACR3__REGFRINWRMAXCR 3 537 #define O_DMACR3__REGFRINRDMAXCR 6 538 #define W_DMACR3__REGFRINRDMAXCR 3 539 #define O_DMACR3__FROUTWRMAXCR 3 540 #define W_DMACR3__FROUTWRMAXCR 3 541 #define O_DMACR3__FROUTRDMAXCR 0 542 #define W_DMACR3__FROUTRDMAXCR 3 543 #define R_REG_FRIN_SPILL_MEM_START_0 0x204 544 #define O_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 0 545 #define W_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 32 546 #define R_REG_FRIN_SPILL_MEM_START_1 0x205 547 #define O_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 0 548 #define W_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 3 549 #define R_REG_FRIN_SPILL_MEM_SIZE 0x206 550 #define O_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 0 551 #define W_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 32 552 #define R_FROUT_SPILL_MEM_START_0 0x207 553 #define O_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 0 554 #define W_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 32 555 #define R_FROUT_SPILL_MEM_START_1 0x208 556 #define O_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 0 557 #define W_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 3 558 #define R_FROUT_SPILL_MEM_SIZE 0x209 559 #define O_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 0 560 #define W_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 32 561 #define R_CLASS0_SPILL_MEM_START_0 0x20A 562 #define O_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 0 563 #define W_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 32 564 #define R_CLASS0_SPILL_MEM_START_1 0x20B 565 #define O_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 0 566 #define W_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 3 567 #define R_CLASS0_SPILL_MEM_SIZE 0x20C 568 #define O_CLASS0_SPILL_MEM_SIZE__CLASS0SPILLMEMSIZE 0 569 #define W_CLASS0_SPILL_MEM_SIZE__CLASS0SPILLMEMSIZE 32 570 #define R_JUMFRIN_SPILL_MEM_START_0 0x20D 571 #define O_JUMFRIN_SPILL_MEM_START_0__JUMFRINSPILLMEMSTART0 0 572 #define W_JUMFRIN_SPILL_MEM_START_0__JUMFRINSPILLMEMSTART0 32 573 #define R_JUMFRIN_SPILL_MEM_START_1 0x20E 574 #define O_JUMFRIN_SPILL_MEM_START_1__JUMFRINSPILLMEMSTART1 0 575 #define W_JUMFRIN_SPILL_MEM_START_1__JUMFRINSPILLMEMSTART1 3 576 #define R_JUMFRIN_SPILL_MEM_SIZE 0x20F 577 #define O_JUMFRIN_SPILL_MEM_SIZE__JUMFRINSPILLMEMSIZE 0 578 #define W_JUMFRIN_SPILL_MEM_SIZE__JUMFRINSPILLMEMSIZE 32 579 #define R_CLASS1_SPILL_MEM_START_0 0x210 580 #define O_CLASS1_SPILL_MEM_START_0__CLASS1SPILLMEMSTART0 0 581 #define W_CLASS1_SPILL_MEM_START_0__CLASS1SPILLMEMSTART0 32 582 #define R_CLASS1_SPILL_MEM_START_1 0x211 583 #define O_CLASS1_SPILL_MEM_START_1__CLASS1SPILLMEMSTART1 0 584 #define W_CLASS1_SPILL_MEM_START_1__CLASS1SPILLMEMSTART1 3 585 #define R_CLASS1_SPILL_MEM_SIZE 0x212 586 #define O_CLASS1_SPILL_MEM_SIZE__CLASS1SPILLMEMSIZE 0 587 #define W_CLASS1_SPILL_MEM_SIZE__CLASS1SPILLMEMSIZE 32 588 #define R_CLASS2_SPILL_MEM_START_0 0x213 589 #define O_CLASS2_SPILL_MEM_START_0__CLASS2SPILLMEMSTART0 0 590 #define W_CLASS2_SPILL_MEM_START_0__CLASS2SPILLMEMSTART0 32 591 #define R_CLASS2_SPILL_MEM_START_1 0x214 592 #define O_CLASS2_SPILL_MEM_START_1__CLASS2SPILLMEMSTART1 0 593 #define W_CLASS2_SPILL_MEM_START_1__CLASS2SPILLMEMSTART1 3 594 #define R_CLASS2_SPILL_MEM_SIZE 0x215 595 #define O_CLASS2_SPILL_MEM_SIZE__CLASS2SPILLMEMSIZE 0 596 #define W_CLASS2_SPILL_MEM_SIZE__CLASS2SPILLMEMSIZE 32 597 #define R_CLASS3_SPILL_MEM_START_0 0x216 598 #define O_CLASS3_SPILL_MEM_START_0__CLASS3SPILLMEMSTART0 0 599 #define W_CLASS3_SPILL_MEM_START_0__CLASS3SPILLMEMSTART0 32 600 #define R_CLASS3_SPILL_MEM_START_1 0x217 601 #define O_CLASS3_SPILL_MEM_START_1__CLASS3SPILLMEMSTART1 0 602 #define W_CLASS3_SPILL_MEM_START_1__CLASS3SPILLMEMSTART1 3 603 #define R_CLASS3_SPILL_MEM_SIZE 0x218 604 #define O_CLASS3_SPILL_MEM_SIZE__CLASS3SPILLMEMSIZE 0 605 #define W_CLASS3_SPILL_MEM_SIZE__CLASS3SPILLMEMSIZE 32 606 #define R_REG_FRIN1_SPILL_MEM_START_0 0x219 607 #define R_REG_FRIN1_SPILL_MEM_START_1 0x21a 608 #define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b 609 #define R_SPIHNGY0 0x219 610 #define O_SPIHNGY0__EG_HNGY_THRESH_0 24 611 #define W_SPIHNGY0__EG_HNGY_THRESH_0 7 612 #define O_SPIHNGY0__EG_HNGY_THRESH_1 16 613 #define W_SPIHNGY0__EG_HNGY_THRESH_1 7 614 #define O_SPIHNGY0__EG_HNGY_THRESH_2 8 615 #define W_SPIHNGY0__EG_HNGY_THRESH_2 7 616 #define O_SPIHNGY0__EG_HNGY_THRESH_3 0 617 #define W_SPIHNGY0__EG_HNGY_THRESH_3 7 618 #define R_SPIHNGY1 0x21A 619 #define O_SPIHNGY1__EG_HNGY_THRESH_4 24 620 #define W_SPIHNGY1__EG_HNGY_THRESH_4 7 621 #define O_SPIHNGY1__EG_HNGY_THRESH_5 16 622 #define W_SPIHNGY1__EG_HNGY_THRESH_5 7 623 #define O_SPIHNGY1__EG_HNGY_THRESH_6 8 624 #define W_SPIHNGY1__EG_HNGY_THRESH_6 7 625 #define O_SPIHNGY1__EG_HNGY_THRESH_7 0 626 #define W_SPIHNGY1__EG_HNGY_THRESH_7 7 627 #define R_SPIHNGY2 0x21B 628 #define O_SPIHNGY2__EG_HNGY_THRESH_8 24 629 #define W_SPIHNGY2__EG_HNGY_THRESH_8 7 630 #define O_SPIHNGY2__EG_HNGY_THRESH_9 16 631 #define W_SPIHNGY2__EG_HNGY_THRESH_9 7 632 #define O_SPIHNGY2__EG_HNGY_THRESH_10 8 633 #define W_SPIHNGY2__EG_HNGY_THRESH_10 7 634 #define O_SPIHNGY2__EG_HNGY_THRESH_11 0 635 #define W_SPIHNGY2__EG_HNGY_THRESH_11 7 636 #define R_SPIHNGY3 0x21C 637 #define O_SPIHNGY3__EG_HNGY_THRESH_12 24 638 #define W_SPIHNGY3__EG_HNGY_THRESH_12 7 639 #define O_SPIHNGY3__EG_HNGY_THRESH_13 16 640 #define W_SPIHNGY3__EG_HNGY_THRESH_13 7 641 #define O_SPIHNGY3__EG_HNGY_THRESH_14 8 642 #define W_SPIHNGY3__EG_HNGY_THRESH_14 7 643 #define O_SPIHNGY3__EG_HNGY_THRESH_15 0 644 #define W_SPIHNGY3__EG_HNGY_THRESH_15 7 645 #define R_SPISTRV0 0x21D 646 #define O_SPISTRV0__EG_STRV_THRESH_0 24 647 #define W_SPISTRV0__EG_STRV_THRESH_0 7 648 #define O_SPISTRV0__EG_STRV_THRESH_1 16 649 #define W_SPISTRV0__EG_STRV_THRESH_1 7 650 #define O_SPISTRV0__EG_STRV_THRESH_2 8 651 #define W_SPISTRV0__EG_STRV_THRESH_2 7 652 #define O_SPISTRV0__EG_STRV_THRESH_3 0 653 #define W_SPISTRV0__EG_STRV_THRESH_3 7 654 #define R_SPISTRV1 0x21E 655 #define O_SPISTRV1__EG_STRV_THRESH_4 24 656 #define W_SPISTRV1__EG_STRV_THRESH_4 7 657 #define O_SPISTRV1__EG_STRV_THRESH_5 16 658 #define W_SPISTRV1__EG_STRV_THRESH_5 7 659 #define O_SPISTRV1__EG_STRV_THRESH_6 8 660 #define W_SPISTRV1__EG_STRV_THRESH_6 7 661 #define O_SPISTRV1__EG_STRV_THRESH_7 0 662 #define W_SPISTRV1__EG_STRV_THRESH_7 7 663 #define R_SPISTRV2 0x21F 664 #define O_SPISTRV2__EG_STRV_THRESH_8 24 665 #define W_SPISTRV2__EG_STRV_THRESH_8 7 666 #define O_SPISTRV2__EG_STRV_THRESH_9 16 667 #define W_SPISTRV2__EG_STRV_THRESH_9 7 668 #define O_SPISTRV2__EG_STRV_THRESH_10 8 669 #define W_SPISTRV2__EG_STRV_THRESH_10 7 670 #define O_SPISTRV2__EG_STRV_THRESH_11 0 671 #define W_SPISTRV2__EG_STRV_THRESH_11 7 672 #define R_SPISTRV3 0x220 673 #define O_SPISTRV3__EG_STRV_THRESH_12 24 674 #define W_SPISTRV3__EG_STRV_THRESH_12 7 675 #define O_SPISTRV3__EG_STRV_THRESH_13 16 676 #define W_SPISTRV3__EG_STRV_THRESH_13 7 677 #define O_SPISTRV3__EG_STRV_THRESH_14 8 678 #define W_SPISTRV3__EG_STRV_THRESH_14 7 679 #define O_SPISTRV3__EG_STRV_THRESH_15 0 680 #define W_SPISTRV3__EG_STRV_THRESH_15 7 681 #define R_TXDATAFIFO0 0x221 682 #define O_TXDATAFIFO0__TX0DATAFIFOSTART 24 683 #define W_TXDATAFIFO0__TX0DATAFIFOSTART 7 684 #define O_TXDATAFIFO0__TX0DATAFIFOSIZE 16 685 #define W_TXDATAFIFO0__TX0DATAFIFOSIZE 7 686 #define O_TXDATAFIFO0__TX1DATAFIFOSTART 8 687 #define W_TXDATAFIFO0__TX1DATAFIFOSTART 7 688 #define O_TXDATAFIFO0__TX1DATAFIFOSIZE 0 689 #define W_TXDATAFIFO0__TX1DATAFIFOSIZE 7 690 #define R_TXDATAFIFO1 0x222 691 #define O_TXDATAFIFO1__TX2DATAFIFOSTART 24 692 #define W_TXDATAFIFO1__TX2DATAFIFOSTART 7 693 #define O_TXDATAFIFO1__TX2DATAFIFOSIZE 16 694 #define W_TXDATAFIFO1__TX2DATAFIFOSIZE 7 695 #define O_TXDATAFIFO1__TX3DATAFIFOSTART 8 696 #define W_TXDATAFIFO1__TX3DATAFIFOSTART 7 697 #define O_TXDATAFIFO1__TX3DATAFIFOSIZE 0 698 #define W_TXDATAFIFO1__TX3DATAFIFOSIZE 7 699 #define R_TXDATAFIFO2 0x223 700 #define O_TXDATAFIFO2__TX4DATAFIFOSTART 24 701 #define W_TXDATAFIFO2__TX4DATAFIFOSTART 7 702 #define O_TXDATAFIFO2__TX4DATAFIFOSIZE 16 703 #define W_TXDATAFIFO2__TX4DATAFIFOSIZE 7 704 #define O_TXDATAFIFO2__TX5DATAFIFOSTART 8 705 #define W_TXDATAFIFO2__TX5DATAFIFOSTART 7 706 #define O_TXDATAFIFO2__TX5DATAFIFOSIZE 0 707 #define W_TXDATAFIFO2__TX5DATAFIFOSIZE 7 708 #define R_TXDATAFIFO3 0x224 709 #define O_TXDATAFIFO3__TX6DATAFIFOSTART 24 710 #define W_TXDATAFIFO3__TX6DATAFIFOSTART 7 711 #define O_TXDATAFIFO3__TX6DATAFIFOSIZE 16 712 #define W_TXDATAFIFO3__TX6DATAFIFOSIZE 7 713 #define O_TXDATAFIFO3__TX7DATAFIFOSTART 8 714 #define W_TXDATAFIFO3__TX7DATAFIFOSTART 7 715 #define O_TXDATAFIFO3__TX7DATAFIFOSIZE 0 716 #define W_TXDATAFIFO3__TX7DATAFIFOSIZE 7 717 #define R_TXDATAFIFO4 0x225 718 #define O_TXDATAFIFO4__TX8DATAFIFOSTART 24 719 #define W_TXDATAFIFO4__TX8DATAFIFOSTART 7 720 #define O_TXDATAFIFO4__TX8DATAFIFOSIZE 16 721 #define W_TXDATAFIFO4__TX8DATAFIFOSIZE 7 722 #define O_TXDATAFIFO4__TX9DATAFIFOSTART 8 723 #define W_TXDATAFIFO4__TX9DATAFIFOSTART 7 724 #define O_TXDATAFIFO4__TX9DATAFIFOSIZE 0 725 #define W_TXDATAFIFO4__TX9DATAFIFOSIZE 7 726 #define R_TXDATAFIFO5 0x226 727 #define O_TXDATAFIFO5__TX10DATAFIFOSTART 24 728 #define W_TXDATAFIFO5__TX10DATAFIFOSTART 7 729 #define O_TXDATAFIFO5__TX10DATAFIFOSIZE 16 730 #define W_TXDATAFIFO5__TX10DATAFIFOSIZE 7 731 #define O_TXDATAFIFO5__TX11DATAFIFOSTART 8 732 #define W_TXDATAFIFO5__TX11DATAFIFOSTART 7 733 #define O_TXDATAFIFO5__TX11DATAFIFOSIZE 0 734 #define W_TXDATAFIFO5__TX11DATAFIFOSIZE 7 735 #define R_TXDATAFIFO6 0x227 736 #define O_TXDATAFIFO6__TX12DATAFIFOSTART 24 737 #define W_TXDATAFIFO6__TX12DATAFIFOSTART 7 738 #define O_TXDATAFIFO6__TX12DATAFIFOSIZE 16 739 #define W_TXDATAFIFO6__TX12DATAFIFOSIZE 7 740 #define O_TXDATAFIFO6__TX13DATAFIFOSTART 8 741 #define W_TXDATAFIFO6__TX13DATAFIFOSTART 7 742 #define O_TXDATAFIFO6__TX13DATAFIFOSIZE 0 743 #define W_TXDATAFIFO6__TX13DATAFIFOSIZE 7 744 #define R_TXDATAFIFO7 0x228 745 #define O_TXDATAFIFO7__TX14DATAFIFOSTART 24 746 #define W_TXDATAFIFO7__TX14DATAFIFOSTART 7 747 #define O_TXDATAFIFO7__TX14DATAFIFOSIZE 16 748 #define W_TXDATAFIFO7__TX14DATAFIFOSIZE 7 749 #define O_TXDATAFIFO7__TX15DATAFIFOSTART 8 750 #define W_TXDATAFIFO7__TX15DATAFIFOSTART 7 751 #define O_TXDATAFIFO7__TX15DATAFIFOSIZE 0 752 #define W_TXDATAFIFO7__TX15DATAFIFOSIZE 7 753 #define R_RXDATAFIFO0 0x229 754 #define O_RXDATAFIFO0__RX0DATAFIFOSTART 24 755 #define W_RXDATAFIFO0__RX0DATAFIFOSTART 7 756 #define O_RXDATAFIFO0__RX0DATAFIFOSIZE 16 757 #define W_RXDATAFIFO0__RX0DATAFIFOSIZE 7 758 #define O_RXDATAFIFO0__RX1DATAFIFOSTART 8 759 #define W_RXDATAFIFO0__RX1DATAFIFOSTART 7 760 #define O_RXDATAFIFO0__RX1DATAFIFOSIZE 0 761 #define W_RXDATAFIFO0__RX1DATAFIFOSIZE 7 762 #define R_RXDATAFIFO1 0x22A 763 #define O_RXDATAFIFO1__RX2DATAFIFOSTART 24 764 #define W_RXDATAFIFO1__RX2DATAFIFOSTART 7 765 #define O_RXDATAFIFO1__RX2DATAFIFOSIZE 16 766 #define W_RXDATAFIFO1__RX2DATAFIFOSIZE 7 767 #define O_RXDATAFIFO1__RX3DATAFIFOSTART 8 768 #define W_RXDATAFIFO1__RX3DATAFIFOSTART 7 769 #define O_RXDATAFIFO1__RX3DATAFIFOSIZE 0 770 #define W_RXDATAFIFO1__RX3DATAFIFOSIZE 7 771 #define R_RXDATAFIFO2 0x22B 772 #define O_RXDATAFIFO2__RX4DATAFIFOSTART 24 773 #define W_RXDATAFIFO2__RX4DATAFIFOSTART 7 774 #define O_RXDATAFIFO2__RX4DATAFIFOSIZE 16 775 #define W_RXDATAFIFO2__RX4DATAFIFOSIZE 7 776 #define O_RXDATAFIFO2__RX5DATAFIFOSTART 8 777 #define W_RXDATAFIFO2__RX5DATAFIFOSTART 7 778 #define O_RXDATAFIFO2__RX5DATAFIFOSIZE 0 779 #define W_RXDATAFIFO2__RX5DATAFIFOSIZE 7 780 #define R_RXDATAFIFO3 0x22C 781 #define O_RXDATAFIFO3__RX6DATAFIFOSTART 24 782 #define W_RXDATAFIFO3__RX6DATAFIFOSTART 7 783 #define O_RXDATAFIFO3__RX6DATAFIFOSIZE 16 784 #define W_RXDATAFIFO3__RX6DATAFIFOSIZE 7 785 #define O_RXDATAFIFO3__RX7DATAFIFOSTART 8 786 #define W_RXDATAFIFO3__RX7DATAFIFOSTART 7 787 #define O_RXDATAFIFO3__RX7DATAFIFOSIZE 0 788 #define W_RXDATAFIFO3__RX7DATAFIFOSIZE 7 789 #define R_RXDATAFIFO4 0x22D 790 #define O_RXDATAFIFO4__RX8DATAFIFOSTART 24 791 #define W_RXDATAFIFO4__RX8DATAFIFOSTART 7 792 #define O_RXDATAFIFO4__RX8DATAFIFOSIZE 16 793 #define W_RXDATAFIFO4__RX8DATAFIFOSIZE 7 794 #define O_RXDATAFIFO4__RX9DATAFIFOSTART 8 795 #define W_RXDATAFIFO4__RX9DATAFIFOSTART 7 796 #define O_RXDATAFIFO4__RX9DATAFIFOSIZE 0 797 #define W_RXDATAFIFO4__RX9DATAFIFOSIZE 7 798 #define R_RXDATAFIFO5 0x22E 799 #define O_RXDATAFIFO5__RX10DATAFIFOSTART 24 800 #define W_RXDATAFIFO5__RX10DATAFIFOSTART 7 801 #define O_RXDATAFIFO5__RX10DATAFIFOSIZE 16 802 #define W_RXDATAFIFO5__RX10DATAFIFOSIZE 7 803 #define O_RXDATAFIFO5__RX11DATAFIFOSTART 8 804 #define W_RXDATAFIFO5__RX11DATAFIFOSTART 7 805 #define O_RXDATAFIFO5__RX11DATAFIFOSIZE 0 806 #define W_RXDATAFIFO5__RX11DATAFIFOSIZE 7 807 #define R_RXDATAFIFO6 0x22F 808 #define O_RXDATAFIFO6__RX12DATAFIFOSTART 24 809 #define W_RXDATAFIFO6__RX12DATAFIFOSTART 7 810 #define O_RXDATAFIFO6__RX12DATAFIFOSIZE 16 811 #define W_RXDATAFIFO6__RX12DATAFIFOSIZE 7 812 #define O_RXDATAFIFO6__RX13DATAFIFOSTART 8 813 #define W_RXDATAFIFO6__RX13DATAFIFOSTART 7 814 #define O_RXDATAFIFO6__RX13DATAFIFOSIZE 0 815 #define W_RXDATAFIFO6__RX13DATAFIFOSIZE 7 816 #define R_RXDATAFIFO7 0x230 817 #define O_RXDATAFIFO7__RX14DATAFIFOSTART 24 818 #define W_RXDATAFIFO7__RX14DATAFIFOSTART 7 819 #define O_RXDATAFIFO7__RX14DATAFIFOSIZE 16 820 #define W_RXDATAFIFO7__RX14DATAFIFOSIZE 7 821 #define O_RXDATAFIFO7__RX15DATAFIFOSTART 8 822 #define W_RXDATAFIFO7__RX15DATAFIFOSTART 7 823 #define O_RXDATAFIFO7__RX15DATAFIFOSIZE 0 824 #define W_RXDATAFIFO7__RX15DATAFIFOSIZE 7 825 #define R_XGMACPADCALIBRATION 0x231 826 #define R_FREEQCARVE 0x233 827 #define R_SPI4STATICDELAY0 0x240 828 #define O_SPI4STATICDELAY0__DATALINE7 28 829 #define W_SPI4STATICDELAY0__DATALINE7 4 830 #define O_SPI4STATICDELAY0__DATALINE6 24 831 #define W_SPI4STATICDELAY0__DATALINE6 4 832 #define O_SPI4STATICDELAY0__DATALINE5 20 833 #define W_SPI4STATICDELAY0__DATALINE5 4 834 #define O_SPI4STATICDELAY0__DATALINE4 16 835 #define W_SPI4STATICDELAY0__DATALINE4 4 836 #define O_SPI4STATICDELAY0__DATALINE3 12 837 #define W_SPI4STATICDELAY0__DATALINE3 4 838 #define O_SPI4STATICDELAY0__DATALINE2 8 839 #define W_SPI4STATICDELAY0__DATALINE2 4 840 #define O_SPI4STATICDELAY0__DATALINE1 4 841 #define W_SPI4STATICDELAY0__DATALINE1 4 842 #define O_SPI4STATICDELAY0__DATALINE0 0 843 #define W_SPI4STATICDELAY0__DATALINE0 4 844 #define R_SPI4STATICDELAY1 0x241 845 #define O_SPI4STATICDELAY1__DATALINE15 28 846 #define W_SPI4STATICDELAY1__DATALINE15 4 847 #define O_SPI4STATICDELAY1__DATALINE14 24 848 #define W_SPI4STATICDELAY1__DATALINE14 4 849 #define O_SPI4STATICDELAY1__DATALINE13 20 850 #define W_SPI4STATICDELAY1__DATALINE13 4 851 #define O_SPI4STATICDELAY1__DATALINE12 16 852 #define W_SPI4STATICDELAY1__DATALINE12 4 853 #define O_SPI4STATICDELAY1__DATALINE11 12 854 #define W_SPI4STATICDELAY1__DATALINE11 4 855 #define O_SPI4STATICDELAY1__DATALINE10 8 856 #define W_SPI4STATICDELAY1__DATALINE10 4 857 #define O_SPI4STATICDELAY1__DATALINE9 4 858 #define W_SPI4STATICDELAY1__DATALINE9 4 859 #define O_SPI4STATICDELAY1__DATALINE8 0 860 #define W_SPI4STATICDELAY1__DATALINE8 4 861 #define R_SPI4STATICDELAY2 0x242 862 #define O_SPI4STATICDELAY0__TXSTAT1 8 863 #define W_SPI4STATICDELAY0__TXSTAT1 4 864 #define O_SPI4STATICDELAY0__TXSTAT0 4 865 #define W_SPI4STATICDELAY0__TXSTAT0 4 866 #define O_SPI4STATICDELAY0__RXCONTROL 0 867 #define W_SPI4STATICDELAY0__RXCONTROL 4 868 #define R_SPI4CONTROL 0x243 869 #define O_SPI4CONTROL__STATICDELAY 2 870 #define O_SPI4CONTROL__LVDS_LVTTL 1 871 #define O_SPI4CONTROL__SPI4ENABLE 0 872 #define R_CLASSWATERMARKS 0x244 873 #define O_CLASSWATERMARKS__CLASS0WATERMARK 24 874 #define W_CLASSWATERMARKS__CLASS0WATERMARK 5 875 #define O_CLASSWATERMARKS__CLASS1WATERMARK 16 876 #define W_CLASSWATERMARKS__CLASS1WATERMARK 5 877 #define O_CLASSWATERMARKS__CLASS3WATERMARK 0 878 #define W_CLASSWATERMARKS__CLASS3WATERMARK 5 879 #define R_RXWATERMARKS1 0x245 880 #define O_RXWATERMARKS__RX0DATAWATERMARK 24 881 #define W_RXWATERMARKS__RX0DATAWATERMARK 7 882 #define O_RXWATERMARKS__RX1DATAWATERMARK 16 883 #define W_RXWATERMARKS__RX1DATAWATERMARK 7 884 #define O_RXWATERMARKS__RX3DATAWATERMARK 0 885 #define W_RXWATERMARKS__RX3DATAWATERMARK 7 886 #define R_RXWATERMARKS2 0x246 887 #define O_RXWATERMARKS__RX4DATAWATERMARK 24 888 #define W_RXWATERMARKS__RX4DATAWATERMARK 7 889 #define O_RXWATERMARKS__RX5DATAWATERMARK 16 890 #define W_RXWATERMARKS__RX5DATAWATERMARK 7 891 #define O_RXWATERMARKS__RX6DATAWATERMARK 8 892 #define W_RXWATERMARKS__RX6DATAWATERMARK 7 893 #define O_RXWATERMARKS__RX7DATAWATERMARK 0 894 #define W_RXWATERMARKS__RX7DATAWATERMARK 7 895 #define R_RXWATERMARKS3 0x247 896 #define O_RXWATERMARKS__RX8DATAWATERMARK 24 897 #define W_RXWATERMARKS__RX8DATAWATERMARK 7 898 #define O_RXWATERMARKS__RX9DATAWATERMARK 16 899 #define W_RXWATERMARKS__RX9DATAWATERMARK 7 900 #define O_RXWATERMARKS__RX10DATAWATERMARK 8 901 #define W_RXWATERMARKS__RX10DATAWATERMARK 7 902 #define O_RXWATERMARKS__RX11DATAWATERMARK 0 903 #define W_RXWATERMARKS__RX11DATAWATERMARK 7 904 #define R_RXWATERMARKS4 0x248 905 #define O_RXWATERMARKS__RX12DATAWATERMARK 24 906 #define W_RXWATERMARKS__RX12DATAWATERMARK 7 907 #define O_RXWATERMARKS__RX13DATAWATERMARK 16 908 #define W_RXWATERMARKS__RX13DATAWATERMARK 7 909 #define O_RXWATERMARKS__RX14DATAWATERMARK 8 910 #define W_RXWATERMARKS__RX14DATAWATERMARK 7 911 #define O_RXWATERMARKS__RX15DATAWATERMARK 0 912 #define W_RXWATERMARKS__RX15DATAWATERMARK 7 913 #define R_FREEWATERMARKS 0x249 914 #define O_FREEWATERMARKS__FREEOUTWATERMARK 16 915 #define W_FREEWATERMARKS__FREEOUTWATERMARK 16 916 #define O_FREEWATERMARKS__JUMFRWATERMARK 8 917 #define W_FREEWATERMARKS__JUMFRWATERMARK 7 918 #define O_FREEWATERMARKS__REGFRWATERMARK 0 919 #define W_FREEWATERMARKS__REGFRWATERMARK 7 920 #define R_EGRESSFIFOCARVINGSLOTS 0x24a 921 922 #define CTRL_RES0 0 923 #define CTRL_RES1 1 924 #define CTRL_REG_FREE 2 925 #define CTRL_JUMBO_FREE 3 926 #define CTRL_CONT 4 927 #define CTRL_EOP 5 928 #define CTRL_START 6 929 #define CTRL_SNGL 7 930 931 #define CTRL_B0_NOT_EOP 0 932 #define CTRL_B0_EOP 1 933 934 #define R_ROUND_ROBIN_TABLE 0 935 #define R_PDE_CLASS_0 0x300 936 #define R_PDE_CLASS_1 0x302 937 #define R_PDE_CLASS_2 0x304 938 #define R_PDE_CLASS_3 0x306 939 940 #define R_MSG_TX_THRESHOLD 0x308 941 942 #define R_GMAC_JFR0_BUCKET_SIZE 0x320 943 #define R_GMAC_RFR0_BUCKET_SIZE 0x321 944 #define R_GMAC_TX0_BUCKET_SIZE 0x322 945 #define R_GMAC_TX1_BUCKET_SIZE 0x323 946 #define R_GMAC_TX2_BUCKET_SIZE 0x324 947 #define R_GMAC_TX3_BUCKET_SIZE 0x325 948 #define R_GMAC_JFR1_BUCKET_SIZE 0x326 949 #define R_GMAC_RFR1_BUCKET_SIZE 0x327 950 951 #define R_XGS_TX0_BUCKET_SIZE 0x320 952 #define R_XGS_TX1_BUCKET_SIZE 0x321 953 #define R_XGS_TX2_BUCKET_SIZE 0x322 954 #define R_XGS_TX3_BUCKET_SIZE 0x323 955 #define R_XGS_TX4_BUCKET_SIZE 0x324 956 #define R_XGS_TX5_BUCKET_SIZE 0x325 957 #define R_XGS_TX6_BUCKET_SIZE 0x326 958 #define R_XGS_TX7_BUCKET_SIZE 0x327 959 #define R_XGS_TX8_BUCKET_SIZE 0x328 960 #define R_XGS_TX9_BUCKET_SIZE 0x329 961 #define R_XGS_TX10_BUCKET_SIZE 0x32A 962 #define R_XGS_TX11_BUCKET_SIZE 0x32B 963 #define R_XGS_TX12_BUCKET_SIZE 0x32C 964 #define R_XGS_TX13_BUCKET_SIZE 0x32D 965 #define R_XGS_TX14_BUCKET_SIZE 0x32E 966 #define R_XGS_TX15_BUCKET_SIZE 0x32F 967 #define R_XGS_JFR_BUCKET_SIZE 0x330 968 #define R_XGS_RFR_BUCKET_SIZE 0x331 969 970 #define R_CC_CPU0_0 0x380 971 #define R_CC_CPU1_0 0x388 972 #define R_CC_CPU2_0 0x390 973 #define R_CC_CPU3_0 0x398 974 #define R_CC_CPU4_0 0x3a0 975 #define R_CC_CPU5_0 0x3a8 976 #define R_CC_CPU6_0 0x3b0 977 #define R_CC_CPU7_0 0x3b8 978 979 #define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ 980 XLR_IO_GMAC_0_OFFSET) 981 982 /* Constants used for configuring the devices */ 983 984 #define XLR_FB_STN 6 /* Bucket used for Tx freeback */ 985 986 #define MAC_B2B_IPG 88 987 988 #define XLR_NET_PREPAD_LEN 32 989 990 /* frame sizes need to be cacheline aligned */ 991 #define MAX_FRAME_SIZE (1536 + XLR_NET_PREPAD_LEN) 992 #define MAX_FRAME_SIZE_JUMBO 9216 993 994 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES 995 #define MAC_PREPAD 0 996 #define BYTE_OFFSET 2 997 #define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ 998 MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) 999 #define MAC_CRC_LEN 4 1000 #define MAX_NUM_MSGRNG_STN_CC 128 1001 #define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + 1002 * headroom 1003 */ 1004 1005 #define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 1006 1007 #define MAX_NUM_DESC_SPILL 1024 1008 #define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) 1009 #define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) 1010 #define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) 1011 #define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) 1012 #define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) 1013 #define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) 1014 1015 enum { 1016 SGMII_SPEED_10 = 0x00000000, 1017 SGMII_SPEED_100 = 0x02000000, 1018 SGMII_SPEED_1000 = 0x04000000, 1019 }; 1020 1021 enum tsv_rsv_reg { 1022 TX_RX_64_BYTE_FRAME = 0x20, 1023 TX_RX_64_127_BYTE_FRAME, 1024 TX_RX_128_255_BYTE_FRAME, 1025 TX_RX_256_511_BYTE_FRAME, 1026 TX_RX_512_1023_BYTE_FRAME, 1027 TX_RX_1024_1518_BYTE_FRAME, 1028 TX_RX_1519_1522_VLAN_BYTE_FRAME, 1029 1030 RX_BYTE_COUNTER = 0x27, 1031 RX_PACKET_COUNTER, 1032 RX_FCS_ERROR_COUNTER, 1033 RX_MULTICAST_PACKET_COUNTER, 1034 RX_BROADCAST_PACKET_COUNTER, 1035 RX_CONTROL_FRAME_PACKET_COUNTER, 1036 RX_PAUSE_FRAME_PACKET_COUNTER, 1037 RX_UNKNOWN_OP_CODE_COUNTER, 1038 RX_ALIGNMENT_ERROR_COUNTER, 1039 RX_FRAME_LENGTH_ERROR_COUNTER, 1040 RX_CODE_ERROR_COUNTER, 1041 RX_CARRIER_SENSE_ERROR_COUNTER, 1042 RX_UNDERSIZE_PACKET_COUNTER, 1043 RX_OVERSIZE_PACKET_COUNTER, 1044 RX_FRAGMENTS_COUNTER, 1045 RX_JABBER_COUNTER, 1046 RX_DROP_PACKET_COUNTER, 1047 1048 TX_BYTE_COUNTER = 0x38, 1049 TX_PACKET_COUNTER, 1050 TX_MULTICAST_PACKET_COUNTER, 1051 TX_BROADCAST_PACKET_COUNTER, 1052 TX_PAUSE_CONTROL_FRAME_COUNTER, 1053 TX_DEFERRAL_PACKET_COUNTER, 1054 TX_EXCESSIVE_DEFERRAL_PACKET_COUNTER, 1055 TX_SINGLE_COLLISION_PACKET_COUNTER, 1056 TX_MULTI_COLLISION_PACKET_COUNTER, 1057 TX_LATE_COLLISION_PACKET_COUNTER, 1058 TX_EXCESSIVE_COLLISION_PACKET_COUNTER, 1059 TX_TOTAL_COLLISION_COUNTER, 1060 TX_PAUSE_FRAME_HONERED_COUNTER, 1061 TX_DROP_FRAME_COUNTER, 1062 TX_JABBER_FRAME_COUNTER, 1063 TX_FCS_ERROR_COUNTER, 1064 TX_CONTROL_FRAME_COUNTER, 1065 TX_OVERSIZE_FRAME_COUNTER, 1066 TX_UNDERSIZE_FRAME_COUNTER, 1067 TX_FRAGMENT_FRAME_COUNTER, 1068 1069 CARRY_REG_1 = 0x4c, 1070 CARRY_REG_2 = 0x4d, 1071 }; 1072 1073 struct xlr_adapter { 1074 struct net_device *netdev[4]; 1075 }; 1076 1077 struct xlr_net_priv { 1078 u32 __iomem *base_addr; 1079 struct net_device *ndev; 1080 struct xlr_adapter *adapter; 1081 struct mii_bus *mii_bus; 1082 int num_rx_desc; 1083 int phy_addr; /* PHY addr on MDIO bus */ 1084 int pcs_id; /* PCS id on MDIO bus */ 1085 int port_id; /* Port(gmac/xgmac) number, i.e 0-7 */ 1086 int tx_stnid; 1087 u32 __iomem *mii_addr; 1088 u32 __iomem *serdes_addr; 1089 u32 __iomem *pcs_addr; 1090 u32 __iomem *gpio_addr; 1091 int phy_speed; 1092 int port_type; 1093 struct timer_list queue_timer; 1094 int wakeup_q; 1095 struct platform_device *pdev; 1096 struct xlr_net_data *nd; 1097 1098 u64 *frin_spill; 1099 u64 *frout_spill; 1100 u64 *class_0_spill; 1101 u64 *class_1_spill; 1102 u64 *class_2_spill; 1103 u64 *class_3_spill; 1104 }; 1105 1106 void xlr_set_gmac_speed(struct xlr_net_priv *priv); 1107