1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef REG_ADDR_H 10 #define REG_ADDR_H 11 12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 13 0 14 15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 16 0xfff << 0) 17 18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 19 12 20 21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 22 0xfff << 12) 23 24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 25 24 26 27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 28 0xff << 24) 29 30 #define CDU_REG_SEGMENT0_PARAMS \ 31 0x580904UL 32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 33 (0xfff << 0) 34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 35 0 36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 37 (0xff << 16) 38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 39 16 40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 41 (0xff << 24) 42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 43 24 44 #define CDU_REG_SEGMENT1_PARAMS \ 45 0x580908UL 46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 47 (0xfff << 0) 48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 49 0 50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 51 (0xff << 16) 52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 53 16 54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 55 (0xff << 24) 56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 57 24 58 59 #define XSDM_REG_OPERATION_GEN \ 60 0xf80408UL 61 #define NIG_REG_RX_BRB_OUT_EN \ 62 0x500e18UL 63 #define NIG_REG_STORM_OUT_EN \ 64 0x500e08UL 65 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 66 0x240c50UL 67 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 68 0x2aae04UL 69 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 70 0x2aa16cUL 71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 72 0x2aa118UL 73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \ 74 0x2a0800UL 75 #define BAR0_MAP_REG_MSDM_RAM \ 76 0x1d00000UL 77 #define BAR0_MAP_REG_USDM_RAM \ 78 0x1d80000UL 79 #define BAR0_MAP_REG_PSDM_RAM \ 80 0x1f00000UL 81 #define BAR0_MAP_REG_TSDM_RAM \ 82 0x1c80000UL 83 #define BAR0_MAP_REG_XSDM_RAM \ 84 0x1e00000UL 85 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 86 0x5011f4UL 87 #define PRS_REG_SEARCH_TCP \ 88 0x1f0400UL 89 #define PRS_REG_SEARCH_UDP \ 90 0x1f0404UL 91 #define PRS_REG_SEARCH_FCOE \ 92 0x1f0408UL 93 #define PRS_REG_SEARCH_ROCE \ 94 0x1f040cUL 95 #define PRS_REG_SEARCH_OPENFLOW \ 96 0x1f0434UL 97 #define TM_REG_PF_ENABLE_CONN \ 98 0x2c043cUL 99 #define TM_REG_PF_ENABLE_TASK \ 100 0x2c0444UL 101 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 102 0x2c04fcUL 103 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 104 0x2c0500UL 105 #define IGU_REG_LEADING_EDGE_LATCH \ 106 0x18082cUL 107 #define IGU_REG_TRAILING_EDGE_LATCH \ 108 0x180830UL 109 #define QM_REG_USG_CNT_PF_TX \ 110 0x2f2eacUL 111 #define QM_REG_USG_CNT_PF_OTHER \ 112 0x2f2eb0UL 113 #define DORQ_REG_PF_DB_ENABLE \ 114 0x100508UL 115 #define DORQ_REG_VF_USAGE_CNT \ 116 0x1009c4UL 117 #define QM_REG_PF_EN \ 118 0x2f2ea4UL 119 #define TCFC_REG_WEAK_ENABLE_VF \ 120 0x2d0704UL 121 #define TCFC_REG_STRONG_ENABLE_PF \ 122 0x2d0708UL 123 #define TCFC_REG_STRONG_ENABLE_VF \ 124 0x2d070cUL 125 #define CCFC_REG_WEAK_ENABLE_VF \ 126 0x2e0704UL 127 #define CCFC_REG_STRONG_ENABLE_PF \ 128 0x2e0708UL 129 #define PGLUE_B_REG_PGL_ADDR_88_F0 \ 130 0x2aa404UL 131 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \ 132 0x2aa408UL 133 #define PGLUE_B_REG_PGL_ADDR_90_F0 \ 134 0x2aa40cUL 135 #define PGLUE_B_REG_PGL_ADDR_94_F0 \ 136 0x2aa410UL 137 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 138 0x2aa138UL 139 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 140 0x2aa174UL 141 #define MISC_REG_GEN_PURP_CR0 \ 142 0x008c80UL 143 #define MCP_REG_SCRATCH \ 144 0xe20000UL 145 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 146 0x218200UL 147 #define MISCS_REG_CHIP_NUM \ 148 0x00976cUL 149 #define MISCS_REG_CHIP_REV \ 150 0x009770UL 151 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 152 0x00971cUL 153 #define MISCS_REG_CHIP_TEST_REG \ 154 0x009778UL 155 #define MISCS_REG_CHIP_METAL \ 156 0x009774UL 157 #define MISCS_REG_FUNCTION_HIDE \ 158 0x0096f0UL 159 #define BRB_REG_HEADER_SIZE \ 160 0x340804UL 161 #define BTB_REG_HEADER_SIZE \ 162 0xdb0804UL 163 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 164 0x1c0708UL 165 #define CCFC_REG_ACTIVITY_COUNTER \ 166 0x2e8800UL 167 #define CCFC_REG_STRONG_ENABLE_VF \ 168 0x2e070cUL 169 #define CDU_REG_CID_ADDR_PARAMS \ 170 0x580900UL 171 #define DBG_REG_CLIENT_ENABLE \ 172 0x010004UL 173 #define DMAE_REG_INIT \ 174 0x00c000UL 175 #define DORQ_REG_IFEN \ 176 0x100040UL 177 #define DORQ_REG_DB_DROP_REASON \ 178 0x100a2cUL 179 #define DORQ_REG_DB_DROP_DETAILS \ 180 0x100a24UL 181 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 182 0x100a1cUL 183 #define GRC_REG_TIMEOUT_EN \ 184 0x050404UL 185 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 186 0x050054UL 187 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 188 0x05004cUL 189 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 190 0x050050UL 191 #define IGU_REG_BLOCK_CONFIGURATION \ 192 0x180040UL 193 #define MCM_REG_INIT \ 194 0x1200000UL 195 #define MCP2_REG_DBG_DWORD_ENABLE \ 196 0x052404UL 197 #define MISC_REG_PORT_MODE \ 198 0x008c00UL 199 #define MISCS_REG_CLK_100G_MODE \ 200 0x009070UL 201 #define MSDM_REG_ENABLE_IN1 \ 202 0xfc0004UL 203 #define MSEM_REG_ENABLE_IN \ 204 0x1800004UL 205 #define NIG_REG_CM_HDR \ 206 0x500840UL 207 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 208 0x50196cUL 209 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 210 0x501964UL 211 #define NIG_REG_LLH_FUNC_FILTER_VALUE \ 212 0x501a00UL 213 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 214 32 215 #define NIG_REG_LLH_FUNC_FILTER_EN \ 216 0x501a80UL 217 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 218 16 219 #define NIG_REG_LLH_FUNC_FILTER_MODE \ 220 0x501ac0UL 221 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 222 16 223 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 224 0x501b00UL 225 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 226 16 227 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 228 0x501b40UL 229 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 230 16 231 #define NCSI_REG_CONFIG \ 232 0x040200UL 233 #define PBF_REG_INIT \ 234 0xd80000UL 235 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 236 0xd806c8UL 237 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 238 0xd806ccUL 239 #define PTU_REG_ATC_INIT_ARRAY \ 240 0x560000UL 241 #define PCM_REG_INIT \ 242 0x1100000UL 243 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 244 0x2a9000UL 245 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 246 0x2aa150UL 247 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 248 0x2aa144UL 249 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 250 0x2aa148UL 251 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 252 0x2aa14cUL 253 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 254 0x2aa154UL 255 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 256 0x2aa158UL 257 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 258 0x2aa15cUL 259 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 260 0x2aa160UL 261 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 262 0x2aa164UL 263 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 264 0x2aa54cUL 265 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 266 0x2aa544UL 267 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 268 0x2aa548UL 269 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 270 0x2aae74UL 271 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 272 0x2aae78UL 273 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 274 0x2aae7cUL 275 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 276 0x2aae80UL 277 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 278 0x2aa3bcUL 279 #define PRM_REG_DISABLE_PRM \ 280 0x230000UL 281 #define PRS_REG_SOFT_RST \ 282 0x1f0000UL 283 #define PRS_REG_MSG_INFO \ 284 0x1f0a1cUL 285 #define PRS_REG_ROCE_DEST_QP_MAX_PF \ 286 0x1f0430UL 287 #define PRS_REG_USE_LIGHT_L2 \ 288 0x1f096cUL 289 #define PSDM_REG_ENABLE_IN1 \ 290 0xfa0004UL 291 #define PSEM_REG_ENABLE_IN \ 292 0x1600004UL 293 #define PSWRQ_REG_DBG_SELECT \ 294 0x280020UL 295 #define PSWRQ2_REG_CDUT_P_SIZE \ 296 0x24000cUL 297 #define PSWRQ2_REG_ILT_MEMORY \ 298 0x260000UL 299 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 300 0x2a0040UL 301 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 302 0x29e050UL 303 #define PSWHST_REG_INCORRECT_ACCESS_VALID \ 304 0x2a0070UL 305 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 306 0x2a0074UL 307 #define PSWHST_REG_INCORRECT_ACCESS_DATA \ 308 0x2a0068UL 309 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 310 0x2a006cUL 311 #define PSWRD_REG_DBG_SELECT \ 312 0x29c040UL 313 #define PSWRD2_REG_CONF11 \ 314 0x29d064UL 315 #define PSWWR_REG_USDM_FULL_TH \ 316 0x29a040UL 317 #define PSWWR2_REG_CDU_FULL_TH2 \ 318 0x29b040UL 319 #define QM_REG_MAXPQSIZE_0 \ 320 0x2f0434UL 321 #define RSS_REG_RSS_INIT_EN \ 322 0x238804UL 323 #define RDIF_REG_STOP_ON_ERROR \ 324 0x300040UL 325 #define SRC_REG_SOFT_RST \ 326 0x23874cUL 327 #define TCFC_REG_ACTIVITY_COUNTER \ 328 0x2d8800UL 329 #define TCM_REG_INIT \ 330 0x1180000UL 331 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 332 0x2c0014UL 333 #define TSDM_REG_ENABLE_IN1 \ 334 0xfb0004UL 335 #define TSEM_REG_ENABLE_IN \ 336 0x1700004UL 337 #define TDIF_REG_STOP_ON_ERROR \ 338 0x310040UL 339 #define UCM_REG_INIT \ 340 0x1280000UL 341 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 342 0x051004UL 343 #define USDM_REG_ENABLE_IN1 \ 344 0xfd0004UL 345 #define USEM_REG_ENABLE_IN \ 346 0x1900004UL 347 #define XCM_REG_INIT \ 348 0x1000000UL 349 #define XSDM_REG_ENABLE_IN1 \ 350 0xf80004UL 351 #define XSEM_REG_ENABLE_IN \ 352 0x1400004UL 353 #define YCM_REG_INIT \ 354 0x1080000UL 355 #define YSDM_REG_ENABLE_IN1 \ 356 0xf90004UL 357 #define YSEM_REG_ENABLE_IN \ 358 0x1500004UL 359 #define XYLD_REG_SCBD_STRICT_PRIO \ 360 0x4c0000UL 361 #define TMLD_REG_SCBD_STRICT_PRIO \ 362 0x4d0000UL 363 #define MULD_REG_SCBD_STRICT_PRIO \ 364 0x4e0000UL 365 #define YULD_REG_SCBD_STRICT_PRIO \ 366 0x4c8000UL 367 #define MISC_REG_SHARED_MEM_ADDR \ 368 0x008c20UL 369 #define DMAE_REG_GO_C0 \ 370 0x00c048UL 371 #define DMAE_REG_GO_C1 \ 372 0x00c04cUL 373 #define DMAE_REG_GO_C2 \ 374 0x00c050UL 375 #define DMAE_REG_GO_C3 \ 376 0x00c054UL 377 #define DMAE_REG_GO_C4 \ 378 0x00c058UL 379 #define DMAE_REG_GO_C5 \ 380 0x00c05cUL 381 #define DMAE_REG_GO_C6 \ 382 0x00c060UL 383 #define DMAE_REG_GO_C7 \ 384 0x00c064UL 385 #define DMAE_REG_GO_C8 \ 386 0x00c068UL 387 #define DMAE_REG_GO_C9 \ 388 0x00c06cUL 389 #define DMAE_REG_GO_C10 \ 390 0x00c070UL 391 #define DMAE_REG_GO_C11 \ 392 0x00c074UL 393 #define DMAE_REG_GO_C12 \ 394 0x00c078UL 395 #define DMAE_REG_GO_C13 \ 396 0x00c07cUL 397 #define DMAE_REG_GO_C14 \ 398 0x00c080UL 399 #define DMAE_REG_GO_C15 \ 400 0x00c084UL 401 #define DMAE_REG_GO_C16 \ 402 0x00c088UL 403 #define DMAE_REG_GO_C17 \ 404 0x00c08cUL 405 #define DMAE_REG_GO_C18 \ 406 0x00c090UL 407 #define DMAE_REG_GO_C19 \ 408 0x00c094UL 409 #define DMAE_REG_GO_C20 \ 410 0x00c098UL 411 #define DMAE_REG_GO_C21 \ 412 0x00c09cUL 413 #define DMAE_REG_GO_C22 \ 414 0x00c0a0UL 415 #define DMAE_REG_GO_C23 \ 416 0x00c0a4UL 417 #define DMAE_REG_GO_C24 \ 418 0x00c0a8UL 419 #define DMAE_REG_GO_C25 \ 420 0x00c0acUL 421 #define DMAE_REG_GO_C26 \ 422 0x00c0b0UL 423 #define DMAE_REG_GO_C27 \ 424 0x00c0b4UL 425 #define DMAE_REG_GO_C28 \ 426 0x00c0b8UL 427 #define DMAE_REG_GO_C29 \ 428 0x00c0bcUL 429 #define DMAE_REG_GO_C30 \ 430 0x00c0c0UL 431 #define DMAE_REG_GO_C31 \ 432 0x00c0c4UL 433 #define DMAE_REG_CMD_MEM \ 434 0x00c800UL 435 #define QM_REG_MAXPQSIZETXSEL_0 \ 436 0x2f0440UL 437 #define QM_REG_SDMCMDREADY \ 438 0x2f1e10UL 439 #define QM_REG_SDMCMDADDR \ 440 0x2f1e04UL 441 #define QM_REG_SDMCMDDATALSB \ 442 0x2f1e08UL 443 #define QM_REG_SDMCMDDATAMSB \ 444 0x2f1e0cUL 445 #define QM_REG_SDMCMDGO \ 446 0x2f1e14UL 447 #define QM_REG_RLPFCRD \ 448 0x2f4d80UL 449 #define QM_REG_RLPFINCVAL \ 450 0x2f4c80UL 451 #define QM_REG_RLGLBLCRD \ 452 0x2f4400UL 453 #define QM_REG_RLGLBLINCVAL \ 454 0x2f3400UL 455 #define IGU_REG_ATTENTION_ENABLE \ 456 0x18083cUL 457 #define IGU_REG_ATTN_MSG_ADDR_L \ 458 0x180820UL 459 #define IGU_REG_ATTN_MSG_ADDR_H \ 460 0x180824UL 461 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 462 0x008400UL 463 #define CAU_REG_SB_ADDR_MEMORY \ 464 0x1c8000UL 465 #define CAU_REG_SB_VAR_MEMORY \ 466 0x1c6000UL 467 #define CAU_REG_PI_MEMORY \ 468 0x1d0000UL 469 #define IGU_REG_PF_CONFIGURATION \ 470 0x180800UL 471 #define IGU_REG_VF_CONFIGURATION \ 472 0x180804UL 473 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 474 0x00849cUL 475 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 476 0x0087b4UL 477 #define MISC_REG_AEU_MASK_ATTN_IGU \ 478 0x008494UL 479 #define IGU_REG_CLEANUP_STATUS_0 \ 480 0x180980UL 481 #define IGU_REG_CLEANUP_STATUS_1 \ 482 0x180a00UL 483 #define IGU_REG_CLEANUP_STATUS_2 \ 484 0x180a80UL 485 #define IGU_REG_CLEANUP_STATUS_3 \ 486 0x180b00UL 487 #define IGU_REG_CLEANUP_STATUS_4 \ 488 0x180b80UL 489 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 490 0x180840UL 491 #define IGU_REG_COMMAND_REG_CTRL \ 492 0x180848UL 493 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 494 0x1 << 1) 495 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 496 0x1 << 0) 497 #define IGU_REG_MAPPING_MEMORY \ 498 0x184000UL 499 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 500 0x180408UL 501 #define IGU_REG_WRITE_DONE_PENDING \ 502 0x180900UL 503 #define MISCS_REG_GENERIC_POR_0 \ 504 0x0096d4UL 505 #define MCP_REG_NVM_CFG4 \ 506 0xe0642cUL 507 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 508 0x7 << 0) 509 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 510 0 511 #define MCP_REG_CPU_STATE \ 512 0xe05004UL 513 #define MCP_REG_CPU_EVENT_MASK \ 514 0xe05008UL 515 #define PGLUE_B_REG_PF_BAR0_SIZE \ 516 0x2aae60UL 517 #define PGLUE_B_REG_PF_BAR1_SIZE \ 518 0x2aae64UL 519 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 520 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL 521 #define PRS_REG_VXLAN_PORT 0x1f0738UL 522 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 523 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 524 525 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 526 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 527 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 528 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 529 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 530 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 531 532 #define NIG_REG_VXLAN_CTRL 0x50105cUL 533 #define PBF_REG_VXLAN_PORT 0xd80518UL 534 #define PBF_REG_NGE_PORT 0xd8051cUL 535 #define PRS_REG_NGE_PORT 0x1f086cUL 536 #define NIG_REG_NGE_PORT 0x508b38UL 537 538 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 539 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 540 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 541 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 542 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 543 544 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 545 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 546 #define NIG_REG_NGE_COMP_VER 0x508b30UL 547 #define PBF_REG_NGE_COMP_VER 0xd80524UL 548 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 549 550 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 551 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 552 553 #define PGLCS_REG_DBG_SELECT \ 554 0x001d14UL 555 #define PGLCS_REG_DBG_DWORD_ENABLE \ 556 0x001d18UL 557 #define PGLCS_REG_DBG_SHIFT \ 558 0x001d1cUL 559 #define PGLCS_REG_DBG_FORCE_VALID \ 560 0x001d20UL 561 #define PGLCS_REG_DBG_FORCE_FRAME \ 562 0x001d24UL 563 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 564 0x008070UL 565 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 566 0x008080UL 567 #define MISC_REG_RESET_PL_PDA_VAUX \ 568 0x008090UL 569 #define MISCS_REG_RESET_PL_UA \ 570 0x009050UL 571 #define MISCS_REG_RESET_PL_HV \ 572 0x009060UL 573 #define MISCS_REG_RESET_PL_HV_2 \ 574 0x009150UL 575 #define DMAE_REG_DBG_SELECT \ 576 0x00c510UL 577 #define DMAE_REG_DBG_DWORD_ENABLE \ 578 0x00c514UL 579 #define DMAE_REG_DBG_SHIFT \ 580 0x00c518UL 581 #define DMAE_REG_DBG_FORCE_VALID \ 582 0x00c51cUL 583 #define DMAE_REG_DBG_FORCE_FRAME \ 584 0x00c520UL 585 #define NCSI_REG_DBG_SELECT \ 586 0x040474UL 587 #define NCSI_REG_DBG_DWORD_ENABLE \ 588 0x040478UL 589 #define NCSI_REG_DBG_SHIFT \ 590 0x04047cUL 591 #define NCSI_REG_DBG_FORCE_VALID \ 592 0x040480UL 593 #define NCSI_REG_DBG_FORCE_FRAME \ 594 0x040484UL 595 #define GRC_REG_DBG_SELECT \ 596 0x0500a4UL 597 #define GRC_REG_DBG_DWORD_ENABLE \ 598 0x0500a8UL 599 #define GRC_REG_DBG_SHIFT \ 600 0x0500acUL 601 #define GRC_REG_DBG_FORCE_VALID \ 602 0x0500b0UL 603 #define GRC_REG_DBG_FORCE_FRAME \ 604 0x0500b4UL 605 #define UMAC_REG_DBG_SELECT \ 606 0x051094UL 607 #define UMAC_REG_DBG_DWORD_ENABLE \ 608 0x051098UL 609 #define UMAC_REG_DBG_SHIFT \ 610 0x05109cUL 611 #define UMAC_REG_DBG_FORCE_VALID \ 612 0x0510a0UL 613 #define UMAC_REG_DBG_FORCE_FRAME \ 614 0x0510a4UL 615 #define MCP2_REG_DBG_SELECT \ 616 0x052400UL 617 #define MCP2_REG_DBG_DWORD_ENABLE \ 618 0x052404UL 619 #define MCP2_REG_DBG_SHIFT \ 620 0x052408UL 621 #define MCP2_REG_DBG_FORCE_VALID \ 622 0x052440UL 623 #define MCP2_REG_DBG_FORCE_FRAME \ 624 0x052444UL 625 #define PCIE_REG_DBG_SELECT \ 626 0x0547e8UL 627 #define PCIE_REG_DBG_DWORD_ENABLE \ 628 0x0547ecUL 629 #define PCIE_REG_DBG_SHIFT \ 630 0x0547f0UL 631 #define PCIE_REG_DBG_FORCE_VALID \ 632 0x0547f4UL 633 #define PCIE_REG_DBG_FORCE_FRAME \ 634 0x0547f8UL 635 #define DORQ_REG_DBG_SELECT \ 636 0x100ad0UL 637 #define DORQ_REG_DBG_DWORD_ENABLE \ 638 0x100ad4UL 639 #define DORQ_REG_DBG_SHIFT \ 640 0x100ad8UL 641 #define DORQ_REG_DBG_FORCE_VALID \ 642 0x100adcUL 643 #define DORQ_REG_DBG_FORCE_FRAME \ 644 0x100ae0UL 645 #define IGU_REG_DBG_SELECT \ 646 0x181578UL 647 #define IGU_REG_DBG_DWORD_ENABLE \ 648 0x18157cUL 649 #define IGU_REG_DBG_SHIFT \ 650 0x181580UL 651 #define IGU_REG_DBG_FORCE_VALID \ 652 0x181584UL 653 #define IGU_REG_DBG_FORCE_FRAME \ 654 0x181588UL 655 #define CAU_REG_DBG_SELECT \ 656 0x1c0ea8UL 657 #define CAU_REG_DBG_DWORD_ENABLE \ 658 0x1c0eacUL 659 #define CAU_REG_DBG_SHIFT \ 660 0x1c0eb0UL 661 #define CAU_REG_DBG_FORCE_VALID \ 662 0x1c0eb4UL 663 #define CAU_REG_DBG_FORCE_FRAME \ 664 0x1c0eb8UL 665 #define PRS_REG_DBG_SELECT \ 666 0x1f0b6cUL 667 #define PRS_REG_DBG_DWORD_ENABLE \ 668 0x1f0b70UL 669 #define PRS_REG_DBG_SHIFT \ 670 0x1f0b74UL 671 #define PRS_REG_DBG_FORCE_VALID \ 672 0x1f0ba0UL 673 #define PRS_REG_DBG_FORCE_FRAME \ 674 0x1f0ba4UL 675 #define CNIG_REG_DBG_SELECT_K2 \ 676 0x218254UL 677 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \ 678 0x218258UL 679 #define CNIG_REG_DBG_SHIFT_K2 \ 680 0x21825cUL 681 #define CNIG_REG_DBG_FORCE_VALID_K2 \ 682 0x218260UL 683 #define CNIG_REG_DBG_FORCE_FRAME_K2 \ 684 0x218264UL 685 #define PRM_REG_DBG_SELECT \ 686 0x2306a8UL 687 #define PRM_REG_DBG_DWORD_ENABLE \ 688 0x2306acUL 689 #define PRM_REG_DBG_SHIFT \ 690 0x2306b0UL 691 #define PRM_REG_DBG_FORCE_VALID \ 692 0x2306b4UL 693 #define PRM_REG_DBG_FORCE_FRAME \ 694 0x2306b8UL 695 #define SRC_REG_DBG_SELECT \ 696 0x238700UL 697 #define SRC_REG_DBG_DWORD_ENABLE \ 698 0x238704UL 699 #define SRC_REG_DBG_SHIFT \ 700 0x238708UL 701 #define SRC_REG_DBG_FORCE_VALID \ 702 0x23870cUL 703 #define SRC_REG_DBG_FORCE_FRAME \ 704 0x238710UL 705 #define RSS_REG_DBG_SELECT \ 706 0x238c4cUL 707 #define RSS_REG_DBG_DWORD_ENABLE \ 708 0x238c50UL 709 #define RSS_REG_DBG_SHIFT \ 710 0x238c54UL 711 #define RSS_REG_DBG_FORCE_VALID \ 712 0x238c58UL 713 #define RSS_REG_DBG_FORCE_FRAME \ 714 0x238c5cUL 715 #define RPB_REG_DBG_SELECT \ 716 0x23c728UL 717 #define RPB_REG_DBG_DWORD_ENABLE \ 718 0x23c72cUL 719 #define RPB_REG_DBG_SHIFT \ 720 0x23c730UL 721 #define RPB_REG_DBG_FORCE_VALID \ 722 0x23c734UL 723 #define RPB_REG_DBG_FORCE_FRAME \ 724 0x23c738UL 725 #define PSWRQ2_REG_DBG_SELECT \ 726 0x240100UL 727 #define PSWRQ2_REG_DBG_DWORD_ENABLE \ 728 0x240104UL 729 #define PSWRQ2_REG_DBG_SHIFT \ 730 0x240108UL 731 #define PSWRQ2_REG_DBG_FORCE_VALID \ 732 0x24010cUL 733 #define PSWRQ2_REG_DBG_FORCE_FRAME \ 734 0x240110UL 735 #define PSWRQ_REG_DBG_SELECT \ 736 0x280020UL 737 #define PSWRQ_REG_DBG_DWORD_ENABLE \ 738 0x280024UL 739 #define PSWRQ_REG_DBG_SHIFT \ 740 0x280028UL 741 #define PSWRQ_REG_DBG_FORCE_VALID \ 742 0x28002cUL 743 #define PSWRQ_REG_DBG_FORCE_FRAME \ 744 0x280030UL 745 #define PSWWR_REG_DBG_SELECT \ 746 0x29a084UL 747 #define PSWWR_REG_DBG_DWORD_ENABLE \ 748 0x29a088UL 749 #define PSWWR_REG_DBG_SHIFT \ 750 0x29a08cUL 751 #define PSWWR_REG_DBG_FORCE_VALID \ 752 0x29a090UL 753 #define PSWWR_REG_DBG_FORCE_FRAME \ 754 0x29a094UL 755 #define PSWRD_REG_DBG_SELECT \ 756 0x29c040UL 757 #define PSWRD_REG_DBG_DWORD_ENABLE \ 758 0x29c044UL 759 #define PSWRD_REG_DBG_SHIFT \ 760 0x29c048UL 761 #define PSWRD_REG_DBG_FORCE_VALID \ 762 0x29c04cUL 763 #define PSWRD_REG_DBG_FORCE_FRAME \ 764 0x29c050UL 765 #define PSWRD2_REG_DBG_SELECT \ 766 0x29d400UL 767 #define PSWRD2_REG_DBG_DWORD_ENABLE \ 768 0x29d404UL 769 #define PSWRD2_REG_DBG_SHIFT \ 770 0x29d408UL 771 #define PSWRD2_REG_DBG_FORCE_VALID \ 772 0x29d40cUL 773 #define PSWRD2_REG_DBG_FORCE_FRAME \ 774 0x29d410UL 775 #define PSWHST2_REG_DBG_SELECT \ 776 0x29e058UL 777 #define PSWHST2_REG_DBG_DWORD_ENABLE \ 778 0x29e05cUL 779 #define PSWHST2_REG_DBG_SHIFT \ 780 0x29e060UL 781 #define PSWHST2_REG_DBG_FORCE_VALID \ 782 0x29e064UL 783 #define PSWHST2_REG_DBG_FORCE_FRAME \ 784 0x29e068UL 785 #define PSWHST_REG_DBG_SELECT \ 786 0x2a0100UL 787 #define PSWHST_REG_DBG_DWORD_ENABLE \ 788 0x2a0104UL 789 #define PSWHST_REG_DBG_SHIFT \ 790 0x2a0108UL 791 #define PSWHST_REG_DBG_FORCE_VALID \ 792 0x2a010cUL 793 #define PSWHST_REG_DBG_FORCE_FRAME \ 794 0x2a0110UL 795 #define PGLUE_B_REG_DBG_SELECT \ 796 0x2a8400UL 797 #define PGLUE_B_REG_DBG_DWORD_ENABLE \ 798 0x2a8404UL 799 #define PGLUE_B_REG_DBG_SHIFT \ 800 0x2a8408UL 801 #define PGLUE_B_REG_DBG_FORCE_VALID \ 802 0x2a840cUL 803 #define PGLUE_B_REG_DBG_FORCE_FRAME \ 804 0x2a8410UL 805 #define TM_REG_DBG_SELECT \ 806 0x2c07a8UL 807 #define TM_REG_DBG_DWORD_ENABLE \ 808 0x2c07acUL 809 #define TM_REG_DBG_SHIFT \ 810 0x2c07b0UL 811 #define TM_REG_DBG_FORCE_VALID \ 812 0x2c07b4UL 813 #define TM_REG_DBG_FORCE_FRAME \ 814 0x2c07b8UL 815 #define TCFC_REG_DBG_SELECT \ 816 0x2d0500UL 817 #define TCFC_REG_DBG_DWORD_ENABLE \ 818 0x2d0504UL 819 #define TCFC_REG_DBG_SHIFT \ 820 0x2d0508UL 821 #define TCFC_REG_DBG_FORCE_VALID \ 822 0x2d050cUL 823 #define TCFC_REG_DBG_FORCE_FRAME \ 824 0x2d0510UL 825 #define CCFC_REG_DBG_SELECT \ 826 0x2e0500UL 827 #define CCFC_REG_DBG_DWORD_ENABLE \ 828 0x2e0504UL 829 #define CCFC_REG_DBG_SHIFT \ 830 0x2e0508UL 831 #define CCFC_REG_DBG_FORCE_VALID \ 832 0x2e050cUL 833 #define CCFC_REG_DBG_FORCE_FRAME \ 834 0x2e0510UL 835 #define QM_REG_DBG_SELECT \ 836 0x2f2e74UL 837 #define QM_REG_DBG_DWORD_ENABLE \ 838 0x2f2e78UL 839 #define QM_REG_DBG_SHIFT \ 840 0x2f2e7cUL 841 #define QM_REG_DBG_FORCE_VALID \ 842 0x2f2e80UL 843 #define QM_REG_DBG_FORCE_FRAME \ 844 0x2f2e84UL 845 #define RDIF_REG_DBG_SELECT \ 846 0x300500UL 847 #define RDIF_REG_DBG_DWORD_ENABLE \ 848 0x300504UL 849 #define RDIF_REG_DBG_SHIFT \ 850 0x300508UL 851 #define RDIF_REG_DBG_FORCE_VALID \ 852 0x30050cUL 853 #define RDIF_REG_DBG_FORCE_FRAME \ 854 0x300510UL 855 #define TDIF_REG_DBG_SELECT \ 856 0x310500UL 857 #define TDIF_REG_DBG_DWORD_ENABLE \ 858 0x310504UL 859 #define TDIF_REG_DBG_SHIFT \ 860 0x310508UL 861 #define TDIF_REG_DBG_FORCE_VALID \ 862 0x31050cUL 863 #define TDIF_REG_DBG_FORCE_FRAME \ 864 0x310510UL 865 #define BRB_REG_DBG_SELECT \ 866 0x340ed0UL 867 #define BRB_REG_DBG_DWORD_ENABLE \ 868 0x340ed4UL 869 #define BRB_REG_DBG_SHIFT \ 870 0x340ed8UL 871 #define BRB_REG_DBG_FORCE_VALID \ 872 0x340edcUL 873 #define BRB_REG_DBG_FORCE_FRAME \ 874 0x340ee0UL 875 #define XYLD_REG_DBG_SELECT \ 876 0x4c1600UL 877 #define XYLD_REG_DBG_DWORD_ENABLE \ 878 0x4c1604UL 879 #define XYLD_REG_DBG_SHIFT \ 880 0x4c1608UL 881 #define XYLD_REG_DBG_FORCE_VALID \ 882 0x4c160cUL 883 #define XYLD_REG_DBG_FORCE_FRAME \ 884 0x4c1610UL 885 #define YULD_REG_DBG_SELECT \ 886 0x4c9600UL 887 #define YULD_REG_DBG_DWORD_ENABLE \ 888 0x4c9604UL 889 #define YULD_REG_DBG_SHIFT \ 890 0x4c9608UL 891 #define YULD_REG_DBG_FORCE_VALID \ 892 0x4c960cUL 893 #define YULD_REG_DBG_FORCE_FRAME \ 894 0x4c9610UL 895 #define TMLD_REG_DBG_SELECT \ 896 0x4d1600UL 897 #define TMLD_REG_DBG_DWORD_ENABLE \ 898 0x4d1604UL 899 #define TMLD_REG_DBG_SHIFT \ 900 0x4d1608UL 901 #define TMLD_REG_DBG_FORCE_VALID \ 902 0x4d160cUL 903 #define TMLD_REG_DBG_FORCE_FRAME \ 904 0x4d1610UL 905 #define MULD_REG_DBG_SELECT \ 906 0x4e1600UL 907 #define MULD_REG_DBG_DWORD_ENABLE \ 908 0x4e1604UL 909 #define MULD_REG_DBG_SHIFT \ 910 0x4e1608UL 911 #define MULD_REG_DBG_FORCE_VALID \ 912 0x4e160cUL 913 #define MULD_REG_DBG_FORCE_FRAME \ 914 0x4e1610UL 915 #define NIG_REG_DBG_SELECT \ 916 0x502140UL 917 #define NIG_REG_DBG_DWORD_ENABLE \ 918 0x502144UL 919 #define NIG_REG_DBG_SHIFT \ 920 0x502148UL 921 #define NIG_REG_DBG_FORCE_VALID \ 922 0x50214cUL 923 #define NIG_REG_DBG_FORCE_FRAME \ 924 0x502150UL 925 #define BMB_REG_DBG_SELECT \ 926 0x540a7cUL 927 #define BMB_REG_DBG_DWORD_ENABLE \ 928 0x540a80UL 929 #define BMB_REG_DBG_SHIFT \ 930 0x540a84UL 931 #define BMB_REG_DBG_FORCE_VALID \ 932 0x540a88UL 933 #define BMB_REG_DBG_FORCE_FRAME \ 934 0x540a8cUL 935 #define PTU_REG_DBG_SELECT \ 936 0x560100UL 937 #define PTU_REG_DBG_DWORD_ENABLE \ 938 0x560104UL 939 #define PTU_REG_DBG_SHIFT \ 940 0x560108UL 941 #define PTU_REG_DBG_FORCE_VALID \ 942 0x56010cUL 943 #define PTU_REG_DBG_FORCE_FRAME \ 944 0x560110UL 945 #define CDU_REG_DBG_SELECT \ 946 0x580704UL 947 #define CDU_REG_DBG_DWORD_ENABLE \ 948 0x580708UL 949 #define CDU_REG_DBG_SHIFT \ 950 0x58070cUL 951 #define CDU_REG_DBG_FORCE_VALID \ 952 0x580710UL 953 #define CDU_REG_DBG_FORCE_FRAME \ 954 0x580714UL 955 #define WOL_REG_DBG_SELECT \ 956 0x600140UL 957 #define WOL_REG_DBG_DWORD_ENABLE \ 958 0x600144UL 959 #define WOL_REG_DBG_SHIFT \ 960 0x600148UL 961 #define WOL_REG_DBG_FORCE_VALID \ 962 0x60014cUL 963 #define WOL_REG_DBG_FORCE_FRAME \ 964 0x600150UL 965 #define BMBN_REG_DBG_SELECT \ 966 0x610140UL 967 #define BMBN_REG_DBG_DWORD_ENABLE \ 968 0x610144UL 969 #define BMBN_REG_DBG_SHIFT \ 970 0x610148UL 971 #define BMBN_REG_DBG_FORCE_VALID \ 972 0x61014cUL 973 #define BMBN_REG_DBG_FORCE_FRAME \ 974 0x610150UL 975 #define NWM_REG_DBG_SELECT \ 976 0x8000ecUL 977 #define NWM_REG_DBG_DWORD_ENABLE \ 978 0x8000f0UL 979 #define NWM_REG_DBG_SHIFT \ 980 0x8000f4UL 981 #define NWM_REG_DBG_FORCE_VALID \ 982 0x8000f8UL 983 #define NWM_REG_DBG_FORCE_FRAME \ 984 0x8000fcUL 985 #define PBF_REG_DBG_SELECT \ 986 0xd80060UL 987 #define PBF_REG_DBG_DWORD_ENABLE \ 988 0xd80064UL 989 #define PBF_REG_DBG_SHIFT \ 990 0xd80068UL 991 #define PBF_REG_DBG_FORCE_VALID \ 992 0xd8006cUL 993 #define PBF_REG_DBG_FORCE_FRAME \ 994 0xd80070UL 995 #define PBF_PB1_REG_DBG_SELECT \ 996 0xda0728UL 997 #define PBF_PB1_REG_DBG_DWORD_ENABLE \ 998 0xda072cUL 999 #define PBF_PB1_REG_DBG_SHIFT \ 1000 0xda0730UL 1001 #define PBF_PB1_REG_DBG_FORCE_VALID \ 1002 0xda0734UL 1003 #define PBF_PB1_REG_DBG_FORCE_FRAME \ 1004 0xda0738UL 1005 #define PBF_PB2_REG_DBG_SELECT \ 1006 0xda4728UL 1007 #define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1008 0xda472cUL 1009 #define PBF_PB2_REG_DBG_SHIFT \ 1010 0xda4730UL 1011 #define PBF_PB2_REG_DBG_FORCE_VALID \ 1012 0xda4734UL 1013 #define PBF_PB2_REG_DBG_FORCE_FRAME \ 1014 0xda4738UL 1015 #define BTB_REG_DBG_SELECT \ 1016 0xdb08c8UL 1017 #define BTB_REG_DBG_DWORD_ENABLE \ 1018 0xdb08ccUL 1019 #define BTB_REG_DBG_SHIFT \ 1020 0xdb08d0UL 1021 #define BTB_REG_DBG_FORCE_VALID \ 1022 0xdb08d4UL 1023 #define BTB_REG_DBG_FORCE_FRAME \ 1024 0xdb08d8UL 1025 #define XSDM_REG_DBG_SELECT \ 1026 0xf80e28UL 1027 #define XSDM_REG_DBG_DWORD_ENABLE \ 1028 0xf80e2cUL 1029 #define XSDM_REG_DBG_SHIFT \ 1030 0xf80e30UL 1031 #define XSDM_REG_DBG_FORCE_VALID \ 1032 0xf80e34UL 1033 #define XSDM_REG_DBG_FORCE_FRAME \ 1034 0xf80e38UL 1035 #define YSDM_REG_DBG_SELECT \ 1036 0xf90e28UL 1037 #define YSDM_REG_DBG_DWORD_ENABLE \ 1038 0xf90e2cUL 1039 #define YSDM_REG_DBG_SHIFT \ 1040 0xf90e30UL 1041 #define YSDM_REG_DBG_FORCE_VALID \ 1042 0xf90e34UL 1043 #define YSDM_REG_DBG_FORCE_FRAME \ 1044 0xf90e38UL 1045 #define PSDM_REG_DBG_SELECT \ 1046 0xfa0e28UL 1047 #define PSDM_REG_DBG_DWORD_ENABLE \ 1048 0xfa0e2cUL 1049 #define PSDM_REG_DBG_SHIFT \ 1050 0xfa0e30UL 1051 #define PSDM_REG_DBG_FORCE_VALID \ 1052 0xfa0e34UL 1053 #define PSDM_REG_DBG_FORCE_FRAME \ 1054 0xfa0e38UL 1055 #define TSDM_REG_DBG_SELECT \ 1056 0xfb0e28UL 1057 #define TSDM_REG_DBG_DWORD_ENABLE \ 1058 0xfb0e2cUL 1059 #define TSDM_REG_DBG_SHIFT \ 1060 0xfb0e30UL 1061 #define TSDM_REG_DBG_FORCE_VALID \ 1062 0xfb0e34UL 1063 #define TSDM_REG_DBG_FORCE_FRAME \ 1064 0xfb0e38UL 1065 #define MSDM_REG_DBG_SELECT \ 1066 0xfc0e28UL 1067 #define MSDM_REG_DBG_DWORD_ENABLE \ 1068 0xfc0e2cUL 1069 #define MSDM_REG_DBG_SHIFT \ 1070 0xfc0e30UL 1071 #define MSDM_REG_DBG_FORCE_VALID \ 1072 0xfc0e34UL 1073 #define MSDM_REG_DBG_FORCE_FRAME \ 1074 0xfc0e38UL 1075 #define USDM_REG_DBG_SELECT \ 1076 0xfd0e28UL 1077 #define USDM_REG_DBG_DWORD_ENABLE \ 1078 0xfd0e2cUL 1079 #define USDM_REG_DBG_SHIFT \ 1080 0xfd0e30UL 1081 #define USDM_REG_DBG_FORCE_VALID \ 1082 0xfd0e34UL 1083 #define USDM_REG_DBG_FORCE_FRAME \ 1084 0xfd0e38UL 1085 #define XCM_REG_DBG_SELECT \ 1086 0x1000040UL 1087 #define XCM_REG_DBG_DWORD_ENABLE \ 1088 0x1000044UL 1089 #define XCM_REG_DBG_SHIFT \ 1090 0x1000048UL 1091 #define XCM_REG_DBG_FORCE_VALID \ 1092 0x100004cUL 1093 #define XCM_REG_DBG_FORCE_FRAME \ 1094 0x1000050UL 1095 #define YCM_REG_DBG_SELECT \ 1096 0x1080040UL 1097 #define YCM_REG_DBG_DWORD_ENABLE \ 1098 0x1080044UL 1099 #define YCM_REG_DBG_SHIFT \ 1100 0x1080048UL 1101 #define YCM_REG_DBG_FORCE_VALID \ 1102 0x108004cUL 1103 #define YCM_REG_DBG_FORCE_FRAME \ 1104 0x1080050UL 1105 #define PCM_REG_DBG_SELECT \ 1106 0x1100040UL 1107 #define PCM_REG_DBG_DWORD_ENABLE \ 1108 0x1100044UL 1109 #define PCM_REG_DBG_SHIFT \ 1110 0x1100048UL 1111 #define PCM_REG_DBG_FORCE_VALID \ 1112 0x110004cUL 1113 #define PCM_REG_DBG_FORCE_FRAME \ 1114 0x1100050UL 1115 #define TCM_REG_DBG_SELECT \ 1116 0x1180040UL 1117 #define TCM_REG_DBG_DWORD_ENABLE \ 1118 0x1180044UL 1119 #define TCM_REG_DBG_SHIFT \ 1120 0x1180048UL 1121 #define TCM_REG_DBG_FORCE_VALID \ 1122 0x118004cUL 1123 #define TCM_REG_DBG_FORCE_FRAME \ 1124 0x1180050UL 1125 #define MCM_REG_DBG_SELECT \ 1126 0x1200040UL 1127 #define MCM_REG_DBG_DWORD_ENABLE \ 1128 0x1200044UL 1129 #define MCM_REG_DBG_SHIFT \ 1130 0x1200048UL 1131 #define MCM_REG_DBG_FORCE_VALID \ 1132 0x120004cUL 1133 #define MCM_REG_DBG_FORCE_FRAME \ 1134 0x1200050UL 1135 #define UCM_REG_DBG_SELECT \ 1136 0x1280050UL 1137 #define UCM_REG_DBG_DWORD_ENABLE \ 1138 0x1280054UL 1139 #define UCM_REG_DBG_SHIFT \ 1140 0x1280058UL 1141 #define UCM_REG_DBG_FORCE_VALID \ 1142 0x128005cUL 1143 #define UCM_REG_DBG_FORCE_FRAME \ 1144 0x1280060UL 1145 #define XSEM_REG_DBG_SELECT \ 1146 0x1401528UL 1147 #define XSEM_REG_DBG_DWORD_ENABLE \ 1148 0x140152cUL 1149 #define XSEM_REG_DBG_SHIFT \ 1150 0x1401530UL 1151 #define XSEM_REG_DBG_FORCE_VALID \ 1152 0x1401534UL 1153 #define XSEM_REG_DBG_FORCE_FRAME \ 1154 0x1401538UL 1155 #define YSEM_REG_DBG_SELECT \ 1156 0x1501528UL 1157 #define YSEM_REG_DBG_DWORD_ENABLE \ 1158 0x150152cUL 1159 #define YSEM_REG_DBG_SHIFT \ 1160 0x1501530UL 1161 #define YSEM_REG_DBG_FORCE_VALID \ 1162 0x1501534UL 1163 #define YSEM_REG_DBG_FORCE_FRAME \ 1164 0x1501538UL 1165 #define PSEM_REG_DBG_SELECT \ 1166 0x1601528UL 1167 #define PSEM_REG_DBG_DWORD_ENABLE \ 1168 0x160152cUL 1169 #define PSEM_REG_DBG_SHIFT \ 1170 0x1601530UL 1171 #define PSEM_REG_DBG_FORCE_VALID \ 1172 0x1601534UL 1173 #define PSEM_REG_DBG_FORCE_FRAME \ 1174 0x1601538UL 1175 #define TSEM_REG_DBG_SELECT \ 1176 0x1701528UL 1177 #define TSEM_REG_DBG_DWORD_ENABLE \ 1178 0x170152cUL 1179 #define TSEM_REG_DBG_SHIFT \ 1180 0x1701530UL 1181 #define TSEM_REG_DBG_FORCE_VALID \ 1182 0x1701534UL 1183 #define TSEM_REG_DBG_FORCE_FRAME \ 1184 0x1701538UL 1185 #define MSEM_REG_DBG_SELECT \ 1186 0x1801528UL 1187 #define MSEM_REG_DBG_DWORD_ENABLE \ 1188 0x180152cUL 1189 #define MSEM_REG_DBG_SHIFT \ 1190 0x1801530UL 1191 #define MSEM_REG_DBG_FORCE_VALID \ 1192 0x1801534UL 1193 #define MSEM_REG_DBG_FORCE_FRAME \ 1194 0x1801538UL 1195 #define USEM_REG_DBG_SELECT \ 1196 0x1901528UL 1197 #define USEM_REG_DBG_DWORD_ENABLE \ 1198 0x190152cUL 1199 #define USEM_REG_DBG_SHIFT \ 1200 0x1901530UL 1201 #define USEM_REG_DBG_FORCE_VALID \ 1202 0x1901534UL 1203 #define USEM_REG_DBG_FORCE_FRAME \ 1204 0x1901538UL 1205 #define PCIE_REG_DBG_COMMON_SELECT \ 1206 0x054398UL 1207 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \ 1208 0x05439cUL 1209 #define PCIE_REG_DBG_COMMON_SHIFT \ 1210 0x0543a0UL 1211 #define PCIE_REG_DBG_COMMON_FORCE_VALID \ 1212 0x0543a4UL 1213 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \ 1214 0x0543a8UL 1215 #define MISC_REG_RESET_PL_UA \ 1216 0x008050UL 1217 #define MISC_REG_RESET_PL_HV \ 1218 0x008060UL 1219 #define XCM_REG_CTX_RBC_ACCS \ 1220 0x1001800UL 1221 #define XCM_REG_AGG_CON_CTX \ 1222 0x1001804UL 1223 #define XCM_REG_SM_CON_CTX \ 1224 0x1001808UL 1225 #define YCM_REG_CTX_RBC_ACCS \ 1226 0x1081800UL 1227 #define YCM_REG_AGG_CON_CTX \ 1228 0x1081804UL 1229 #define YCM_REG_AGG_TASK_CTX \ 1230 0x1081808UL 1231 #define YCM_REG_SM_CON_CTX \ 1232 0x108180cUL 1233 #define YCM_REG_SM_TASK_CTX \ 1234 0x1081810UL 1235 #define PCM_REG_CTX_RBC_ACCS \ 1236 0x1101440UL 1237 #define PCM_REG_SM_CON_CTX \ 1238 0x1101444UL 1239 #define TCM_REG_CTX_RBC_ACCS \ 1240 0x11814c0UL 1241 #define TCM_REG_AGG_CON_CTX \ 1242 0x11814c4UL 1243 #define TCM_REG_AGG_TASK_CTX \ 1244 0x11814c8UL 1245 #define TCM_REG_SM_CON_CTX \ 1246 0x11814ccUL 1247 #define TCM_REG_SM_TASK_CTX \ 1248 0x11814d0UL 1249 #define MCM_REG_CTX_RBC_ACCS \ 1250 0x1201800UL 1251 #define MCM_REG_AGG_CON_CTX \ 1252 0x1201804UL 1253 #define MCM_REG_AGG_TASK_CTX \ 1254 0x1201808UL 1255 #define MCM_REG_SM_CON_CTX \ 1256 0x120180cUL 1257 #define MCM_REG_SM_TASK_CTX \ 1258 0x1201810UL 1259 #define UCM_REG_CTX_RBC_ACCS \ 1260 0x1281700UL 1261 #define UCM_REG_AGG_CON_CTX \ 1262 0x1281704UL 1263 #define UCM_REG_AGG_TASK_CTX \ 1264 0x1281708UL 1265 #define UCM_REG_SM_CON_CTX \ 1266 0x128170cUL 1267 #define UCM_REG_SM_TASK_CTX \ 1268 0x1281710UL 1269 #define XSEM_REG_SLOW_DBG_EMPTY \ 1270 0x1401140UL 1271 #define XSEM_REG_SYNC_DBG_EMPTY \ 1272 0x1401160UL 1273 #define XSEM_REG_SLOW_DBG_ACTIVE \ 1274 0x1401400UL 1275 #define XSEM_REG_SLOW_DBG_MODE \ 1276 0x1401404UL 1277 #define XSEM_REG_DBG_FRAME_MODE \ 1278 0x1401408UL 1279 #define XSEM_REG_DBG_MODE1_CFG \ 1280 0x1401420UL 1281 #define XSEM_REG_FAST_MEMORY \ 1282 0x1440000UL 1283 #define YSEM_REG_SYNC_DBG_EMPTY \ 1284 0x1501160UL 1285 #define YSEM_REG_SLOW_DBG_ACTIVE \ 1286 0x1501400UL 1287 #define YSEM_REG_SLOW_DBG_MODE \ 1288 0x1501404UL 1289 #define YSEM_REG_DBG_FRAME_MODE \ 1290 0x1501408UL 1291 #define YSEM_REG_DBG_MODE1_CFG \ 1292 0x1501420UL 1293 #define YSEM_REG_FAST_MEMORY \ 1294 0x1540000UL 1295 #define PSEM_REG_SLOW_DBG_EMPTY \ 1296 0x1601140UL 1297 #define PSEM_REG_SYNC_DBG_EMPTY \ 1298 0x1601160UL 1299 #define PSEM_REG_SLOW_DBG_ACTIVE \ 1300 0x1601400UL 1301 #define PSEM_REG_SLOW_DBG_MODE \ 1302 0x1601404UL 1303 #define PSEM_REG_DBG_FRAME_MODE \ 1304 0x1601408UL 1305 #define PSEM_REG_DBG_MODE1_CFG \ 1306 0x1601420UL 1307 #define PSEM_REG_FAST_MEMORY \ 1308 0x1640000UL 1309 #define TSEM_REG_SLOW_DBG_EMPTY \ 1310 0x1701140UL 1311 #define TSEM_REG_SYNC_DBG_EMPTY \ 1312 0x1701160UL 1313 #define TSEM_REG_SLOW_DBG_ACTIVE \ 1314 0x1701400UL 1315 #define TSEM_REG_SLOW_DBG_MODE \ 1316 0x1701404UL 1317 #define TSEM_REG_DBG_FRAME_MODE \ 1318 0x1701408UL 1319 #define TSEM_REG_DBG_MODE1_CFG \ 1320 0x1701420UL 1321 #define TSEM_REG_FAST_MEMORY \ 1322 0x1740000UL 1323 #define MSEM_REG_SLOW_DBG_EMPTY \ 1324 0x1801140UL 1325 #define MSEM_REG_SYNC_DBG_EMPTY \ 1326 0x1801160UL 1327 #define MSEM_REG_SLOW_DBG_ACTIVE \ 1328 0x1801400UL 1329 #define MSEM_REG_SLOW_DBG_MODE \ 1330 0x1801404UL 1331 #define MSEM_REG_DBG_FRAME_MODE \ 1332 0x1801408UL 1333 #define MSEM_REG_DBG_MODE1_CFG \ 1334 0x1801420UL 1335 #define MSEM_REG_FAST_MEMORY \ 1336 0x1840000UL 1337 #define USEM_REG_SLOW_DBG_EMPTY \ 1338 0x1901140UL 1339 #define USEM_REG_SYNC_DBG_EMPTY \ 1340 0x1901160UL 1341 #define USEM_REG_SLOW_DBG_ACTIVE \ 1342 0x1901400UL 1343 #define USEM_REG_SLOW_DBG_MODE \ 1344 0x1901404UL 1345 #define USEM_REG_DBG_FRAME_MODE \ 1346 0x1901408UL 1347 #define USEM_REG_DBG_MODE1_CFG \ 1348 0x1901420UL 1349 #define USEM_REG_FAST_MEMORY \ 1350 0x1940000UL 1351 #define SEM_FAST_REG_INT_RAM \ 1352 0x020000UL 1353 #define SEM_FAST_REG_INT_RAM_SIZE \ 1354 20480 1355 #define GRC_REG_TRACE_FIFO_VALID_DATA \ 1356 0x050064UL 1357 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1358 0x05040cUL 1359 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1360 0x050500UL 1361 #define IGU_REG_ERROR_HANDLING_MEMORY \ 1362 0x181520UL 1363 #define MCP_REG_CPU_MODE \ 1364 0xe05000UL 1365 #define MCP_REG_CPU_MODE_SOFT_HALT \ 1366 (0x1 << 10) 1367 #define BRB_REG_BIG_RAM_ADDRESS \ 1368 0x340800UL 1369 #define BRB_REG_BIG_RAM_DATA \ 1370 0x341500UL 1371 #define SEM_FAST_REG_STALL_0 \ 1372 0x000488UL 1373 #define SEM_FAST_REG_STALLED \ 1374 0x000494UL 1375 #define BTB_REG_BIG_RAM_ADDRESS \ 1376 0xdb0800UL 1377 #define BTB_REG_BIG_RAM_DATA \ 1378 0xdb0c00UL 1379 #define BMB_REG_BIG_RAM_ADDRESS \ 1380 0x540800UL 1381 #define BMB_REG_BIG_RAM_DATA \ 1382 0x540f00UL 1383 #define SEM_FAST_REG_STORM_REG_FILE \ 1384 0x008000UL 1385 #define RSS_REG_RSS_RAM_ADDR \ 1386 0x238c30UL 1387 #define MISCS_REG_BLOCK_256B_EN \ 1388 0x009074UL 1389 #define MCP_REG_SCRATCH_SIZE \ 1390 57344 1391 #define MCP_REG_CPU_REG_FILE \ 1392 0xe05200UL 1393 #define MCP_REG_CPU_REG_FILE_SIZE \ 1394 32 1395 #define DBG_REG_DEBUG_TARGET \ 1396 0x01005cUL 1397 #define DBG_REG_FULL_MODE \ 1398 0x010060UL 1399 #define DBG_REG_CALENDAR_OUT_DATA \ 1400 0x010480UL 1401 #define GRC_REG_TRACE_FIFO \ 1402 0x050068UL 1403 #define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1404 0x181530UL 1405 #define DBG_REG_DBG_BLOCK_ON \ 1406 0x010454UL 1407 #define DBG_REG_FRAMING_MODE \ 1408 0x010058UL 1409 #define SEM_FAST_REG_VFC_DATA_WR \ 1410 0x000b40UL 1411 #define SEM_FAST_REG_VFC_ADDR \ 1412 0x000b44UL 1413 #define SEM_FAST_REG_VFC_DATA_RD \ 1414 0x000b48UL 1415 #define RSS_REG_RSS_RAM_DATA \ 1416 0x238c20UL 1417 #define MISC_REG_BLOCK_256B_EN \ 1418 0x008c14UL 1419 #define NWS_REG_NWS_CMU \ 1420 0x720000UL 1421 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \ 1422 0x000680UL 1423 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \ 1424 0x000684UL 1425 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \ 1426 0x0006c0UL 1427 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \ 1428 0x0006c4UL 1429 #define MS_REG_MS_CMU \ 1430 0x6a4000UL 1431 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \ 1432 0x000208UL 1433 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \ 1434 0x000210UL 1435 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \ 1436 0x00020cUL 1437 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \ 1438 0x000214UL 1439 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \ 1440 0x000208UL 1441 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \ 1442 0x00020cUL 1443 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \ 1444 0x000210UL 1445 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \ 1446 0x000214UL 1447 #define PHY_PCIE_REG_PHY0 \ 1448 0x620000UL 1449 #define PHY_PCIE_REG_PHY1 \ 1450 0x624000UL 1451 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1452 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1453 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1454 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1455 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1456 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1457 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1458 #endif 1459