| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 84 #define PERIPH_GATE(_name, _bit) \ argument
93 #define PERIPH_MUX(_name, _shift) \ argument
103 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
114 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
124 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
129 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
134 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
138 #define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \ argument
142 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
146 #define REF_CLK_FULL(_name) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
69 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
77 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
97 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
115 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
131 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
139 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 610 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
649 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
658 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
725 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
756 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
765 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
843 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
852 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
866 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
882 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
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| D | clk-mtk.h | 36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ argument
108 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
124 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ argument
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| D | clk-mt8135.c | 411 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
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| /drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 46 #define DEF_TYPE(_name, _id, _type...) \ argument
48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
51 #define DEF_INPUT(_name, _id) \ argument
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
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| /drivers/regulator/ |
| D | mc13xxx.h | 59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
92 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
107 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
109 #define MC13xxx_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages, ops) \ argument
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| D | pfuze100-regulator.c | 163 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ argument
178 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ argument
196 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ argument
213 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ argument
233 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ argument
253 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \ argument
270 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 86 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
103 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
110 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
129 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
138 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
148 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
163 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| D | ccu_common.h | 27 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
36 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
45 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
89 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
133 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/pinctrl/mvebu/ |
| D | pinctrl-mvebu.h | 116 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ argument
128 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \ argument
140 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
150 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
153 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
157 #define MPP_FUNCTION(_val, _name, _subname) \ argument
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| /drivers/usb/atm/ |
| D | cxacru.c | 213 #define CXACRU__ATTR_INIT(_name) \ argument
216 #define CXACRU_CMD_INIT(_name) \ argument
220 #define CXACRU_SET_INIT(_name) \ argument
224 #define CXACRU_ATTR_INIT(_value, _type, _name) \ argument
238 #define CXACRU_ATTR_CREATE(_v, _t, _name) CXACRU_DEVICE_CREATE_FILE(_name) argument
239 #define CXACRU_CMD_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
240 #define CXACRU_SET_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
241 #define CXACRU__ATTR_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
243 #define CXACRU_ATTR_REMOVE(_v, _t, _name) CXACRU_DEVICE_REMOVE_FILE(_name) argument
244 #define CXACRU_CMD_REMOVE(_name) CXACRU_DEVICE_REMOVE_FILE(_name) argument
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 144 #define MUX(_name, _parents, _offset, \ argument
151 #define MUX_FLAGS(_name, _parents, _offset,\ argument
158 #define MUX8(_name, _parents, _offset, \ argument
165 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
171 #define INT(_name, _parents, _offset, \ argument
178 #define INT_FLAGS(_name, _parents, _offset,\ argument
185 #define INT8(_name, _parents, _offset,\ argument
192 #define UART(_name, _parents, _offset,\ argument
199 #define UART8(_name, _parents, _offset,\ argument
206 #define I2C(_name, _parents, _offset,\ argument
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| D | clk-tegra-audio.c | 46 #define SYNC(_name) \ argument
62 #define AUDIO(_name, _offset) \ argument
81 #define AUDIO2X(_name, _num, _offset) \ argument
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| /drivers/s390/scsi/ |
| D | zfcp_sysfs.c | 15 #define ZFCP_DEV_ATTR(_feat, _name, _mode, _show, _store) \ argument
18 #define ZFCP_DEFINE_ATTR(_feat_def, _feat, _name, _format, _value) \ argument
30 #define ZFCP_DEFINE_ATTR_CONST(_feat, _name, _format, _value) \ argument
40 #define ZFCP_DEFINE_A_ATTR(_name, _format, _value) \ argument
376 #define ZFCP_DEFINE_LATENCY_ATTR(_name) \ argument
437 #define ZFCP_DEFINE_SCSI_ATTR(_name, _format, _value) \ argument
572 #define ZFCP_SHOST_ATTR(_name, _format, _arg...) \ argument
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| /drivers/cpuidle/ |
| D | sysfs.c | 168 #define define_one_ro(_name, show) \ argument
170 #define define_one_rw(_name, show, store) \ argument
245 #define define_one_state_ro(_name, show) \ argument
248 #define define_one_state_rw(_name, show, store) \ argument
251 #define define_show_state_function(_name) \ argument
258 #define define_store_state_ull_function(_name) \ argument
277 #define define_show_state_ull_function(_name) \ argument
285 #define define_show_state_str_function(_name) \ argument
447 #define define_one_driver_ro(_name, show) \ argument
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| /drivers/input/mouse/ |
| D | trackpoint.c | 145 #define TRACKPOINT_INT_ATTR(_name, _command, _default) \ argument
183 #define TRACKPOINT_BIT_ATTR(_name, _command, _mask, _inv, _default) \ argument
196 #define TRACKPOINT_UPDATE_BIT(_psmouse, _tp, _name) \ argument
204 #define TRACKPOINT_UPDATE(_power_on, _psmouse, _tp, _name) \ argument
217 #define TRACKPOINT_SET_POWER_ON_DEFAULT(_tp, _name) \ argument
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| /drivers/firmware/ |
| D | dcdbas.h | 57 #define DCDBAS_DEV_ATTR_RW(_name) \ argument
60 #define DCDBAS_DEV_ATTR_RO(_name) \ argument
63 #define DCDBAS_DEV_ATTR_WO(_name) \ argument
66 #define DCDBAS_BIN_ATTR_RW(_name) \ argument
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| D | dmi-id.c | 34 #define DMI_ATTR(_name, _mode, _show, _field) \ argument
38 #define DEFINE_DMI_ATTR_WITH_SHOW(_name, _mode, _field) \ argument
172 #define ADD_DMI_ATTR(_name, _field) \ argument
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| /drivers/mfd/ |
| D | lp8788.c | 23 #define MFD_DEV_SIMPLE(_name) \ argument
28 #define MFD_DEV_WITH_ID(_name, _id) \ argument
34 #define MFD_DEV_WITH_RESOURCE(_name, _resource, num_resource) \ argument
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| D | lm3533-ctrlbank.c | 96 #define lm3533_ctrlbank_set(_name, _NAME) \ argument
114 #define lm3533_ctrlbank_get(_name, _NAME) \ argument
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| /drivers/lightnvm/ |
| D | sysfs.c | 85 #define NVM_DEV_ATTR_RO(_name) \ argument
115 #define NVM_DEV_ATTR(_name) (dev_attr_##_name##) argument
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| /drivers/iio/adc/ |
| D | ad7266.c | 207 #define AD7266_DECLARE_SINGLE_ENDED_CHANNELS(_name, _sign) \ argument
224 #define AD7266_DECLARE_SINGLE_ENDED_CHANNELS_FIXED(_name, _sign) \ argument
256 #define AD7266_DECLARE_DIFF_CHANNELS(_name, _sign) \ argument
270 #define AD7266_DECLARE_DIFF_CHANNELS_FIXED(_name, _sign) \ argument
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| /drivers/bus/ |
| D | arm-ccn.c | 233 #define CCN_FORMAT_ATTR(_name, _config) \ argument
281 #define CCN_EVENT_ATTR(_name) \ argument
292 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ argument
297 #define CCN_EVENT_HNI(_name, _def, _mask) { \ argument
302 #define CCN_EVENT_SBSX(_name, _def, _mask) { \ argument
307 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \ argument
310 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \ argument
319 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \ argument
322 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \ argument
325 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \ argument
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