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/drivers/clk/zte/
Dclk.h17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
69 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
77 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
97 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
115 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
131 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
139 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
/drivers/clk/mediatek/
Dclk-mt8173.c610 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
649 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
658 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
725 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
756 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
765 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
843 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
852 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
866 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
882 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
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Dclk-mt8135.c411 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
Dclk-mtk.h36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
124 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ argument
/drivers/clk/renesas/
Drenesas-cpg-mssr.h48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
Drcar-gen3-cpg.h25 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
/drivers/clk/sunxi-ng/
Dccu_div.h86 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
103 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
148 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
163 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
Dccu_nm.h40 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
64 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
Dccu_common.h27 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
45 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ argument
Dccu_gate.h27 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
Dccu_phase.h28 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
Dccu_mult.h26 #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
Dccu_nk.h41 #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ argument
Dccu_nkmp.h40 #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
Dccu_nkm.h62 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
/drivers/clk/uniphier/
Dclk-uniphier.h68 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ argument
81 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
/drivers/iio/pressure/
Dzpa2326.c742 #define zpa2326_init_runtime(_parent) argument
743 #define zpa2326_fini_runtime(_parent) argument
/drivers/clk/pxa/
Dclk-pxa25x.c220 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument
Dclk-pxa3xx.c301 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument
Dclk-pxa27x.c356 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument