1 /*
2 * ADE7758 Poly Phase Multifunction Energy Metering IC driver
3 *
4 * Copyright 2010-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/delay.h>
12 #include <linux/mutex.h>
13 #include <linux/device.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/slab.h>
17 #include <linux/sysfs.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include "meter.h"
25 #include "ade7758.h"
26
ade7758_spi_write_reg_8(struct device * dev,u8 reg_address,u8 val)27 int ade7758_spi_write_reg_8(struct device *dev, u8 reg_address, u8 val)
28 {
29 int ret;
30 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
31 struct ade7758_state *st = iio_priv(indio_dev);
32
33 mutex_lock(&st->buf_lock);
34 st->tx[0] = ADE7758_WRITE_REG(reg_address);
35 st->tx[1] = val;
36
37 ret = spi_write(st->us, st->tx, 2);
38 mutex_unlock(&st->buf_lock);
39
40 return ret;
41 }
42
ade7758_spi_write_reg_16(struct device * dev,u8 reg_address,u16 value)43 static int ade7758_spi_write_reg_16(struct device *dev, u8 reg_address,
44 u16 value)
45 {
46 int ret;
47 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
48 struct ade7758_state *st = iio_priv(indio_dev);
49 struct spi_transfer xfers[] = {
50 {
51 .tx_buf = st->tx,
52 .bits_per_word = 8,
53 .len = 3,
54 }
55 };
56
57 mutex_lock(&st->buf_lock);
58 st->tx[0] = ADE7758_WRITE_REG(reg_address);
59 st->tx[1] = (value >> 8) & 0xFF;
60 st->tx[2] = value & 0xFF;
61
62 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
63 mutex_unlock(&st->buf_lock);
64
65 return ret;
66 }
67
ade7758_spi_write_reg_24(struct device * dev,u8 reg_address,u32 value)68 static int ade7758_spi_write_reg_24(struct device *dev, u8 reg_address,
69 u32 value)
70 {
71 int ret;
72 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
73 struct ade7758_state *st = iio_priv(indio_dev);
74 struct spi_transfer xfers[] = {
75 {
76 .tx_buf = st->tx,
77 .bits_per_word = 8,
78 .len = 4,
79 }
80 };
81
82 mutex_lock(&st->buf_lock);
83 st->tx[0] = ADE7758_WRITE_REG(reg_address);
84 st->tx[1] = (value >> 16) & 0xFF;
85 st->tx[2] = (value >> 8) & 0xFF;
86 st->tx[3] = value & 0xFF;
87
88 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
89 mutex_unlock(&st->buf_lock);
90
91 return ret;
92 }
93
ade7758_spi_read_reg_8(struct device * dev,u8 reg_address,u8 * val)94 int ade7758_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
95 {
96 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
97 struct ade7758_state *st = iio_priv(indio_dev);
98 int ret;
99 struct spi_transfer xfers[] = {
100 {
101 .tx_buf = st->tx,
102 .bits_per_word = 8,
103 .len = 1,
104 .delay_usecs = 4,
105 },
106 {
107 .tx_buf = &st->tx[1],
108 .rx_buf = st->rx,
109 .bits_per_word = 8,
110 .len = 1,
111 },
112 };
113
114 mutex_lock(&st->buf_lock);
115 st->tx[0] = ADE7758_READ_REG(reg_address);
116 st->tx[1] = 0;
117
118 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
119 if (ret) {
120 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
121 reg_address);
122 goto error_ret;
123 }
124 *val = st->rx[0];
125
126 error_ret:
127 mutex_unlock(&st->buf_lock);
128 return ret;
129 }
130
ade7758_spi_read_reg_16(struct device * dev,u8 reg_address,u16 * val)131 static int ade7758_spi_read_reg_16(struct device *dev, u8 reg_address,
132 u16 *val)
133 {
134 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
135 struct ade7758_state *st = iio_priv(indio_dev);
136 int ret;
137 struct spi_transfer xfers[] = {
138 {
139 .tx_buf = st->tx,
140 .bits_per_word = 8,
141 .len = 1,
142 .delay_usecs = 4,
143 },
144 {
145 .tx_buf = &st->tx[1],
146 .rx_buf = st->rx,
147 .bits_per_word = 8,
148 .len = 2,
149 },
150 };
151
152 mutex_lock(&st->buf_lock);
153 st->tx[0] = ADE7758_READ_REG(reg_address);
154 st->tx[1] = 0;
155 st->tx[2] = 0;
156
157 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
158 if (ret) {
159 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
160 reg_address);
161 goto error_ret;
162 }
163
164 *val = (st->rx[0] << 8) | st->rx[1];
165
166 error_ret:
167 mutex_unlock(&st->buf_lock);
168 return ret;
169 }
170
ade7758_spi_read_reg_24(struct device * dev,u8 reg_address,u32 * val)171 static int ade7758_spi_read_reg_24(struct device *dev, u8 reg_address,
172 u32 *val)
173 {
174 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
175 struct ade7758_state *st = iio_priv(indio_dev);
176 int ret;
177 struct spi_transfer xfers[] = {
178 {
179 .tx_buf = st->tx,
180 .bits_per_word = 8,
181 .len = 1,
182 .delay_usecs = 4,
183 },
184 {
185 .tx_buf = &st->tx[1],
186 .rx_buf = st->rx,
187 .bits_per_word = 8,
188 .len = 3,
189 },
190 };
191
192 mutex_lock(&st->buf_lock);
193 st->tx[0] = ADE7758_READ_REG(reg_address);
194 st->tx[1] = 0;
195 st->tx[2] = 0;
196 st->tx[3] = 0;
197
198 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
199 if (ret) {
200 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
201 reg_address);
202 goto error_ret;
203 }
204 *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
205
206 error_ret:
207 mutex_unlock(&st->buf_lock);
208 return ret;
209 }
210
ade7758_read_8bit(struct device * dev,struct device_attribute * attr,char * buf)211 static ssize_t ade7758_read_8bit(struct device *dev,
212 struct device_attribute *attr, char *buf)
213 {
214 int ret;
215 u8 val = 0;
216 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
217
218 ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val);
219 if (ret)
220 return ret;
221
222 return sprintf(buf, "%u\n", val);
223 }
224
ade7758_read_16bit(struct device * dev,struct device_attribute * attr,char * buf)225 static ssize_t ade7758_read_16bit(struct device *dev,
226 struct device_attribute *attr, char *buf)
227 {
228 int ret;
229 u16 val = 0;
230 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
231
232 ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val);
233 if (ret)
234 return ret;
235
236 return sprintf(buf, "%u\n", val);
237 }
238
ade7758_read_24bit(struct device * dev,struct device_attribute * attr,char * buf)239 static ssize_t ade7758_read_24bit(struct device *dev,
240 struct device_attribute *attr, char *buf)
241 {
242 int ret;
243 u32 val = 0;
244 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
245
246 ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val);
247 if (ret)
248 return ret;
249
250 return sprintf(buf, "%u\n", val & 0xFFFFFF);
251 }
252
ade7758_write_8bit(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)253 static ssize_t ade7758_write_8bit(struct device *dev,
254 struct device_attribute *attr,
255 const char *buf, size_t len)
256 {
257 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
258 int ret;
259 u8 val;
260
261 ret = kstrtou8(buf, 10, &val);
262 if (ret)
263 goto error_ret;
264 ret = ade7758_spi_write_reg_8(dev, this_attr->address, val);
265
266 error_ret:
267 return ret ? ret : len;
268 }
269
ade7758_write_16bit(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)270 static ssize_t ade7758_write_16bit(struct device *dev,
271 struct device_attribute *attr,
272 const char *buf, size_t len)
273 {
274 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
275 int ret;
276 u16 val;
277
278 ret = kstrtou16(buf, 10, &val);
279 if (ret)
280 goto error_ret;
281 ret = ade7758_spi_write_reg_16(dev, this_attr->address, val);
282
283 error_ret:
284 return ret ? ret : len;
285 }
286
ade7758_reset(struct device * dev)287 static int ade7758_reset(struct device *dev)
288 {
289 int ret;
290 u8 val;
291
292 ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
293 if (ret < 0) {
294 dev_err(dev, "Failed to read opmode reg\n");
295 return ret;
296 }
297 val |= BIT(6); /* Software Chip Reset */
298 ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
299 if (ret < 0)
300 dev_err(dev, "Failed to write opmode reg\n");
301 return ret;
302 }
303
304 static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO,
305 ade7758_read_8bit,
306 ade7758_write_8bit,
307 ADE7758_VPEAK);
308 static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO,
309 ade7758_read_8bit,
310 ade7758_write_8bit,
311 ADE7758_VPEAK);
312 static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO,
313 ade7758_read_8bit,
314 ade7758_write_8bit,
315 ADE7758_APHCAL);
316 static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO,
317 ade7758_read_8bit,
318 ade7758_write_8bit,
319 ADE7758_BPHCAL);
320 static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO,
321 ade7758_read_8bit,
322 ade7758_write_8bit,
323 ADE7758_CPHCAL);
324 static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO,
325 ade7758_read_8bit,
326 ade7758_write_8bit,
327 ADE7758_WDIV);
328 static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO,
329 ade7758_read_8bit,
330 ade7758_write_8bit,
331 ADE7758_VADIV);
332 static IIO_DEV_ATTR_AIRMS(S_IRUGO,
333 ade7758_read_24bit,
334 NULL,
335 ADE7758_AIRMS);
336 static IIO_DEV_ATTR_BIRMS(S_IRUGO,
337 ade7758_read_24bit,
338 NULL,
339 ADE7758_BIRMS);
340 static IIO_DEV_ATTR_CIRMS(S_IRUGO,
341 ade7758_read_24bit,
342 NULL,
343 ADE7758_CIRMS);
344 static IIO_DEV_ATTR_AVRMS(S_IRUGO,
345 ade7758_read_24bit,
346 NULL,
347 ADE7758_AVRMS);
348 static IIO_DEV_ATTR_BVRMS(S_IRUGO,
349 ade7758_read_24bit,
350 NULL,
351 ADE7758_BVRMS);
352 static IIO_DEV_ATTR_CVRMS(S_IRUGO,
353 ade7758_read_24bit,
354 NULL,
355 ADE7758_CVRMS);
356 static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO,
357 ade7758_read_16bit,
358 ade7758_write_16bit,
359 ADE7758_AIRMSOS);
360 static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO,
361 ade7758_read_16bit,
362 ade7758_write_16bit,
363 ADE7758_BIRMSOS);
364 static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO,
365 ade7758_read_16bit,
366 ade7758_write_16bit,
367 ADE7758_CIRMSOS);
368 static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO,
369 ade7758_read_16bit,
370 ade7758_write_16bit,
371 ADE7758_AVRMSOS);
372 static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO,
373 ade7758_read_16bit,
374 ade7758_write_16bit,
375 ADE7758_BVRMSOS);
376 static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO,
377 ade7758_read_16bit,
378 ade7758_write_16bit,
379 ADE7758_CVRMSOS);
380 static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO,
381 ade7758_read_16bit,
382 ade7758_write_16bit,
383 ADE7758_AIGAIN);
384 static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO,
385 ade7758_read_16bit,
386 ade7758_write_16bit,
387 ADE7758_BIGAIN);
388 static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO,
389 ade7758_read_16bit,
390 ade7758_write_16bit,
391 ADE7758_CIGAIN);
392 static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO,
393 ade7758_read_16bit,
394 ade7758_write_16bit,
395 ADE7758_AVRMSGAIN);
396 static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO,
397 ade7758_read_16bit,
398 ade7758_write_16bit,
399 ADE7758_BVRMSGAIN);
400 static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO,
401 ade7758_read_16bit,
402 ade7758_write_16bit,
403 ADE7758_CVRMSGAIN);
404
ade7758_set_irq(struct device * dev,bool enable)405 int ade7758_set_irq(struct device *dev, bool enable)
406 {
407 int ret;
408 u32 irqen;
409
410 ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen);
411 if (ret)
412 return ret;
413
414 if (enable)
415 irqen |= BIT(16); /* Enables an interrupt when a data is
416 * present in the waveform register
417 */
418 else
419 irqen &= ~BIT(16);
420
421 ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen);
422
423 return ret;
424 }
425
426 /* Power down the device */
ade7758_stop_device(struct device * dev)427 static int ade7758_stop_device(struct device *dev)
428 {
429 int ret;
430 u8 val;
431
432 ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
433 if (ret < 0) {
434 dev_err(dev, "Failed to read opmode reg\n");
435 return ret;
436 }
437 val |= 7 << 3; /* ADE7758 powered down */
438 ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
439 if (ret < 0)
440 dev_err(dev, "Failed to write opmode reg\n");
441 return ret;
442 }
443
ade7758_initial_setup(struct iio_dev * indio_dev)444 static int ade7758_initial_setup(struct iio_dev *indio_dev)
445 {
446 struct ade7758_state *st = iio_priv(indio_dev);
447 struct device *dev = &indio_dev->dev;
448 int ret;
449
450 /* use low spi speed for init */
451 st->us->mode = SPI_MODE_1;
452 spi_setup(st->us);
453
454 /* Disable IRQ */
455 ret = ade7758_set_irq(dev, false);
456 if (ret) {
457 dev_err(dev, "disable irq failed");
458 goto err_ret;
459 }
460
461 ade7758_reset(dev);
462 msleep(ADE7758_STARTUP_DELAY);
463
464 err_ret:
465 return ret;
466 }
467
ade7758_read_frequency(struct device * dev,struct device_attribute * attr,char * buf)468 static ssize_t ade7758_read_frequency(struct device *dev,
469 struct device_attribute *attr, char *buf)
470 {
471 int ret;
472 u8 t;
473 int sps;
474
475 ret = ade7758_spi_read_reg_8(dev, ADE7758_WAVMODE, &t);
476 if (ret)
477 return ret;
478
479 t = (t >> 5) & 0x3;
480 sps = 26040 / (1 << t);
481
482 return sprintf(buf, "%d SPS\n", sps);
483 }
484
ade7758_write_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)485 static ssize_t ade7758_write_frequency(struct device *dev,
486 struct device_attribute *attr,
487 const char *buf, size_t len)
488 {
489 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
490 u16 val;
491 int ret;
492 u8 reg, t;
493
494 ret = kstrtou16(buf, 10, &val);
495 if (ret)
496 return ret;
497
498 mutex_lock(&indio_dev->mlock);
499
500 switch (val) {
501 case 26040:
502 t = 0;
503 break;
504 case 13020:
505 t = 1;
506 break;
507 case 6510:
508 t = 2;
509 break;
510 case 3255:
511 t = 3;
512 break;
513 default:
514 ret = -EINVAL;
515 goto out;
516 }
517
518 ret = ade7758_spi_read_reg_8(dev, ADE7758_WAVMODE, ®);
519 if (ret)
520 goto out;
521
522 reg &= ~(5 << 3);
523 reg |= t << 5;
524
525 ret = ade7758_spi_write_reg_8(dev, ADE7758_WAVMODE, reg);
526
527 out:
528 mutex_unlock(&indio_dev->mlock);
529
530 return ret ? ret : len;
531 }
532
533 static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
534 static IIO_CONST_ATTR(in_temp_offset, "129 C");
535 static IIO_CONST_ATTR(in_temp_scale, "4 C");
536
537 static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit,
538 ADE7758_AWATTHR);
539 static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit,
540 ADE7758_BWATTHR);
541 static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit,
542 ADE7758_CWATTHR);
543 static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit,
544 ADE7758_AVARHR);
545 static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit,
546 ADE7758_BVARHR);
547 static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit,
548 ADE7758_CVARHR);
549 static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit,
550 ADE7758_AVAHR);
551 static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit,
552 ADE7758_BVAHR);
553 static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit,
554 ADE7758_CVAHR);
555
556 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
557 ade7758_read_frequency,
558 ade7758_write_frequency);
559
560 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
561
562 static struct attribute *ade7758_attributes[] = {
563 &iio_dev_attr_in_temp_raw.dev_attr.attr,
564 &iio_const_attr_in_temp_offset.dev_attr.attr,
565 &iio_const_attr_in_temp_scale.dev_attr.attr,
566 &iio_dev_attr_sampling_frequency.dev_attr.attr,
567 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
568 &iio_dev_attr_awatthr.dev_attr.attr,
569 &iio_dev_attr_bwatthr.dev_attr.attr,
570 &iio_dev_attr_cwatthr.dev_attr.attr,
571 &iio_dev_attr_avarhr.dev_attr.attr,
572 &iio_dev_attr_bvarhr.dev_attr.attr,
573 &iio_dev_attr_cvarhr.dev_attr.attr,
574 &iio_dev_attr_avahr.dev_attr.attr,
575 &iio_dev_attr_bvahr.dev_attr.attr,
576 &iio_dev_attr_cvahr.dev_attr.attr,
577 &iio_dev_attr_vpeak.dev_attr.attr,
578 &iio_dev_attr_ipeak.dev_attr.attr,
579 &iio_dev_attr_aphcal.dev_attr.attr,
580 &iio_dev_attr_bphcal.dev_attr.attr,
581 &iio_dev_attr_cphcal.dev_attr.attr,
582 &iio_dev_attr_wdiv.dev_attr.attr,
583 &iio_dev_attr_vadiv.dev_attr.attr,
584 &iio_dev_attr_airms.dev_attr.attr,
585 &iio_dev_attr_birms.dev_attr.attr,
586 &iio_dev_attr_cirms.dev_attr.attr,
587 &iio_dev_attr_avrms.dev_attr.attr,
588 &iio_dev_attr_bvrms.dev_attr.attr,
589 &iio_dev_attr_cvrms.dev_attr.attr,
590 &iio_dev_attr_aigain.dev_attr.attr,
591 &iio_dev_attr_bigain.dev_attr.attr,
592 &iio_dev_attr_cigain.dev_attr.attr,
593 &iio_dev_attr_avrmsgain.dev_attr.attr,
594 &iio_dev_attr_bvrmsgain.dev_attr.attr,
595 &iio_dev_attr_cvrmsgain.dev_attr.attr,
596 &iio_dev_attr_airmsos.dev_attr.attr,
597 &iio_dev_attr_birmsos.dev_attr.attr,
598 &iio_dev_attr_cirmsos.dev_attr.attr,
599 &iio_dev_attr_avrmsos.dev_attr.attr,
600 &iio_dev_attr_bvrmsos.dev_attr.attr,
601 &iio_dev_attr_cvrmsos.dev_attr.attr,
602 NULL,
603 };
604
605 static const struct attribute_group ade7758_attribute_group = {
606 .attrs = ade7758_attributes,
607 };
608
609 static const struct iio_chan_spec ade7758_channels[] = {
610 {
611 .type = IIO_VOLTAGE,
612 .indexed = 1,
613 .channel = 0,
614 .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
615 .scan_index = 0,
616 .scan_type = {
617 .sign = 's',
618 .realbits = 24,
619 .storagebits = 32,
620 },
621 }, {
622 .type = IIO_CURRENT,
623 .indexed = 1,
624 .channel = 0,
625 .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
626 .scan_index = 1,
627 .scan_type = {
628 .sign = 's',
629 .realbits = 24,
630 .storagebits = 32,
631 },
632 }, {
633 .type = IIO_POWER,
634 .indexed = 1,
635 .channel = 0,
636 .extend_name = "apparent",
637 .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
638 .scan_index = 2,
639 .scan_type = {
640 .sign = 's',
641 .realbits = 24,
642 .storagebits = 32,
643 },
644 }, {
645 .type = IIO_POWER,
646 .indexed = 1,
647 .channel = 0,
648 .extend_name = "active",
649 .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
650 .scan_index = 3,
651 .scan_type = {
652 .sign = 's',
653 .realbits = 24,
654 .storagebits = 32,
655 },
656 }, {
657 .type = IIO_POWER,
658 .indexed = 1,
659 .channel = 0,
660 .extend_name = "reactive",
661 .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
662 .scan_index = 4,
663 .scan_type = {
664 .sign = 's',
665 .realbits = 24,
666 .storagebits = 32,
667 },
668 }, {
669 .type = IIO_VOLTAGE,
670 .indexed = 1,
671 .channel = 1,
672 .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
673 .scan_index = 5,
674 .scan_type = {
675 .sign = 's',
676 .realbits = 24,
677 .storagebits = 32,
678 },
679 }, {
680 .type = IIO_CURRENT,
681 .indexed = 1,
682 .channel = 1,
683 .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
684 .scan_index = 6,
685 .scan_type = {
686 .sign = 's',
687 .realbits = 24,
688 .storagebits = 32,
689 },
690 }, {
691 .type = IIO_POWER,
692 .indexed = 1,
693 .channel = 1,
694 .extend_name = "apparent",
695 .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
696 .scan_index = 7,
697 .scan_type = {
698 .sign = 's',
699 .realbits = 24,
700 .storagebits = 32,
701 },
702 }, {
703 .type = IIO_POWER,
704 .indexed = 1,
705 .channel = 1,
706 .extend_name = "active",
707 .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
708 .scan_index = 8,
709 .scan_type = {
710 .sign = 's',
711 .realbits = 24,
712 .storagebits = 32,
713 },
714 }, {
715 .type = IIO_POWER,
716 .indexed = 1,
717 .channel = 1,
718 .extend_name = "reactive",
719 .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
720 .scan_index = 9,
721 .scan_type = {
722 .sign = 's',
723 .realbits = 24,
724 .storagebits = 32,
725 },
726 }, {
727 .type = IIO_VOLTAGE,
728 .indexed = 1,
729 .channel = 2,
730 .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
731 .scan_index = 10,
732 .scan_type = {
733 .sign = 's',
734 .realbits = 24,
735 .storagebits = 32,
736 },
737 }, {
738 .type = IIO_CURRENT,
739 .indexed = 1,
740 .channel = 2,
741 .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
742 .scan_index = 11,
743 .scan_type = {
744 .sign = 's',
745 .realbits = 24,
746 .storagebits = 32,
747 },
748 }, {
749 .type = IIO_POWER,
750 .indexed = 1,
751 .channel = 2,
752 .extend_name = "apparent",
753 .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
754 .scan_index = 12,
755 .scan_type = {
756 .sign = 's',
757 .realbits = 24,
758 .storagebits = 32,
759 },
760 }, {
761 .type = IIO_POWER,
762 .indexed = 1,
763 .channel = 2,
764 .extend_name = "active",
765 .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
766 .scan_index = 13,
767 .scan_type = {
768 .sign = 's',
769 .realbits = 24,
770 .storagebits = 32,
771 },
772 }, {
773 .type = IIO_POWER,
774 .indexed = 1,
775 .channel = 2,
776 .extend_name = "reactive",
777 .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
778 .scan_index = 14,
779 .scan_type = {
780 .sign = 's',
781 .realbits = 24,
782 .storagebits = 32,
783 },
784 },
785 IIO_CHAN_SOFT_TIMESTAMP(15),
786 };
787
788 static const struct iio_info ade7758_info = {
789 .attrs = &ade7758_attribute_group,
790 .driver_module = THIS_MODULE,
791 };
792
ade7758_probe(struct spi_device * spi)793 static int ade7758_probe(struct spi_device *spi)
794 {
795 int ret;
796 struct ade7758_state *st;
797 struct iio_dev *indio_dev;
798
799 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
800 if (!indio_dev)
801 return -ENOMEM;
802
803 st = iio_priv(indio_dev);
804 /* this is only used for removal purposes */
805 spi_set_drvdata(spi, indio_dev);
806
807 /* Allocate the comms buffers */
808 st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL);
809 if (!st->rx)
810 return -ENOMEM;
811 st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL);
812 if (!st->tx) {
813 ret = -ENOMEM;
814 goto error_free_rx;
815 }
816 st->us = spi;
817 mutex_init(&st->buf_lock);
818
819 indio_dev->name = spi->dev.driver->name;
820 indio_dev->dev.parent = &spi->dev;
821 indio_dev->info = &ade7758_info;
822 indio_dev->modes = INDIO_DIRECT_MODE;
823 indio_dev->channels = ade7758_channels;
824 indio_dev->num_channels = ARRAY_SIZE(ade7758_channels);
825
826 ret = ade7758_configure_ring(indio_dev);
827 if (ret)
828 goto error_free_tx;
829
830 /* Get the device into a sane initial state */
831 ret = ade7758_initial_setup(indio_dev);
832 if (ret)
833 goto error_unreg_ring_funcs;
834
835 if (spi->irq) {
836 ret = ade7758_probe_trigger(indio_dev);
837 if (ret)
838 goto error_unreg_ring_funcs;
839 }
840
841 ret = iio_device_register(indio_dev);
842 if (ret)
843 goto error_remove_trigger;
844
845 return 0;
846
847 error_remove_trigger:
848 if (spi->irq)
849 ade7758_remove_trigger(indio_dev);
850 error_unreg_ring_funcs:
851 ade7758_unconfigure_ring(indio_dev);
852 error_free_tx:
853 kfree(st->tx);
854 error_free_rx:
855 kfree(st->rx);
856 return ret;
857 }
858
ade7758_remove(struct spi_device * spi)859 static int ade7758_remove(struct spi_device *spi)
860 {
861 struct iio_dev *indio_dev = spi_get_drvdata(spi);
862 struct ade7758_state *st = iio_priv(indio_dev);
863
864 iio_device_unregister(indio_dev);
865 ade7758_stop_device(&indio_dev->dev);
866 ade7758_remove_trigger(indio_dev);
867 ade7758_unconfigure_ring(indio_dev);
868 kfree(st->tx);
869 kfree(st->rx);
870
871 return 0;
872 }
873
874 static const struct spi_device_id ade7758_id[] = {
875 {"ade7758", 0},
876 {}
877 };
878 MODULE_DEVICE_TABLE(spi, ade7758_id);
879
880 static struct spi_driver ade7758_driver = {
881 .driver = {
882 .name = "ade7758",
883 },
884 .probe = ade7758_probe,
885 .remove = ade7758_remove,
886 .id_table = ade7758_id,
887 };
888 module_spi_driver(ade7758_driver);
889
890 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
891 MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver");
892 MODULE_LICENSE("GPL v2");
893