1 #include <linux/export.h>
2 #include <linux/bitops.h>
3 #include <linux/elf.h>
4 #include <linux/mm.h>
5
6 #include <linux/io.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
10 #include <asm/apic.h>
11 #include <asm/cpu.h>
12 #include <asm/smp.h>
13 #include <asm/pci-direct.h>
14 #include <asm/delay.h>
15
16 #ifdef CONFIG_X86_64
17 # include <asm/mmconfig.h>
18 # include <asm/cacheflush.h>
19 #endif
20
21 #include "cpu.h"
22
23 static const int amd_erratum_383[];
24 static const int amd_erratum_400[];
25 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
26
27 /*
28 * nodes_per_socket: Stores the number of nodes per socket.
29 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
30 * Node Identifiers[10:8]
31 */
32 static u32 nodes_per_socket = 1;
33
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)34 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
35 {
36 u32 gprs[8] = { 0 };
37 int err;
38
39 WARN_ONCE((boot_cpu_data.x86 != 0xf),
40 "%s should only be used on K8!\n", __func__);
41
42 gprs[1] = msr;
43 gprs[7] = 0x9c5a203a;
44
45 err = rdmsr_safe_regs(gprs);
46
47 *p = gprs[0] | ((u64)gprs[2] << 32);
48
49 return err;
50 }
51
wrmsrl_amd_safe(unsigned msr,unsigned long long val)52 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
53 {
54 u32 gprs[8] = { 0 };
55
56 WARN_ONCE((boot_cpu_data.x86 != 0xf),
57 "%s should only be used on K8!\n", __func__);
58
59 gprs[0] = (u32)val;
60 gprs[1] = msr;
61 gprs[2] = val >> 32;
62 gprs[7] = 0x9c5a203a;
63
64 return wrmsr_safe_regs(gprs);
65 }
66
67 /*
68 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
69 * misexecution of code under Linux. Owners of such processors should
70 * contact AMD for precise details and a CPU swap.
71 *
72 * See http://www.multimania.com/poulot/k6bug.html
73 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
74 * (Publication # 21266 Issue Date: August 1998)
75 *
76 * The following test is erm.. interesting. AMD neglected to up
77 * the chip setting when fixing the bug but they also tweaked some
78 * performance at the same time..
79 */
80
81 extern __visible void vide(void);
82 __asm__(".globl vide\n"
83 ".type vide, @function\n"
84 ".align 4\n"
85 "vide: ret\n");
86
init_amd_k5(struct cpuinfo_x86 * c)87 static void init_amd_k5(struct cpuinfo_x86 *c)
88 {
89 #ifdef CONFIG_X86_32
90 /*
91 * General Systems BIOSen alias the cpu frequency registers
92 * of the Elan at 0x000df000. Unfortunately, one of the Linux
93 * drivers subsequently pokes it, and changes the CPU speed.
94 * Workaround : Remove the unneeded alias.
95 */
96 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
97 #define CBAR_ENB (0x80000000)
98 #define CBAR_KEY (0X000000CB)
99 if (c->x86_model == 9 || c->x86_model == 10) {
100 if (inl(CBAR) & CBAR_ENB)
101 outl(0 | CBAR_KEY, CBAR);
102 }
103 #endif
104 }
105
init_amd_k6(struct cpuinfo_x86 * c)106 static void init_amd_k6(struct cpuinfo_x86 *c)
107 {
108 #ifdef CONFIG_X86_32
109 u32 l, h;
110 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
111
112 if (c->x86_model < 6) {
113 /* Based on AMD doc 20734R - June 2000 */
114 if (c->x86_model == 0) {
115 clear_cpu_cap(c, X86_FEATURE_APIC);
116 set_cpu_cap(c, X86_FEATURE_PGE);
117 }
118 return;
119 }
120
121 if (c->x86_model == 6 && c->x86_stepping == 1) {
122 const int K6_BUG_LOOP = 1000000;
123 int n;
124 void (*f_vide)(void);
125 u64 d, d2;
126
127 pr_info("AMD K6 stepping B detected - ");
128
129 /*
130 * It looks like AMD fixed the 2.6.2 bug and improved indirect
131 * calls at the same time.
132 */
133
134 n = K6_BUG_LOOP;
135 f_vide = vide;
136 d = rdtsc();
137 while (n--)
138 f_vide();
139 d2 = rdtsc();
140 d = d2-d;
141
142 if (d > 20*K6_BUG_LOOP)
143 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
144 else
145 pr_cont("probably OK (after B9730xxxx).\n");
146 }
147
148 /* K6 with old style WHCR */
149 if (c->x86_model < 8 ||
150 (c->x86_model == 8 && c->x86_stepping < 8)) {
151 /* We can only write allocate on the low 508Mb */
152 if (mbytes > 508)
153 mbytes = 508;
154
155 rdmsr(MSR_K6_WHCR, l, h);
156 if ((l&0x0000FFFF) == 0) {
157 unsigned long flags;
158 l = (1<<0)|((mbytes/4)<<1);
159 local_irq_save(flags);
160 wbinvd();
161 wrmsr(MSR_K6_WHCR, l, h);
162 local_irq_restore(flags);
163 pr_info("Enabling old style K6 write allocation for %d Mb\n",
164 mbytes);
165 }
166 return;
167 }
168
169 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
170 c->x86_model == 9 || c->x86_model == 13) {
171 /* The more serious chips .. */
172
173 if (mbytes > 4092)
174 mbytes = 4092;
175
176 rdmsr(MSR_K6_WHCR, l, h);
177 if ((l&0xFFFF0000) == 0) {
178 unsigned long flags;
179 l = ((mbytes>>2)<<22)|(1<<16);
180 local_irq_save(flags);
181 wbinvd();
182 wrmsr(MSR_K6_WHCR, l, h);
183 local_irq_restore(flags);
184 pr_info("Enabling new style K6 write allocation for %d Mb\n",
185 mbytes);
186 }
187
188 return;
189 }
190
191 if (c->x86_model == 10) {
192 /* AMD Geode LX is model 10 */
193 /* placeholder for any needed mods */
194 return;
195 }
196 #endif
197 }
198
init_amd_k7(struct cpuinfo_x86 * c)199 static void init_amd_k7(struct cpuinfo_x86 *c)
200 {
201 #ifdef CONFIG_X86_32
202 u32 l, h;
203
204 /*
205 * Bit 15 of Athlon specific MSR 15, needs to be 0
206 * to enable SSE on Palomino/Morgan/Barton CPU's.
207 * If the BIOS didn't enable it already, enable it here.
208 */
209 if (c->x86_model >= 6 && c->x86_model <= 10) {
210 if (!cpu_has(c, X86_FEATURE_XMM)) {
211 pr_info("Enabling disabled K7/SSE Support.\n");
212 msr_clear_bit(MSR_K7_HWCR, 15);
213 set_cpu_cap(c, X86_FEATURE_XMM);
214 }
215 }
216
217 /*
218 * It's been determined by AMD that Athlons since model 8 stepping 1
219 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
220 * As per AMD technical note 27212 0.2
221 */
222 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
223 rdmsr(MSR_K7_CLK_CTL, l, h);
224 if ((l & 0xfff00000) != 0x20000000) {
225 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
226 l, ((l & 0x000fffff)|0x20000000));
227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
228 }
229 }
230
231 set_cpu_cap(c, X86_FEATURE_K7);
232
233 /* calling is from identify_secondary_cpu() ? */
234 if (!c->cpu_index)
235 return;
236
237 /*
238 * Certain Athlons might work (for various values of 'work') in SMP
239 * but they are not certified as MP capable.
240 */
241 /* Athlon 660/661 is valid. */
242 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
243 (c->x86_stepping == 1)))
244 return;
245
246 /* Duron 670 is valid */
247 if ((c->x86_model == 7) && (c->x86_stepping == 0))
248 return;
249
250 /*
251 * Athlon 662, Duron 671, and Athlon >model 7 have capability
252 * bit. It's worth noting that the A5 stepping (662) of some
253 * Athlon XP's have the MP bit set.
254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
255 * more.
256 */
257 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
258 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
259 (c->x86_model > 7))
260 if (cpu_has(c, X86_FEATURE_MP))
261 return;
262
263 /* If we get here, not a certified SMP capable AMD system. */
264
265 /*
266 * Don't taint if we are running SMP kernel on a single non-MP
267 * approved Athlon
268 */
269 WARN_ONCE(1, "WARNING: This combination of AMD"
270 " processors is not suitable for SMP.\n");
271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
272 #endif
273 }
274
275 #ifdef CONFIG_NUMA
276 /*
277 * To workaround broken NUMA config. Read the comment in
278 * srat_detect_node().
279 */
nearby_node(int apicid)280 static int nearby_node(int apicid)
281 {
282 int i, node;
283
284 for (i = apicid - 1; i >= 0; i--) {
285 node = __apicid_to_node[i];
286 if (node != NUMA_NO_NODE && node_online(node))
287 return node;
288 }
289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
290 node = __apicid_to_node[i];
291 if (node != NUMA_NO_NODE && node_online(node))
292 return node;
293 }
294 return first_node(node_online_map); /* Shouldn't happen */
295 }
296 #endif
297
298 /*
299 * Fixup core topology information for
300 * (1) AMD multi-node processors
301 * Assumption: Number of cores in each internal node is the same.
302 * (2) AMD processors supporting compute units
303 */
304 #ifdef CONFIG_SMP
amd_get_topology(struct cpuinfo_x86 * c)305 static void amd_get_topology(struct cpuinfo_x86 *c)
306 {
307 u8 node_id;
308 int cpu = smp_processor_id();
309
310 /* get information required for multi-node processors */
311 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
312 u32 eax, ebx, ecx, edx;
313
314 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
315
316 node_id = ecx & 0xff;
317 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
318
319 if (c->x86 == 0x15)
320 c->cu_id = ebx & 0xff;
321
322 if (c->x86 >= 0x17) {
323 c->cpu_core_id = ebx & 0xff;
324
325 if (smp_num_siblings > 1)
326 c->x86_max_cores /= smp_num_siblings;
327 }
328
329 /*
330 * We may have multiple LLCs if L3 caches exist, so check if we
331 * have an L3 cache by looking at the L3 cache CPUID leaf.
332 */
333 if (cpuid_edx(0x80000006)) {
334 if (c->x86 == 0x17) {
335 /*
336 * LLC is at the core complex level.
337 * Core complex id is ApicId[3].
338 */
339 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
340 } else {
341 /* LLC is at the node level. */
342 per_cpu(cpu_llc_id, cpu) = node_id;
343 }
344 }
345 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
346 u64 value;
347
348 rdmsrl(MSR_FAM10H_NODE_ID, value);
349 node_id = value & 7;
350
351 per_cpu(cpu_llc_id, cpu) = node_id;
352 } else
353 return;
354
355 /* fixup multi-node processor information */
356 if (nodes_per_socket > 1) {
357 u32 cus_per_node;
358
359 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
360 cus_per_node = c->x86_max_cores / nodes_per_socket;
361
362 /* core id has to be in the [0 .. cores_per_node - 1] range */
363 c->cpu_core_id %= cus_per_node;
364 }
365 }
366 #endif
367
368 /*
369 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
370 * Assumes number of cores is a power of two.
371 */
amd_detect_cmp(struct cpuinfo_x86 * c)372 static void amd_detect_cmp(struct cpuinfo_x86 *c)
373 {
374 #ifdef CONFIG_SMP
375 unsigned bits;
376 int cpu = smp_processor_id();
377
378 bits = c->x86_coreid_bits;
379 /* Low order bits define the core id (index of core in socket) */
380 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
381 /* Convert the initial APIC ID into the socket ID */
382 c->phys_proc_id = c->initial_apicid >> bits;
383 /* use socket ID also for last level cache */
384 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
385 amd_get_topology(c);
386 #endif
387 }
388
amd_get_nb_id(int cpu)389 u16 amd_get_nb_id(int cpu)
390 {
391 u16 id = 0;
392 #ifdef CONFIG_SMP
393 id = per_cpu(cpu_llc_id, cpu);
394 #endif
395 return id;
396 }
397 EXPORT_SYMBOL_GPL(amd_get_nb_id);
398
amd_get_nodes_per_socket(void)399 u32 amd_get_nodes_per_socket(void)
400 {
401 return nodes_per_socket;
402 }
403 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
404
srat_detect_node(struct cpuinfo_x86 * c)405 static void srat_detect_node(struct cpuinfo_x86 *c)
406 {
407 #ifdef CONFIG_NUMA
408 int cpu = smp_processor_id();
409 int node;
410 unsigned apicid = c->apicid;
411
412 node = numa_cpu_node(cpu);
413 if (node == NUMA_NO_NODE)
414 node = per_cpu(cpu_llc_id, cpu);
415
416 /*
417 * On multi-fabric platform (e.g. Numascale NumaChip) a
418 * platform-specific handler needs to be called to fixup some
419 * IDs of the CPU.
420 */
421 if (x86_cpuinit.fixup_cpu_id)
422 x86_cpuinit.fixup_cpu_id(c, node);
423
424 if (!node_online(node)) {
425 /*
426 * Two possibilities here:
427 *
428 * - The CPU is missing memory and no node was created. In
429 * that case try picking one from a nearby CPU.
430 *
431 * - The APIC IDs differ from the HyperTransport node IDs
432 * which the K8 northbridge parsing fills in. Assume
433 * they are all increased by a constant offset, but in
434 * the same order as the HT nodeids. If that doesn't
435 * result in a usable node fall back to the path for the
436 * previous case.
437 *
438 * This workaround operates directly on the mapping between
439 * APIC ID and NUMA node, assuming certain relationship
440 * between APIC ID, HT node ID and NUMA topology. As going
441 * through CPU mapping may alter the outcome, directly
442 * access __apicid_to_node[].
443 */
444 int ht_nodeid = c->initial_apicid;
445
446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
447 node = __apicid_to_node[ht_nodeid];
448 /* Pick a nearby node */
449 if (!node_online(node))
450 node = nearby_node(apicid);
451 }
452 numa_set_node(cpu, node);
453 #endif
454 }
455
early_init_amd_mc(struct cpuinfo_x86 * c)456 static void early_init_amd_mc(struct cpuinfo_x86 *c)
457 {
458 #ifdef CONFIG_SMP
459 unsigned bits, ecx;
460
461 /* Multi core CPU? */
462 if (c->extended_cpuid_level < 0x80000008)
463 return;
464
465 ecx = cpuid_ecx(0x80000008);
466
467 c->x86_max_cores = (ecx & 0xff) + 1;
468
469 /* CPU telling us the core id bits shift? */
470 bits = (ecx >> 12) & 0xF;
471
472 /* Otherwise recompute */
473 if (bits == 0) {
474 while ((1 << bits) < c->x86_max_cores)
475 bits++;
476 }
477
478 c->x86_coreid_bits = bits;
479 #endif
480 }
481
bsp_init_amd(struct cpuinfo_x86 * c)482 static void bsp_init_amd(struct cpuinfo_x86 *c)
483 {
484
485 #ifdef CONFIG_X86_64
486 if (c->x86 >= 0xf) {
487 unsigned long long tseg;
488
489 /*
490 * Split up direct mapping around the TSEG SMM area.
491 * Don't do it for gbpages because there seems very little
492 * benefit in doing so.
493 */
494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
495 unsigned long pfn = tseg >> PAGE_SHIFT;
496
497 pr_debug("tseg: %010llx\n", tseg);
498 if (pfn_range_is_mapped(pfn, pfn + 1))
499 set_memory_4k((unsigned long)__va(tseg), 1);
500 }
501 }
502 #endif
503
504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
505
506 if (c->x86 > 0x10 ||
507 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
508 u64 val;
509
510 rdmsrl(MSR_K7_HWCR, val);
511 if (!(val & BIT(24)))
512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
513 }
514 }
515
516 if (c->x86 == 0x15) {
517 unsigned long upperbit;
518 u32 cpuid, assoc;
519
520 cpuid = cpuid_edx(0x80000005);
521 assoc = cpuid >> 16 & 0xff;
522 upperbit = ((cpuid >> 24) << 10) / assoc;
523
524 va_align.mask = (upperbit - 1) & PAGE_MASK;
525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
526
527 /* A random value per boot for bit slice [12:upper_bit) */
528 va_align.bits = get_random_int() & va_align.mask;
529 }
530
531 if (cpu_has(c, X86_FEATURE_MWAITX))
532 use_mwaitx_delay();
533
534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
535 u32 ecx;
536
537 ecx = cpuid_ecx(0x8000001e);
538 nodes_per_socket = ((ecx >> 8) & 7) + 1;
539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
540 u64 value;
541
542 rdmsrl(MSR_FAM10H_NODE_ID, value);
543 nodes_per_socket = ((value >> 3) & 7) + 1;
544 }
545 }
546
early_init_amd(struct cpuinfo_x86 * c)547 static void early_init_amd(struct cpuinfo_x86 *c)
548 {
549 early_init_amd_mc(c);
550
551 /*
552 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
553 * with P/T states and does not stop in deep C-states
554 */
555 if (c->x86_power & (1 << 8)) {
556 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
557 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
558 if (!check_tsc_unstable())
559 set_sched_clock_stable();
560 }
561
562 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
563 if (c->x86_power & BIT(12))
564 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
565
566 #ifdef CONFIG_X86_64
567 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
568 #else
569 /* Set MTRR capability flag if appropriate */
570 if (c->x86 == 5)
571 if (c->x86_model == 13 || c->x86_model == 9 ||
572 (c->x86_model == 8 && c->x86_stepping >= 8))
573 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
574 #endif
575 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
576 /*
577 * ApicID can always be treated as an 8-bit value for AMD APIC versions
578 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
579 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
580 * after 16h.
581 */
582 if (boot_cpu_has(X86_FEATURE_APIC)) {
583 if (c->x86 > 0x16)
584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
585 else if (c->x86 >= 0xf) {
586 /* check CPU config space for extended APIC ID */
587 unsigned int val;
588
589 val = read_pci_config(0, 24, 0, 0x68);
590 if ((val >> 17 & 0x3) == 0x3)
591 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
592 }
593 }
594 #endif
595
596 /*
597 * This is only needed to tell the kernel whether to use VMCALL
598 * and VMMCALL. VMMCALL is never executed except under virt, so
599 * we can set it unconditionally.
600 */
601 set_cpu_cap(c, X86_FEATURE_VMMCALL);
602
603 /* F16h erratum 793, CVE-2013-6885 */
604 if (c->x86 == 0x16 && c->x86_model <= 0xf)
605 msr_set_bit(MSR_AMD64_LS_CFG, 15);
606
607 /*
608 * Check whether the machine is affected by erratum 400. This is
609 * used to select the proper idle routine and to enable the check
610 * whether the machine is affected in arch_post_acpi_init(), which
611 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
612 */
613 if (cpu_has_amd_erratum(c, amd_erratum_400))
614 set_cpu_bug(c, X86_BUG_AMD_E400);
615 }
616
init_amd_k8(struct cpuinfo_x86 * c)617 static void init_amd_k8(struct cpuinfo_x86 *c)
618 {
619 u32 level;
620 u64 value;
621
622 /* On C+ stepping K8 rep microcode works well for copy/memset */
623 level = cpuid_eax(1);
624 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
625 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
626
627 /*
628 * Some BIOSes incorrectly force this feature, but only K8 revision D
629 * (model = 0x14) and later actually support it.
630 * (AMD Erratum #110, docId: 25759).
631 */
632 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
633 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
634 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
635 value &= ~BIT_64(32);
636 wrmsrl_amd_safe(0xc001100d, value);
637 }
638 }
639
640 if (!c->x86_model_id[0])
641 strcpy(c->x86_model_id, "Hammer");
642
643 #ifdef CONFIG_SMP
644 /*
645 * Disable TLB flush filter by setting HWCR.FFDIS on K8
646 * bit 6 of msr C001_0015
647 *
648 * Errata 63 for SH-B3 steppings
649 * Errata 122 for all steppings (F+ have it disabled by default)
650 */
651 msr_set_bit(MSR_K7_HWCR, 6);
652 #endif
653 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
654 }
655
init_amd_gh(struct cpuinfo_x86 * c)656 static void init_amd_gh(struct cpuinfo_x86 *c)
657 {
658 #ifdef CONFIG_X86_64
659 /* do this for boot cpu */
660 if (c == &boot_cpu_data)
661 check_enable_amd_mmconf_dmi();
662
663 fam10h_check_enable_mmcfg();
664 #endif
665
666 /*
667 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
668 * is always needed when GART is enabled, even in a kernel which has no
669 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
670 * If it doesn't, we do it here as suggested by the BKDG.
671 *
672 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
673 */
674 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
675
676 /*
677 * On family 10h BIOS may not have properly enabled WC+ support, causing
678 * it to be converted to CD memtype. This may result in performance
679 * degradation for certain nested-paging guests. Prevent this conversion
680 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
681 *
682 * NOTE: we want to use the _safe accessors so as not to #GP kvm
683 * guests on older kvm hosts.
684 */
685 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
686
687 if (cpu_has_amd_erratum(c, amd_erratum_383))
688 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
689 }
690
691 #define MSR_AMD64_DE_CFG 0xC0011029
692
init_amd_ln(struct cpuinfo_x86 * c)693 static void init_amd_ln(struct cpuinfo_x86 *c)
694 {
695 /*
696 * Apply erratum 665 fix unconditionally so machines without a BIOS
697 * fix work.
698 */
699 msr_set_bit(MSR_AMD64_DE_CFG, 31);
700 }
701
init_amd_bd(struct cpuinfo_x86 * c)702 static void init_amd_bd(struct cpuinfo_x86 *c)
703 {
704 u64 value;
705
706 /* re-enable TopologyExtensions if switched off by BIOS */
707 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
709
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
715 }
716 }
717 }
718
719 /*
720 * The way access filter has a performance penalty on some workloads.
721 * Disable it on the affected CPUs.
722 */
723 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
724 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
725 value |= 0x1E;
726 wrmsrl_safe(MSR_F15H_IC_CFG, value);
727 }
728 }
729 }
730
init_amd(struct cpuinfo_x86 * c)731 static void init_amd(struct cpuinfo_x86 *c)
732 {
733 u32 dummy;
734
735 early_init_amd(c);
736
737 /*
738 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
739 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
740 */
741 clear_cpu_cap(c, 0*32+31);
742
743 if (c->x86 >= 0x10)
744 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
745
746 /* get apicid instead of initial apic id from cpuid */
747 c->apicid = hard_smp_processor_id();
748
749 /* K6s reports MCEs but don't actually have all the MSRs */
750 if (c->x86 < 6)
751 clear_cpu_cap(c, X86_FEATURE_MCE);
752
753 switch (c->x86) {
754 case 4: init_amd_k5(c); break;
755 case 5: init_amd_k6(c); break;
756 case 6: init_amd_k7(c); break;
757 case 0xf: init_amd_k8(c); break;
758 case 0x10: init_amd_gh(c); break;
759 case 0x12: init_amd_ln(c); break;
760 case 0x15: init_amd_bd(c); break;
761 }
762
763 /* Enable workaround for FXSAVE leak */
764 if (c->x86 >= 6)
765 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
766
767 cpu_detect_cache_sizes(c);
768
769 /* Multi core CPU? */
770 if (c->extended_cpuid_level >= 0x80000008) {
771 amd_detect_cmp(c);
772 srat_detect_node(c);
773 }
774
775 #ifdef CONFIG_X86_32
776 detect_ht(c);
777 #endif
778
779 init_amd_cacheinfo(c);
780
781 if (c->x86 >= 0xf)
782 set_cpu_cap(c, X86_FEATURE_K8);
783
784 if (cpu_has(c, X86_FEATURE_XMM2)) {
785 unsigned long long val;
786 int ret;
787
788 /*
789 * A serializing LFENCE has less overhead than MFENCE, so
790 * use it for execution serialization. On families which
791 * don't have that MSR, LFENCE is already serializing.
792 * msr_set_bit() uses the safe accessors, too, even if the MSR
793 * is not present.
794 */
795 msr_set_bit(MSR_F10H_DECFG,
796 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
797
798 /*
799 * Verify that the MSR write was successful (could be running
800 * under a hypervisor) and only then assume that LFENCE is
801 * serializing.
802 */
803 ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
804 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
805 /* A serializing LFENCE stops RDTSC speculation */
806 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
807 } else {
808 /* MFENCE stops RDTSC speculation */
809 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
810 }
811 }
812
813 /*
814 * Family 0x12 and above processors have APIC timer
815 * running in deep C states.
816 */
817 if (c->x86 > 0x11)
818 set_cpu_cap(c, X86_FEATURE_ARAT);
819
820 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
821
822 /* 3DNow or LM implies PREFETCHW */
823 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
824 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
825 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
826
827 /* AMD CPUs don't reset SS attributes on SYSRET */
828 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
829 }
830
831 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)832 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
833 {
834 /* AMD errata T13 (order #21922) */
835 if ((c->x86 == 6)) {
836 /* Duron Rev A0 */
837 if (c->x86_model == 3 && c->x86_stepping == 0)
838 size = 64;
839 /* Tbird rev A1/A2 */
840 if (c->x86_model == 4 &&
841 (c->x86_stepping == 0 || c->x86_stepping == 1))
842 size = 256;
843 }
844 return size;
845 }
846 #endif
847
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)848 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
849 {
850 u32 ebx, eax, ecx, edx;
851 u16 mask = 0xfff;
852
853 if (c->x86 < 0xf)
854 return;
855
856 if (c->extended_cpuid_level < 0x80000006)
857 return;
858
859 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
860
861 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
862 tlb_lli_4k[ENTRIES] = ebx & mask;
863
864 /*
865 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
866 * characteristics from the CPUID function 0x80000005 instead.
867 */
868 if (c->x86 == 0xf) {
869 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
870 mask = 0xff;
871 }
872
873 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
874 if (!((eax >> 16) & mask))
875 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
876 else
877 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
878
879 /* a 4M entry uses two 2M entries */
880 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
881
882 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
883 if (!(eax & mask)) {
884 /* Erratum 658 */
885 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
886 tlb_lli_2m[ENTRIES] = 1024;
887 } else {
888 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
889 tlb_lli_2m[ENTRIES] = eax & 0xff;
890 }
891 } else
892 tlb_lli_2m[ENTRIES] = eax & mask;
893
894 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
895 }
896
897 static const struct cpu_dev amd_cpu_dev = {
898 .c_vendor = "AMD",
899 .c_ident = { "AuthenticAMD" },
900 #ifdef CONFIG_X86_32
901 .legacy_models = {
902 { .family = 4, .model_names =
903 {
904 [3] = "486 DX/2",
905 [7] = "486 DX/2-WB",
906 [8] = "486 DX/4",
907 [9] = "486 DX/4-WB",
908 [14] = "Am5x86-WT",
909 [15] = "Am5x86-WB"
910 }
911 },
912 },
913 .legacy_cache_size = amd_size_cache,
914 #endif
915 .c_early_init = early_init_amd,
916 .c_detect_tlb = cpu_detect_tlb_amd,
917 .c_bsp_init = bsp_init_amd,
918 .c_init = init_amd,
919 .c_x86_vendor = X86_VENDOR_AMD,
920 };
921
922 cpu_dev_register(amd_cpu_dev);
923
924 /*
925 * AMD errata checking
926 *
927 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
928 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
929 * have an OSVW id assigned, which it takes as first argument. Both take a
930 * variable number of family-specific model-stepping ranges created by
931 * AMD_MODEL_RANGE().
932 *
933 * Example:
934 *
935 * const int amd_erratum_319[] =
936 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
937 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
938 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
939 */
940
941 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
942 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
943 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
944 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
945 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
946 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
947 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
948
949 static const int amd_erratum_400[] =
950 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
951 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
952
953 static const int amd_erratum_383[] =
954 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
955
956
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)957 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
958 {
959 int osvw_id = *erratum++;
960 u32 range;
961 u32 ms;
962
963 if (osvw_id >= 0 && osvw_id < 65536 &&
964 cpu_has(cpu, X86_FEATURE_OSVW)) {
965 u64 osvw_len;
966
967 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
968 if (osvw_id < osvw_len) {
969 u64 osvw_bits;
970
971 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
972 osvw_bits);
973 return osvw_bits & (1ULL << (osvw_id & 0x3f));
974 }
975 }
976
977 /* OSVW unavailable or ID unknown, match family-model-stepping range */
978 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
979 while ((range = *erratum++))
980 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
981 (ms >= AMD_MODEL_RANGE_START(range)) &&
982 (ms <= AMD_MODEL_RANGE_END(range)))
983 return true;
984
985 return false;
986 }
987
set_dr_addr_mask(unsigned long mask,int dr)988 void set_dr_addr_mask(unsigned long mask, int dr)
989 {
990 if (!boot_cpu_has(X86_FEATURE_BPEXT))
991 return;
992
993 switch (dr) {
994 case 0:
995 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
996 break;
997 case 1:
998 case 2:
999 case 3:
1000 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1001 break;
1002 default:
1003 break;
1004 }
1005 }
1006