1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
25
26 #include "ath9k.h"
27
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
30 struct ath_hw *ah;
31 };
32
33 static char *dev_info = "ath9k";
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
43
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
47
48 int ath9k_led_blink;
49 module_param_named(blink, ath9k_led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
51
52 static int ath9k_led_active_high = -1;
53 module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
54 MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
55
56 static int ath9k_btcoex_enable;
57 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
58 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
59
60 static int ath9k_bt_ant_diversity;
61 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
62 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
63
64 static int ath9k_ps_enable;
65 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
66 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
67
68 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
69
70 int ath9k_use_chanctx;
71 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
72 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
73
74 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
75
76 bool is_ath9k_unloaded;
77
78 #ifdef CONFIG_MAC80211_LEDS
79 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
80 { .throughput = 0 * 1024, .blink_time = 334 },
81 { .throughput = 1 * 1024, .blink_time = 260 },
82 { .throughput = 5 * 1024, .blink_time = 220 },
83 { .throughput = 10 * 1024, .blink_time = 190 },
84 { .throughput = 20 * 1024, .blink_time = 170 },
85 { .throughput = 50 * 1024, .blink_time = 150 },
86 { .throughput = 70 * 1024, .blink_time = 130 },
87 { .throughput = 100 * 1024, .blink_time = 110 },
88 { .throughput = 200 * 1024, .blink_time = 80 },
89 { .throughput = 300 * 1024, .blink_time = 50 },
90 };
91 #endif
92
93 static void ath9k_deinit_softc(struct ath_softc *sc);
94
ath9k_op_ps_wakeup(struct ath_common * common)95 static void ath9k_op_ps_wakeup(struct ath_common *common)
96 {
97 ath9k_ps_wakeup((struct ath_softc *) common->priv);
98 }
99
ath9k_op_ps_restore(struct ath_common * common)100 static void ath9k_op_ps_restore(struct ath_common *common)
101 {
102 ath9k_ps_restore((struct ath_softc *) common->priv);
103 }
104
105 static struct ath_ps_ops ath9k_ps_ops = {
106 .wakeup = ath9k_op_ps_wakeup,
107 .restore = ath9k_op_ps_restore,
108 };
109
110 /*
111 * Read and write, they both share the same lock. We do this to serialize
112 * reads and writes on Atheros 802.11n PCI devices only. This is required
113 * as the FIFO on these devices can only accept sanely 2 requests.
114 */
115
ath9k_iowrite32(void * hw_priv,u32 val,u32 reg_offset)116 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
117 {
118 struct ath_hw *ah = (struct ath_hw *) hw_priv;
119 struct ath_common *common = ath9k_hw_common(ah);
120 struct ath_softc *sc = (struct ath_softc *) common->priv;
121
122 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
123 unsigned long flags;
124 spin_lock_irqsave(&sc->sc_serial_rw, flags);
125 iowrite32(val, sc->mem + reg_offset);
126 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
127 } else
128 iowrite32(val, sc->mem + reg_offset);
129 }
130
ath9k_ioread32(void * hw_priv,u32 reg_offset)131 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
132 {
133 struct ath_hw *ah = (struct ath_hw *) hw_priv;
134 struct ath_common *common = ath9k_hw_common(ah);
135 struct ath_softc *sc = (struct ath_softc *) common->priv;
136 u32 val;
137
138 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
139 unsigned long flags;
140 spin_lock_irqsave(&sc->sc_serial_rw, flags);
141 val = ioread32(sc->mem + reg_offset);
142 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
143 } else
144 val = ioread32(sc->mem + reg_offset);
145 return val;
146 }
147
ath9k_multi_ioread32(void * hw_priv,u32 * addr,u32 * val,u16 count)148 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
149 u32 *val, u16 count)
150 {
151 int i;
152
153 for (i = 0; i < count; i++)
154 val[i] = ath9k_ioread32(hw_priv, addr[i]);
155 }
156
157
__ath9k_reg_rmw(struct ath_softc * sc,u32 reg_offset,u32 set,u32 clr)158 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
159 u32 set, u32 clr)
160 {
161 u32 val;
162
163 val = ioread32(sc->mem + reg_offset);
164 val &= ~clr;
165 val |= set;
166 iowrite32(val, sc->mem + reg_offset);
167
168 return val;
169 }
170
ath9k_reg_rmw(void * hw_priv,u32 reg_offset,u32 set,u32 clr)171 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
172 {
173 struct ath_hw *ah = (struct ath_hw *) hw_priv;
174 struct ath_common *common = ath9k_hw_common(ah);
175 struct ath_softc *sc = (struct ath_softc *) common->priv;
176 unsigned long uninitialized_var(flags);
177 u32 val;
178
179 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
180 spin_lock_irqsave(&sc->sc_serial_rw, flags);
181 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
182 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
183 } else
184 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
185
186 return val;
187 }
188
189 /**************************/
190 /* Initialization */
191 /**************************/
192
ath9k_reg_notifier(struct wiphy * wiphy,struct regulatory_request * request)193 static void ath9k_reg_notifier(struct wiphy *wiphy,
194 struct regulatory_request *request)
195 {
196 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
197 struct ath_softc *sc = hw->priv;
198 struct ath_hw *ah = sc->sc_ah;
199 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
200
201 ath_reg_notifier_apply(wiphy, request, reg);
202
203 /* Set tx power */
204 if (!ah->curchan)
205 return;
206
207 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
208 ath9k_ps_wakeup(sc);
209 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
210 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
211 sc->cur_chan->txpower,
212 &sc->cur_chan->cur_txpower);
213 /* synchronize DFS detector if regulatory domain changed */
214 if (sc->dfs_detector != NULL)
215 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
216 request->dfs_region);
217 ath9k_ps_restore(sc);
218 }
219
220 /*
221 * This function will allocate both the DMA descriptor structure, and the
222 * buffers it contains. These are used to contain the descriptors used
223 * by the system.
224 */
ath_descdma_setup(struct ath_softc * sc,struct ath_descdma * dd,struct list_head * head,const char * name,int nbuf,int ndesc,bool is_tx)225 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
226 struct list_head *head, const char *name,
227 int nbuf, int ndesc, bool is_tx)
228 {
229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
230 u8 *ds;
231 int i, bsize, desc_len;
232
233 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
234 name, nbuf, ndesc);
235
236 INIT_LIST_HEAD(head);
237
238 if (is_tx)
239 desc_len = sc->sc_ah->caps.tx_desc_len;
240 else
241 desc_len = sizeof(struct ath_desc);
242
243 /* ath_desc must be a multiple of DWORDs */
244 if ((desc_len % 4) != 0) {
245 ath_err(common, "ath_desc not DWORD aligned\n");
246 BUG_ON((desc_len % 4) != 0);
247 return -ENOMEM;
248 }
249
250 dd->dd_desc_len = desc_len * nbuf * ndesc;
251
252 /*
253 * Need additional DMA memory because we can't use
254 * descriptors that cross the 4K page boundary. Assume
255 * one skipped descriptor per 4K page.
256 */
257 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
258 u32 ndesc_skipped =
259 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
260 u32 dma_len;
261
262 while (ndesc_skipped) {
263 dma_len = ndesc_skipped * desc_len;
264 dd->dd_desc_len += dma_len;
265
266 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
267 }
268 }
269
270 /* allocate descriptors */
271 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
272 &dd->dd_desc_paddr, GFP_KERNEL);
273 if (!dd->dd_desc)
274 return -ENOMEM;
275
276 ds = (u8 *) dd->dd_desc;
277 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
278 name, ds, (u32) dd->dd_desc_len,
279 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
280
281 /* allocate buffers */
282 if (is_tx) {
283 struct ath_buf *bf;
284
285 bsize = sizeof(struct ath_buf) * nbuf;
286 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
287 if (!bf)
288 return -ENOMEM;
289
290 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
291 bf->bf_desc = ds;
292 bf->bf_daddr = DS2PHYS(dd, ds);
293
294 if (!(sc->sc_ah->caps.hw_caps &
295 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
296 /*
297 * Skip descriptor addresses which can cause 4KB
298 * boundary crossing (addr + length) with a 32 dword
299 * descriptor fetch.
300 */
301 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
302 BUG_ON((caddr_t) bf->bf_desc >=
303 ((caddr_t) dd->dd_desc +
304 dd->dd_desc_len));
305
306 ds += (desc_len * ndesc);
307 bf->bf_desc = ds;
308 bf->bf_daddr = DS2PHYS(dd, ds);
309 }
310 }
311 list_add_tail(&bf->list, head);
312 }
313 } else {
314 struct ath_rxbuf *bf;
315
316 bsize = sizeof(struct ath_rxbuf) * nbuf;
317 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
318 if (!bf)
319 return -ENOMEM;
320
321 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
322 bf->bf_desc = ds;
323 bf->bf_daddr = DS2PHYS(dd, ds);
324
325 if (!(sc->sc_ah->caps.hw_caps &
326 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
327 /*
328 * Skip descriptor addresses which can cause 4KB
329 * boundary crossing (addr + length) with a 32 dword
330 * descriptor fetch.
331 */
332 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
333 BUG_ON((caddr_t) bf->bf_desc >=
334 ((caddr_t) dd->dd_desc +
335 dd->dd_desc_len));
336
337 ds += (desc_len * ndesc);
338 bf->bf_desc = ds;
339 bf->bf_daddr = DS2PHYS(dd, ds);
340 }
341 }
342 list_add_tail(&bf->list, head);
343 }
344 }
345 return 0;
346 }
347
ath9k_init_queues(struct ath_softc * sc)348 static int ath9k_init_queues(struct ath_softc *sc)
349 {
350 int i = 0;
351
352 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
353 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
354 ath_cabq_update(sc);
355
356 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
357
358 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
359 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
360 sc->tx.txq_map[i]->mac80211_qnum = i;
361 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
362 }
363 return 0;
364 }
365
ath9k_init_misc(struct ath_softc * sc)366 static void ath9k_init_misc(struct ath_softc *sc)
367 {
368 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
369 int i = 0;
370
371 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
372
373 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
374 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
375 sc->beacon.slottime = 9;
376
377 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
378 sc->beacon.bslot[i] = NULL;
379
380 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
381 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
382
383 sc->spec_priv.ah = sc->sc_ah;
384 sc->spec_priv.spec_config.enabled = 0;
385 sc->spec_priv.spec_config.short_repeat = true;
386 sc->spec_priv.spec_config.count = 8;
387 sc->spec_priv.spec_config.endless = false;
388 sc->spec_priv.spec_config.period = 0xFF;
389 sc->spec_priv.spec_config.fft_period = 0xF;
390 }
391
ath9k_init_pcoem_platform(struct ath_softc * sc)392 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
393 {
394 struct ath_hw *ah = sc->sc_ah;
395 struct ath9k_hw_capabilities *pCap = &ah->caps;
396 struct ath_common *common = ath9k_hw_common(ah);
397
398 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
399 return;
400
401 if (common->bus_ops->ath_bus_type != ATH_PCI)
402 return;
403
404 if (sc->driver_data & (ATH9K_PCI_CUS198 |
405 ATH9K_PCI_CUS230)) {
406 ah->config.xlna_gpio = 9;
407 ah->config.xatten_margin_cfg = true;
408 ah->config.alt_mingainidx = true;
409 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
410 sc->ant_comb.low_rssi_thresh = 20;
411 sc->ant_comb.fast_div_bias = 3;
412
413 ath_info(common, "Set parameters for %s\n",
414 (sc->driver_data & ATH9K_PCI_CUS198) ?
415 "CUS198" : "CUS230");
416 }
417
418 if (sc->driver_data & ATH9K_PCI_CUS217)
419 ath_info(common, "CUS217 card detected\n");
420
421 if (sc->driver_data & ATH9K_PCI_CUS252)
422 ath_info(common, "CUS252 card detected\n");
423
424 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
425 ath_info(common, "WB335 1-ANT card detected\n");
426
427 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
428 ath_info(common, "WB335 2-ANT card detected\n");
429
430 if (sc->driver_data & ATH9K_PCI_KILLER)
431 ath_info(common, "Killer Wireless card detected\n");
432
433 /*
434 * Some WB335 cards do not support antenna diversity. Since
435 * we use a hardcoded value for AR9565 instead of using the
436 * EEPROM/OTP data, remove the combining feature from
437 * the HW capabilities bitmap.
438 */
439 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
440 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
441 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
442 }
443
444 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
445 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
446 ath_info(common, "Set BT/WLAN RX diversity capability\n");
447 }
448
449 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
450 ah->config.pcie_waen = 0x0040473b;
451 ath_info(common, "Enable WAR for ASPM D3/L1\n");
452 }
453
454 /*
455 * The default value of pll_pwrsave is 1.
456 * For certain AR9485 cards, it is set to 0.
457 * For AR9462, AR9565 it's set to 7.
458 */
459 ah->config.pll_pwrsave = 1;
460
461 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
462 ah->config.pll_pwrsave = 0;
463 ath_info(common, "Disable PLL PowerSave\n");
464 }
465
466 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
467 ah->config.led_active_high = true;
468 }
469
ath9k_eeprom_request_cb(const struct firmware * eeprom_blob,void * ctx)470 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
471 void *ctx)
472 {
473 struct ath9k_eeprom_ctx *ec = ctx;
474
475 if (eeprom_blob)
476 ec->ah->eeprom_blob = eeprom_blob;
477
478 complete(&ec->complete);
479 }
480
ath9k_eeprom_request(struct ath_softc * sc,const char * name)481 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
482 {
483 struct ath9k_eeprom_ctx ec;
484 struct ath_hw *ah = sc->sc_ah;
485 int err;
486
487 /* try to load the EEPROM content asynchronously */
488 init_completion(&ec.complete);
489 ec.ah = sc->sc_ah;
490
491 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
492 &ec, ath9k_eeprom_request_cb);
493 if (err < 0) {
494 ath_err(ath9k_hw_common(ah),
495 "EEPROM request failed\n");
496 return err;
497 }
498
499 wait_for_completion(&ec.complete);
500
501 if (!ah->eeprom_blob) {
502 ath_err(ath9k_hw_common(ah),
503 "Unable to load EEPROM file %s\n", name);
504 return -EINVAL;
505 }
506
507 return 0;
508 }
509
ath9k_eeprom_release(struct ath_softc * sc)510 static void ath9k_eeprom_release(struct ath_softc *sc)
511 {
512 release_firmware(sc->sc_ah->eeprom_blob);
513 }
514
ath9k_init_platform(struct ath_softc * sc)515 static int ath9k_init_platform(struct ath_softc *sc)
516 {
517 struct ath9k_platform_data *pdata = sc->dev->platform_data;
518 struct ath_hw *ah = sc->sc_ah;
519 struct ath_common *common = ath9k_hw_common(ah);
520 int ret;
521
522 if (!pdata)
523 return 0;
524
525 if (!pdata->use_eeprom) {
526 ah->ah_flags &= ~AH_USE_EEPROM;
527 ah->gpio_mask = pdata->gpio_mask;
528 ah->gpio_val = pdata->gpio_val;
529 ah->led_pin = pdata->led_pin;
530 ah->is_clk_25mhz = pdata->is_clk_25mhz;
531 ah->get_mac_revision = pdata->get_mac_revision;
532 ah->external_reset = pdata->external_reset;
533 ah->disable_2ghz = pdata->disable_2ghz;
534 ah->disable_5ghz = pdata->disable_5ghz;
535
536 if (!pdata->endian_check)
537 ah->ah_flags |= AH_NO_EEP_SWAP;
538 }
539
540 if (pdata->eeprom_name) {
541 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
542 if (ret)
543 return ret;
544 }
545
546 if (pdata->led_active_high)
547 ah->config.led_active_high = true;
548
549 if (pdata->tx_gain_buffalo)
550 ah->config.tx_gain_buffalo = true;
551
552 if (pdata->macaddr)
553 ether_addr_copy(common->macaddr, pdata->macaddr);
554
555 return 0;
556 }
557
ath9k_init_softc(u16 devid,struct ath_softc * sc,const struct ath_bus_ops * bus_ops)558 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
559 const struct ath_bus_ops *bus_ops)
560 {
561 struct ath_hw *ah = NULL;
562 struct ath9k_hw_capabilities *pCap;
563 struct ath_common *common;
564 int ret = 0, i;
565 int csz = 0;
566
567 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
568 if (!ah)
569 return -ENOMEM;
570
571 ah->dev = sc->dev;
572 ah->hw = sc->hw;
573 ah->hw_version.devid = devid;
574 ah->ah_flags |= AH_USE_EEPROM;
575 ah->led_pin = -1;
576 ah->reg_ops.read = ath9k_ioread32;
577 ah->reg_ops.multi_read = ath9k_multi_ioread32;
578 ah->reg_ops.write = ath9k_iowrite32;
579 ah->reg_ops.rmw = ath9k_reg_rmw;
580 pCap = &ah->caps;
581
582 common = ath9k_hw_common(ah);
583
584 /* Will be cleared in ath9k_start() */
585 set_bit(ATH_OP_INVALID, &common->op_flags);
586
587 sc->sc_ah = ah;
588 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
589 sc->tx99_power = MAX_RATE_POWER + 1;
590 init_waitqueue_head(&sc->tx_wait);
591 sc->cur_chan = &sc->chanctx[0];
592 if (!ath9k_is_chanctx_enabled())
593 sc->cur_chan->hw_queue_base = 0;
594
595 common->ops = &ah->reg_ops;
596 common->bus_ops = bus_ops;
597 common->ps_ops = &ath9k_ps_ops;
598 common->ah = ah;
599 common->hw = sc->hw;
600 common->priv = sc;
601 common->debug_mask = ath9k_debug;
602 common->btcoex_enabled = ath9k_btcoex_enable == 1;
603 common->disable_ani = false;
604
605 /*
606 * Platform quirks.
607 */
608 ath9k_init_pcoem_platform(sc);
609
610 ret = ath9k_init_platform(sc);
611 if (ret)
612 return ret;
613
614 if (ath9k_led_active_high != -1)
615 ah->config.led_active_high = ath9k_led_active_high == 1;
616
617 /*
618 * Enable WLAN/BT RX Antenna diversity only when:
619 *
620 * - BTCOEX is disabled.
621 * - the user manually requests the feature.
622 * - the HW cap is set using the platform data.
623 */
624 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
625 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
626 common->bt_ant_diversity = 1;
627
628 spin_lock_init(&common->cc_lock);
629 spin_lock_init(&sc->intr_lock);
630 spin_lock_init(&sc->sc_serial_rw);
631 spin_lock_init(&sc->sc_pm_lock);
632 spin_lock_init(&sc->chan_lock);
633 mutex_init(&sc->mutex);
634 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
635 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
636 (unsigned long)sc);
637
638 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
639 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
640 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
641 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
642
643 ath9k_init_channel_context(sc);
644
645 /*
646 * Cache line size is used to size and align various
647 * structures used to communicate with the hardware.
648 */
649 ath_read_cachesize(common, &csz);
650 common->cachelsz = csz << 2; /* convert to bytes */
651
652 /* Initializes the hardware for all supported chipsets */
653 ret = ath9k_hw_init(ah);
654 if (ret)
655 goto err_hw;
656
657 ret = ath9k_init_queues(sc);
658 if (ret)
659 goto err_queues;
660
661 ret = ath9k_init_btcoex(sc);
662 if (ret)
663 goto err_btcoex;
664
665 ret = ath9k_cmn_init_channels_rates(common);
666 if (ret)
667 goto err_btcoex;
668
669 ret = ath9k_init_p2p(sc);
670 if (ret)
671 goto err_btcoex;
672
673 ath9k_cmn_init_crypto(sc->sc_ah);
674 ath9k_init_misc(sc);
675 ath_chanctx_init(sc);
676 ath9k_offchannel_init(sc);
677
678 if (common->bus_ops->aspm_init)
679 common->bus_ops->aspm_init(common);
680
681 return 0;
682
683 err_btcoex:
684 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
685 if (ATH_TXQ_SETUP(sc, i))
686 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
687 err_queues:
688 ath9k_hw_deinit(ah);
689 err_hw:
690 ath9k_eeprom_release(sc);
691 dev_kfree_skb_any(sc->tx99_skb);
692 return ret;
693 }
694
ath9k_init_band_txpower(struct ath_softc * sc,int band)695 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
696 {
697 struct ieee80211_supported_band *sband;
698 struct ieee80211_channel *chan;
699 struct ath_hw *ah = sc->sc_ah;
700 struct ath_common *common = ath9k_hw_common(ah);
701 struct cfg80211_chan_def chandef;
702 int i;
703
704 sband = &common->sbands[band];
705 for (i = 0; i < sband->n_channels; i++) {
706 chan = &sband->channels[i];
707 ah->curchan = &ah->channels[chan->hw_value];
708 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
709 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
710 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
711 }
712 }
713
ath9k_init_txpower_limits(struct ath_softc * sc)714 static void ath9k_init_txpower_limits(struct ath_softc *sc)
715 {
716 struct ath_hw *ah = sc->sc_ah;
717 struct ath9k_channel *curchan = ah->curchan;
718
719 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
720 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
721 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
722 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
723
724 ah->curchan = curchan;
725 }
726
727 static const struct ieee80211_iface_limit if_limits[] = {
728 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
729 { .max = 8, .types =
730 #ifdef CONFIG_MAC80211_MESH
731 BIT(NL80211_IFTYPE_MESH_POINT) |
732 #endif
733 BIT(NL80211_IFTYPE_AP) },
734 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
735 BIT(NL80211_IFTYPE_P2P_GO) },
736 };
737
738 static const struct ieee80211_iface_limit wds_limits[] = {
739 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
740 };
741
742 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
743
744 static const struct ieee80211_iface_limit if_limits_multi[] = {
745 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
746 BIT(NL80211_IFTYPE_AP) |
747 BIT(NL80211_IFTYPE_P2P_CLIENT) |
748 BIT(NL80211_IFTYPE_P2P_GO) },
749 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
750 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
751 };
752
753 static const struct ieee80211_iface_combination if_comb_multi[] = {
754 {
755 .limits = if_limits_multi,
756 .n_limits = ARRAY_SIZE(if_limits_multi),
757 .max_interfaces = 3,
758 .num_different_channels = 2,
759 .beacon_int_infra_match = true,
760 },
761 };
762
763 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
764
765 static const struct ieee80211_iface_combination if_comb[] = {
766 {
767 .limits = if_limits,
768 .n_limits = ARRAY_SIZE(if_limits),
769 .max_interfaces = 2048,
770 .num_different_channels = 1,
771 .beacon_int_infra_match = true,
772 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
773 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
774 BIT(NL80211_CHAN_WIDTH_20) |
775 BIT(NL80211_CHAN_WIDTH_40),
776 #endif
777 },
778 {
779 .limits = wds_limits,
780 .n_limits = ARRAY_SIZE(wds_limits),
781 .max_interfaces = 2048,
782 .num_different_channels = 1,
783 .beacon_int_infra_match = true,
784 },
785 };
786
787 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_mcc_capab(struct ath_softc * sc,struct ieee80211_hw * hw)788 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
789 {
790 struct ath_hw *ah = sc->sc_ah;
791 struct ath_common *common = ath9k_hw_common(ah);
792
793 if (!ath9k_is_chanctx_enabled())
794 return;
795
796 ieee80211_hw_set(hw, QUEUE_CONTROL);
797 hw->queues = ATH9K_NUM_TX_QUEUES;
798 hw->offchannel_tx_hw_queue = hw->queues - 1;
799 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
800 hw->wiphy->iface_combinations = if_comb_multi;
801 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
802 hw->wiphy->max_scan_ssids = 255;
803 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
804 hw->wiphy->max_remain_on_channel_duration = 10000;
805 hw->chanctx_data_size = sizeof(void *);
806 hw->extra_beacon_tailroom =
807 sizeof(struct ieee80211_p2p_noa_attr) + 9;
808
809 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
810 }
811 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
812
ath9k_set_hw_capab(struct ath_softc * sc,struct ieee80211_hw * hw)813 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
814 {
815 struct ath_hw *ah = sc->sc_ah;
816 struct ath_common *common = ath9k_hw_common(ah);
817
818 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
819 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
820 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
821 ieee80211_hw_set(hw, SPECTRUM_MGMT);
822 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
823 ieee80211_hw_set(hw, SIGNAL_DBM);
824 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
825 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
826 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
827 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
828
829 if (ath9k_ps_enable)
830 ieee80211_hw_set(hw, SUPPORTS_PS);
831
832 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
833 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
834
835 if (AR_SREV_9280_20_OR_LATER(ah))
836 hw->radiotap_mcs_details |=
837 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
838 }
839
840 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
841 ieee80211_hw_set(hw, MFP_CAPABLE);
842
843 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
844 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
845 NL80211_FEATURE_P2P_GO_CTWIN;
846
847 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
848 hw->wiphy->interface_modes =
849 BIT(NL80211_IFTYPE_P2P_GO) |
850 BIT(NL80211_IFTYPE_P2P_CLIENT) |
851 BIT(NL80211_IFTYPE_AP) |
852 BIT(NL80211_IFTYPE_STATION) |
853 BIT(NL80211_IFTYPE_ADHOC) |
854 BIT(NL80211_IFTYPE_MESH_POINT) |
855 BIT(NL80211_IFTYPE_WDS) |
856 BIT(NL80211_IFTYPE_OCB);
857
858 if (ath9k_is_chanctx_enabled())
859 hw->wiphy->interface_modes |=
860 BIT(NL80211_IFTYPE_P2P_DEVICE);
861
862 hw->wiphy->iface_combinations = if_comb;
863 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
864 }
865
866 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
867
868 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
869 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
870 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
871 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
872 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
873 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
874
875 hw->queues = 4;
876 hw->max_rates = 4;
877 hw->max_listen_interval = 10;
878 hw->max_rate_tries = 10;
879 hw->sta_data_size = sizeof(struct ath_node);
880 hw->vif_data_size = sizeof(struct ath_vif);
881 hw->extra_tx_headroom = 4;
882
883 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
884 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
885
886 /* single chain devices with rx diversity */
887 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
888 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
889
890 sc->ant_rx = hw->wiphy->available_antennas_rx;
891 sc->ant_tx = hw->wiphy->available_antennas_tx;
892
893 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
894 hw->wiphy->bands[NL80211_BAND_2GHZ] =
895 &common->sbands[NL80211_BAND_2GHZ];
896 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
897 hw->wiphy->bands[NL80211_BAND_5GHZ] =
898 &common->sbands[NL80211_BAND_5GHZ];
899
900 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
901 ath9k_set_mcc_capab(sc, hw);
902 #endif
903 ath9k_init_wow(hw);
904 ath9k_cmn_reload_chainmask(ah);
905
906 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
907 }
908
ath9k_init_device(u16 devid,struct ath_softc * sc,const struct ath_bus_ops * bus_ops)909 int ath9k_init_device(u16 devid, struct ath_softc *sc,
910 const struct ath_bus_ops *bus_ops)
911 {
912 struct ieee80211_hw *hw = sc->hw;
913 struct ath_common *common;
914 struct ath_hw *ah;
915 int error = 0;
916 struct ath_regulatory *reg;
917
918 /* Bring up device */
919 error = ath9k_init_softc(devid, sc, bus_ops);
920 if (error)
921 return error;
922
923 ah = sc->sc_ah;
924 common = ath9k_hw_common(ah);
925 ath9k_set_hw_capab(sc, hw);
926
927 /* Initialize regulatory */
928 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
929 ath9k_reg_notifier);
930 if (error)
931 goto deinit;
932
933 reg = &common->regulatory;
934
935 /* Setup TX DMA */
936 error = ath_tx_init(sc, ATH_TXBUF);
937 if (error != 0)
938 goto deinit;
939
940 /* Setup RX DMA */
941 error = ath_rx_init(sc, ATH_RXBUF);
942 if (error != 0)
943 goto deinit;
944
945 ath9k_init_txpower_limits(sc);
946
947 #ifdef CONFIG_MAC80211_LEDS
948 /* must be initialized before ieee80211_register_hw */
949 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
950 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
951 ARRAY_SIZE(ath9k_tpt_blink));
952 #endif
953
954 /* Register with mac80211 */
955 error = ieee80211_register_hw(hw);
956 if (error)
957 goto rx_cleanup;
958
959 error = ath9k_init_debug(ah);
960 if (error) {
961 ath_err(common, "Unable to create debugfs files\n");
962 goto unregister;
963 }
964
965 /* Handle world regulatory */
966 if (!ath_is_world_regd(reg)) {
967 error = regulatory_hint(hw->wiphy, reg->alpha2);
968 if (error)
969 goto debug_cleanup;
970 }
971
972 ath_init_leds(sc);
973 ath_start_rfkill_poll(sc);
974
975 return 0;
976
977 debug_cleanup:
978 ath9k_deinit_debug(sc);
979 unregister:
980 ieee80211_unregister_hw(hw);
981 rx_cleanup:
982 ath_rx_cleanup(sc);
983 deinit:
984 ath9k_deinit_softc(sc);
985 return error;
986 }
987
988 /*****************************/
989 /* De-Initialization */
990 /*****************************/
991
ath9k_deinit_softc(struct ath_softc * sc)992 static void ath9k_deinit_softc(struct ath_softc *sc)
993 {
994 int i = 0;
995
996 ath9k_deinit_p2p(sc);
997 ath9k_deinit_btcoex(sc);
998
999 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1000 if (ATH_TXQ_SETUP(sc, i))
1001 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1002
1003 del_timer_sync(&sc->sleep_timer);
1004 ath9k_hw_deinit(sc->sc_ah);
1005 if (sc->dfs_detector != NULL)
1006 sc->dfs_detector->exit(sc->dfs_detector);
1007
1008 ath9k_eeprom_release(sc);
1009 }
1010
ath9k_deinit_device(struct ath_softc * sc)1011 void ath9k_deinit_device(struct ath_softc *sc)
1012 {
1013 struct ieee80211_hw *hw = sc->hw;
1014
1015 ath9k_ps_wakeup(sc);
1016
1017 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1018 ath_deinit_leds(sc);
1019
1020 ath9k_ps_restore(sc);
1021
1022 ath9k_deinit_debug(sc);
1023 ath9k_deinit_wow(hw);
1024 ieee80211_unregister_hw(hw);
1025 ath_rx_cleanup(sc);
1026 ath9k_deinit_softc(sc);
1027 }
1028
1029 /************************/
1030 /* Module Hooks */
1031 /************************/
1032
ath9k_init(void)1033 static int __init ath9k_init(void)
1034 {
1035 int error;
1036
1037 error = ath_pci_init();
1038 if (error < 0) {
1039 pr_err("No PCI devices found, driver not installed\n");
1040 error = -ENODEV;
1041 goto err_out;
1042 }
1043
1044 error = ath_ahb_init();
1045 if (error < 0) {
1046 error = -ENODEV;
1047 goto err_pci_exit;
1048 }
1049
1050 return 0;
1051
1052 err_pci_exit:
1053 ath_pci_exit();
1054 err_out:
1055 return error;
1056 }
1057 module_init(ath9k_init);
1058
ath9k_exit(void)1059 static void __exit ath9k_exit(void)
1060 {
1061 is_ath9k_unloaded = true;
1062 ath_ahb_exit();
1063 ath_pci_exit();
1064 pr_info("%s: Driver unloaded\n", dev_info);
1065 }
1066 module_exit(ath9k_exit);
1067