1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
31 #include <net/dsa.h>
32 #include <net/switchdev.h>
33
34 #include "b53_regs.h"
35 #include "b53_priv.h"
36
37 struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41 };
42
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77 };
78
79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81 /* BCM63xx MIB counters */
82 static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125 };
126
127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129 /* MIB counters */
130 static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166 };
167
168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
170 static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225 };
226
227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
b53_do_vlan_op(struct b53_device * dev,u8 op)229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230 {
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246 }
247
b53_set_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
250 {
251 if (is5325(dev)) {
252 u32 entry = 0;
253
254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286 }
287
b53_get_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290 {
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
325 }
326
b53_set_forwarding(struct b53_device * dev,int enable)327 static void b53_set_forwarding(struct b53_device *dev, int enable)
328 {
329 struct dsa_switch *ds = dev->ds;
330 u8 mgmt;
331
332 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
333
334 if (enable)
335 mgmt |= SM_SW_FWD_EN;
336 else
337 mgmt &= ~SM_SW_FWD_EN;
338
339 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
340
341 /* Include IMP port in dumb forwarding mode when no tagging protocol is
342 * set
343 */
344 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
346 mgmt |= B53_MII_DUMB_FWDG_EN;
347 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
348 }
349 }
350
b53_enable_vlan(struct b53_device * dev,bool enable)351 static void b53_enable_vlan(struct b53_device *dev, bool enable)
352 {
353 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
354
355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
358
359 if (is5325(dev) || is5365(dev)) {
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
362 } else if (is63xx(dev)) {
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
365 } else {
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
368 }
369
370 mgmt &= ~SM_SW_FWD_MODE;
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
377 vc5 |= VC5_DROP_VTABLE_MISS;
378
379 if (is5325(dev))
380 vc0 &= ~VC0_RESERVED_1;
381
382 if (is5325(dev) || is5365(dev))
383 vc1 |= VC1_RX_MCST_TAG_EN;
384
385 } else {
386 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
387 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
388 vc4 &= ~VC4_ING_VID_CHECK_MASK;
389 vc5 &= ~VC5_DROP_VTABLE_MISS;
390
391 if (is5325(dev) || is5365(dev))
392 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
393 else
394 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
395
396 if (is5325(dev) || is5365(dev))
397 vc1 &= ~VC1_RX_MCST_TAG_EN;
398 }
399
400 if (!is5325(dev) && !is5365(dev))
401 vc5 &= ~VC5_VID_FFF_EN;
402
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
405
406 if (is5325(dev) || is5365(dev)) {
407 /* enable the high 8 bit vid check on 5325 */
408 if (is5325(dev) && enable)
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
410 VC3_HIGH_8BIT_EN);
411 else
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
413
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
416 } else if (is63xx(dev)) {
417 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
420 } else {
421 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
424 }
425
426 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
427 }
428
b53_set_jumbo(struct b53_device * dev,bool enable,bool allow_10_100)429 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
430 {
431 u32 port_mask = 0;
432 u16 max_size = JMS_MIN_SIZE;
433
434 if (is5325(dev) || is5365(dev))
435 return -EINVAL;
436
437 if (enable) {
438 port_mask = dev->enabled_ports;
439 max_size = JMS_MAX_SIZE;
440 if (allow_10_100)
441 port_mask |= JPM_10_100_JUMBO_EN;
442 }
443
444 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
445 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
446 }
447
b53_flush_arl(struct b53_device * dev,u8 mask)448 static int b53_flush_arl(struct b53_device *dev, u8 mask)
449 {
450 unsigned int i;
451
452 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
453 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
454
455 for (i = 0; i < 10; i++) {
456 u8 fast_age_ctrl;
457
458 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
459 &fast_age_ctrl);
460
461 if (!(fast_age_ctrl & FAST_AGE_DONE))
462 goto out;
463
464 msleep(1);
465 }
466
467 return -ETIMEDOUT;
468 out:
469 /* Only age dynamic entries (default behavior) */
470 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
471 return 0;
472 }
473
b53_fast_age_port(struct b53_device * dev,int port)474 static int b53_fast_age_port(struct b53_device *dev, int port)
475 {
476 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
477
478 return b53_flush_arl(dev, FAST_AGE_PORT);
479 }
480
b53_fast_age_vlan(struct b53_device * dev,u16 vid)481 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
482 {
483 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
484
485 return b53_flush_arl(dev, FAST_AGE_VLAN);
486 }
487
b53_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)488 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
489 {
490 struct b53_device *dev = ds->priv;
491 unsigned int i;
492 u16 pvlan;
493
494 /* Enable the IMP port to be in the same VLAN as the other ports
495 * on a per-port basis such that we only have Port i and IMP in
496 * the same VLAN.
497 */
498 b53_for_each_port(dev, i) {
499 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
500 pvlan |= BIT(cpu_port);
501 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
502 }
503 }
504
b53_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)505 static int b53_enable_port(struct dsa_switch *ds, int port,
506 struct phy_device *phy)
507 {
508 struct b53_device *dev = ds->priv;
509 unsigned int cpu_port = dev->cpu_port;
510 u16 pvlan;
511
512 /* Clear the Rx and Tx disable bits and set to no spanning tree */
513 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
514
515 /* Set this port, and only this one to be in the default VLAN,
516 * if member of a bridge, restore its membership prior to
517 * bringing down this port.
518 */
519 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
520 pvlan &= ~0x1ff;
521 pvlan |= BIT(port);
522 pvlan |= dev->ports[port].vlan_ctl_mask;
523 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
524
525 b53_imp_vlan_setup(ds, cpu_port);
526
527 return 0;
528 }
529
b53_disable_port(struct dsa_switch * ds,int port,struct phy_device * phy)530 static void b53_disable_port(struct dsa_switch *ds, int port,
531 struct phy_device *phy)
532 {
533 struct b53_device *dev = ds->priv;
534 u8 reg;
535
536 /* Disable Tx/Rx for the port */
537 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
538 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
539 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
540 }
541
b53_enable_cpu_port(struct b53_device * dev)542 static void b53_enable_cpu_port(struct b53_device *dev)
543 {
544 unsigned int cpu_port = dev->cpu_port;
545 u8 port_ctrl;
546
547 /* BCM5325 CPU port is at 8 */
548 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
549 cpu_port = B53_CPU_PORT;
550
551 port_ctrl = PORT_CTRL_RX_BCST_EN |
552 PORT_CTRL_RX_MCST_EN |
553 PORT_CTRL_RX_UCST_EN;
554 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
555 }
556
b53_enable_mib(struct b53_device * dev)557 static void b53_enable_mib(struct b53_device *dev)
558 {
559 u8 gc;
560
561 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
562 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
563 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
564 }
565
b53_configure_vlan(struct b53_device * dev)566 static int b53_configure_vlan(struct b53_device *dev)
567 {
568 struct b53_vlan vl = { 0 };
569 int i;
570
571 /* clear all vlan entries */
572 if (is5325(dev) || is5365(dev)) {
573 for (i = 1; i < dev->num_vlans; i++)
574 b53_set_vlan_entry(dev, i, &vl);
575 } else {
576 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
577 }
578
579 b53_enable_vlan(dev, false);
580
581 b53_for_each_port(dev, i)
582 b53_write16(dev, B53_VLAN_PAGE,
583 B53_VLAN_PORT_DEF_TAG(i), 1);
584
585 if (!is5325(dev) && !is5365(dev))
586 b53_set_jumbo(dev, dev->enable_jumbo, false);
587
588 return 0;
589 }
590
b53_switch_reset_gpio(struct b53_device * dev)591 static void b53_switch_reset_gpio(struct b53_device *dev)
592 {
593 int gpio = dev->reset_gpio;
594
595 if (gpio < 0)
596 return;
597
598 /* Reset sequence: RESET low(50ms)->high(20ms)
599 */
600 gpio_set_value(gpio, 0);
601 mdelay(50);
602
603 gpio_set_value(gpio, 1);
604 mdelay(20);
605
606 dev->current_page = 0xff;
607 }
608
b53_switch_reset(struct b53_device * dev)609 static int b53_switch_reset(struct b53_device *dev)
610 {
611 u8 mgmt;
612
613 b53_switch_reset_gpio(dev);
614
615 if (is539x(dev)) {
616 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
617 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
618 }
619
620 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
621
622 if (!(mgmt & SM_SW_FWD_EN)) {
623 mgmt &= ~SM_SW_FWD_MODE;
624 mgmt |= SM_SW_FWD_EN;
625
626 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
627 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
628
629 if (!(mgmt & SM_SW_FWD_EN)) {
630 dev_err(dev->dev, "Failed to enable switch!\n");
631 return -EINVAL;
632 }
633 }
634
635 b53_enable_mib(dev);
636
637 return b53_flush_arl(dev, FAST_AGE_STATIC);
638 }
639
b53_phy_read16(struct dsa_switch * ds,int addr,int reg)640 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
641 {
642 struct b53_device *priv = ds->priv;
643 u16 value = 0;
644 int ret;
645
646 if (priv->ops->phy_read16)
647 ret = priv->ops->phy_read16(priv, addr, reg, &value);
648 else
649 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
650 reg * 2, &value);
651
652 return ret ? ret : value;
653 }
654
b53_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)655 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
656 {
657 struct b53_device *priv = ds->priv;
658
659 if (priv->ops->phy_write16)
660 return priv->ops->phy_write16(priv, addr, reg, val);
661
662 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
663 }
664
b53_reset_switch(struct b53_device * priv)665 static int b53_reset_switch(struct b53_device *priv)
666 {
667 /* reset vlans */
668 priv->enable_jumbo = false;
669
670 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
671 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
672
673 return b53_switch_reset(priv);
674 }
675
b53_apply_config(struct b53_device * priv)676 static int b53_apply_config(struct b53_device *priv)
677 {
678 /* disable switching */
679 b53_set_forwarding(priv, 0);
680
681 b53_configure_vlan(priv);
682
683 /* enable switching */
684 b53_set_forwarding(priv, 1);
685
686 return 0;
687 }
688
b53_reset_mib(struct b53_device * priv)689 static void b53_reset_mib(struct b53_device *priv)
690 {
691 u8 gc;
692
693 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
694
695 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
696 msleep(1);
697 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
698 msleep(1);
699 }
700
b53_get_mib(struct b53_device * dev)701 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
702 {
703 if (is5365(dev))
704 return b53_mibs_65;
705 else if (is63xx(dev))
706 return b53_mibs_63xx;
707 else if (is58xx(dev))
708 return b53_mibs_58xx;
709 else
710 return b53_mibs;
711 }
712
b53_get_mib_size(struct b53_device * dev)713 static unsigned int b53_get_mib_size(struct b53_device *dev)
714 {
715 if (is5365(dev))
716 return B53_MIBS_65_SIZE;
717 else if (is63xx(dev))
718 return B53_MIBS_63XX_SIZE;
719 else if (is58xx(dev))
720 return B53_MIBS_58XX_SIZE;
721 else
722 return B53_MIBS_SIZE;
723 }
724
b53_get_strings(struct dsa_switch * ds,int port,uint8_t * data)725 static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
726 {
727 struct b53_device *dev = ds->priv;
728 const struct b53_mib_desc *mibs = b53_get_mib(dev);
729 unsigned int mib_size = b53_get_mib_size(dev);
730 unsigned int i;
731
732 for (i = 0; i < mib_size; i++)
733 memcpy(data + i * ETH_GSTRING_LEN,
734 mibs[i].name, ETH_GSTRING_LEN);
735 }
736
b53_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)737 static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
738 uint64_t *data)
739 {
740 struct b53_device *dev = ds->priv;
741 const struct b53_mib_desc *mibs = b53_get_mib(dev);
742 unsigned int mib_size = b53_get_mib_size(dev);
743 const struct b53_mib_desc *s;
744 unsigned int i;
745 u64 val = 0;
746
747 if (is5365(dev) && port == 5)
748 port = 8;
749
750 mutex_lock(&dev->stats_mutex);
751
752 for (i = 0; i < mib_size; i++) {
753 s = &mibs[i];
754
755 if (s->size == 8) {
756 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
757 } else {
758 u32 val32;
759
760 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
761 &val32);
762 val = val32;
763 }
764 data[i] = (u64)val;
765 }
766
767 mutex_unlock(&dev->stats_mutex);
768 }
769
b53_get_sset_count(struct dsa_switch * ds)770 static int b53_get_sset_count(struct dsa_switch *ds)
771 {
772 struct b53_device *dev = ds->priv;
773
774 return b53_get_mib_size(dev);
775 }
776
b53_setup(struct dsa_switch * ds)777 static int b53_setup(struct dsa_switch *ds)
778 {
779 struct b53_device *dev = ds->priv;
780 unsigned int port;
781 int ret;
782
783 ret = b53_reset_switch(dev);
784 if (ret) {
785 dev_err(ds->dev, "failed to reset switch\n");
786 return ret;
787 }
788
789 b53_reset_mib(dev);
790
791 ret = b53_apply_config(dev);
792 if (ret)
793 dev_err(ds->dev, "failed to apply configuration\n");
794
795 for (port = 0; port < dev->num_ports; port++) {
796 if (BIT(port) & ds->enabled_port_mask)
797 b53_enable_port(ds, port, NULL);
798 else if (dsa_is_cpu_port(ds, port))
799 b53_enable_cpu_port(dev);
800 else
801 b53_disable_port(ds, port, NULL);
802 }
803
804 return ret;
805 }
806
b53_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)807 static void b53_adjust_link(struct dsa_switch *ds, int port,
808 struct phy_device *phydev)
809 {
810 struct b53_device *dev = ds->priv;
811 u8 rgmii_ctrl = 0, reg = 0, off;
812
813 if (!phy_is_pseudo_fixed_link(phydev))
814 return;
815
816 /* Override the port settings */
817 if (port == dev->cpu_port) {
818 off = B53_PORT_OVERRIDE_CTRL;
819 reg = PORT_OVERRIDE_EN;
820 } else {
821 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
822 reg = GMII_PO_EN;
823 }
824
825 /* Set the link UP */
826 if (phydev->link)
827 reg |= PORT_OVERRIDE_LINK;
828
829 if (phydev->duplex == DUPLEX_FULL)
830 reg |= PORT_OVERRIDE_FULL_DUPLEX;
831
832 switch (phydev->speed) {
833 case 2000:
834 reg |= PORT_OVERRIDE_SPEED_2000M;
835 /* fallthrough */
836 case SPEED_1000:
837 reg |= PORT_OVERRIDE_SPEED_1000M;
838 break;
839 case SPEED_100:
840 reg |= PORT_OVERRIDE_SPEED_100M;
841 break;
842 case SPEED_10:
843 reg |= PORT_OVERRIDE_SPEED_10M;
844 break;
845 default:
846 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
847 return;
848 }
849
850 /* Enable flow control on BCM5301x's CPU port */
851 if (is5301x(dev) && port == dev->cpu_port)
852 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
853
854 if (phydev->pause) {
855 if (phydev->asym_pause)
856 reg |= PORT_OVERRIDE_TX_FLOW;
857 reg |= PORT_OVERRIDE_RX_FLOW;
858 }
859
860 b53_write8(dev, B53_CTRL_PAGE, off, reg);
861
862 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
863 if (port == 8)
864 off = B53_RGMII_CTRL_IMP;
865 else
866 off = B53_RGMII_CTRL_P(port);
867
868 /* Configure the port RGMII clock delay by DLL disabled and
869 * tx_clk aligned timing (restoring to reset defaults)
870 */
871 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
872 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
873 RGMII_CTRL_TIMING_SEL);
874
875 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
876 * sure that we enable the port TX clock internal delay to
877 * account for this internal delay that is inserted, otherwise
878 * the switch won't be able to receive correctly.
879 *
880 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
881 * any delay neither on transmission nor reception, so the
882 * BCM53125 must also be configured accordingly to account for
883 * the lack of delay and introduce
884 *
885 * The BCM53125 switch has its RX clock and TX clock control
886 * swapped, hence the reason why we modify the TX clock path in
887 * the "RGMII" case
888 */
889 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
890 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
891 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
892 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
893 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
894 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
895
896 dev_info(ds->dev, "Configured port %d for %s\n", port,
897 phy_modes(phydev->interface));
898 }
899
900 /* configure MII port if necessary */
901 if (is5325(dev)) {
902 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
903 ®);
904
905 /* reverse mii needs to be enabled */
906 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
907 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
908 reg | PORT_OVERRIDE_RV_MII_25);
909 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
910 ®);
911
912 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
913 dev_err(ds->dev,
914 "Failed to enable reverse MII mode\n");
915 return;
916 }
917 }
918 } else if (is5301x(dev)) {
919 if (port != dev->cpu_port) {
920 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
921 u8 gmii_po;
922
923 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
924 gmii_po |= GMII_PO_LINK |
925 GMII_PO_RX_FLOW |
926 GMII_PO_TX_FLOW |
927 GMII_PO_EN |
928 GMII_PO_SPEED_2000M;
929 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
930 }
931 }
932 }
933
b53_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering)934 static int b53_vlan_filtering(struct dsa_switch *ds, int port,
935 bool vlan_filtering)
936 {
937 return 0;
938 }
939
b53_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct switchdev_trans * trans)940 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
941 const struct switchdev_obj_port_vlan *vlan,
942 struct switchdev_trans *trans)
943 {
944 struct b53_device *dev = ds->priv;
945
946 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
947 return -EOPNOTSUPP;
948
949 if (vlan->vid_end > dev->num_vlans)
950 return -ERANGE;
951
952 b53_enable_vlan(dev, true);
953
954 return 0;
955 }
956
b53_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct switchdev_trans * trans)957 static void b53_vlan_add(struct dsa_switch *ds, int port,
958 const struct switchdev_obj_port_vlan *vlan,
959 struct switchdev_trans *trans)
960 {
961 struct b53_device *dev = ds->priv;
962 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
963 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
964 unsigned int cpu_port = dev->cpu_port;
965 struct b53_vlan *vl;
966 u16 vid;
967
968 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
969 vl = &dev->vlans[vid];
970
971 b53_get_vlan_entry(dev, vid, vl);
972
973 vl->members |= BIT(port) | BIT(cpu_port);
974 if (untagged)
975 vl->untag |= BIT(port);
976 else
977 vl->untag &= ~BIT(port);
978 vl->untag &= ~BIT(cpu_port);
979
980 b53_set_vlan_entry(dev, vid, vl);
981 b53_fast_age_vlan(dev, vid);
982 }
983
984 if (pvid) {
985 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
986 vlan->vid_end);
987 b53_fast_age_vlan(dev, vid);
988 }
989 }
990
b53_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)991 static int b53_vlan_del(struct dsa_switch *ds, int port,
992 const struct switchdev_obj_port_vlan *vlan)
993 {
994 struct b53_device *dev = ds->priv;
995 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
996 struct b53_vlan *vl;
997 u16 vid;
998 u16 pvid;
999
1000 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1001
1002 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1003 vl = &dev->vlans[vid];
1004
1005 b53_get_vlan_entry(dev, vid, vl);
1006
1007 vl->members &= ~BIT(port);
1008
1009 if (pvid == vid) {
1010 if (is5325(dev) || is5365(dev))
1011 pvid = 1;
1012 else
1013 pvid = 0;
1014 }
1015
1016 if (untagged)
1017 vl->untag &= ~(BIT(port));
1018
1019 b53_set_vlan_entry(dev, vid, vl);
1020 b53_fast_age_vlan(dev, vid);
1021 }
1022
1023 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1024 b53_fast_age_vlan(dev, pvid);
1025
1026 return 0;
1027 }
1028
b53_vlan_dump(struct dsa_switch * ds,int port,struct switchdev_obj_port_vlan * vlan,int (* cb)(struct switchdev_obj * obj))1029 static int b53_vlan_dump(struct dsa_switch *ds, int port,
1030 struct switchdev_obj_port_vlan *vlan,
1031 int (*cb)(struct switchdev_obj *obj))
1032 {
1033 struct b53_device *dev = ds->priv;
1034 u16 vid, vid_start = 0, pvid;
1035 struct b53_vlan *vl;
1036 int err = 0;
1037
1038 if (is5325(dev) || is5365(dev))
1039 vid_start = 1;
1040
1041 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1042
1043 /* Use our software cache for dumps, since we do not have any HW
1044 * operation returning only the used/valid VLANs
1045 */
1046 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1047 vl = &dev->vlans[vid];
1048
1049 if (!vl->valid)
1050 continue;
1051
1052 if (!(vl->members & BIT(port)))
1053 continue;
1054
1055 vlan->vid_begin = vlan->vid_end = vid;
1056 vlan->flags = 0;
1057
1058 if (vl->untag & BIT(port))
1059 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1060 if (pvid == vid)
1061 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1062
1063 err = cb(&vlan->obj);
1064 if (err)
1065 break;
1066 }
1067
1068 return err;
1069 }
1070
1071 /* Address Resolution Logic routines */
b53_arl_op_wait(struct b53_device * dev)1072 static int b53_arl_op_wait(struct b53_device *dev)
1073 {
1074 unsigned int timeout = 10;
1075 u8 reg;
1076
1077 do {
1078 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1079 if (!(reg & ARLTBL_START_DONE))
1080 return 0;
1081
1082 usleep_range(1000, 2000);
1083 } while (timeout--);
1084
1085 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1086
1087 return -ETIMEDOUT;
1088 }
1089
b53_arl_rw_op(struct b53_device * dev,unsigned int op)1090 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1091 {
1092 u8 reg;
1093
1094 if (op > ARLTBL_RW)
1095 return -EINVAL;
1096
1097 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1098 reg |= ARLTBL_START_DONE;
1099 if (op)
1100 reg |= ARLTBL_RW;
1101 else
1102 reg &= ~ARLTBL_RW;
1103 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1104
1105 return b53_arl_op_wait(dev);
1106 }
1107
b53_arl_read(struct b53_device * dev,u64 mac,u16 vid,struct b53_arl_entry * ent,u8 * idx,bool is_valid)1108 static int b53_arl_read(struct b53_device *dev, u64 mac,
1109 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1110 bool is_valid)
1111 {
1112 unsigned int i;
1113 int ret;
1114
1115 ret = b53_arl_op_wait(dev);
1116 if (ret)
1117 return ret;
1118
1119 /* Read the bins */
1120 for (i = 0; i < dev->num_arl_entries; i++) {
1121 u64 mac_vid;
1122 u32 fwd_entry;
1123
1124 b53_read64(dev, B53_ARLIO_PAGE,
1125 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1126 b53_read32(dev, B53_ARLIO_PAGE,
1127 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1128 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1129
1130 if (!(fwd_entry & ARLTBL_VALID))
1131 continue;
1132 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1133 continue;
1134 *idx = i;
1135 }
1136
1137 return -ENOENT;
1138 }
1139
b53_arl_op(struct b53_device * dev,int op,int port,const unsigned char * addr,u16 vid,bool is_valid)1140 static int b53_arl_op(struct b53_device *dev, int op, int port,
1141 const unsigned char *addr, u16 vid, bool is_valid)
1142 {
1143 struct b53_arl_entry ent;
1144 u32 fwd_entry;
1145 u64 mac, mac_vid = 0;
1146 u8 idx = 0;
1147 int ret;
1148
1149 /* Convert the array into a 64-bit MAC */
1150 mac = b53_mac_to_u64(addr);
1151
1152 /* Perform a read for the given MAC and VID */
1153 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1154 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1155
1156 /* Issue a read operation for this MAC */
1157 ret = b53_arl_rw_op(dev, 1);
1158 if (ret)
1159 return ret;
1160
1161 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1162 /* If this is a read, just finish now */
1163 if (op)
1164 return ret;
1165
1166 /* We could not find a matching MAC, so reset to a new entry */
1167 if (ret) {
1168 fwd_entry = 0;
1169 idx = 1;
1170 }
1171
1172 memset(&ent, 0, sizeof(ent));
1173 ent.port = port;
1174 ent.is_valid = is_valid;
1175 ent.vid = vid;
1176 ent.is_static = true;
1177 memcpy(ent.mac, addr, ETH_ALEN);
1178 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1179
1180 b53_write64(dev, B53_ARLIO_PAGE,
1181 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1182 b53_write32(dev, B53_ARLIO_PAGE,
1183 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1184
1185 return b53_arl_rw_op(dev, 0);
1186 }
1187
b53_fdb_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_fdb * fdb,struct switchdev_trans * trans)1188 static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1189 const struct switchdev_obj_port_fdb *fdb,
1190 struct switchdev_trans *trans)
1191 {
1192 struct b53_device *priv = ds->priv;
1193
1194 /* 5325 and 5365 require some more massaging, but could
1195 * be supported eventually
1196 */
1197 if (is5325(priv) || is5365(priv))
1198 return -EOPNOTSUPP;
1199
1200 return 0;
1201 }
1202
b53_fdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_fdb * fdb,struct switchdev_trans * trans)1203 static void b53_fdb_add(struct dsa_switch *ds, int port,
1204 const struct switchdev_obj_port_fdb *fdb,
1205 struct switchdev_trans *trans)
1206 {
1207 struct b53_device *priv = ds->priv;
1208
1209 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1210 pr_err("%s: failed to add MAC address\n", __func__);
1211 }
1212
b53_fdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_fdb * fdb)1213 static int b53_fdb_del(struct dsa_switch *ds, int port,
1214 const struct switchdev_obj_port_fdb *fdb)
1215 {
1216 struct b53_device *priv = ds->priv;
1217
1218 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1219 }
1220
b53_arl_search_wait(struct b53_device * dev)1221 static int b53_arl_search_wait(struct b53_device *dev)
1222 {
1223 unsigned int timeout = 1000;
1224 u8 reg;
1225
1226 do {
1227 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1228 if (!(reg & ARL_SRCH_STDN))
1229 return 0;
1230
1231 if (reg & ARL_SRCH_VLID)
1232 return 0;
1233
1234 usleep_range(1000, 2000);
1235 } while (timeout--);
1236
1237 return -ETIMEDOUT;
1238 }
1239
b53_arl_search_rd(struct b53_device * dev,u8 idx,struct b53_arl_entry * ent)1240 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1241 struct b53_arl_entry *ent)
1242 {
1243 u64 mac_vid;
1244 u32 fwd_entry;
1245
1246 b53_read64(dev, B53_ARLIO_PAGE,
1247 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1248 b53_read32(dev, B53_ARLIO_PAGE,
1249 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1250 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1251 }
1252
b53_fdb_copy(struct net_device * dev,int port,const struct b53_arl_entry * ent,struct switchdev_obj_port_fdb * fdb,int (* cb)(struct switchdev_obj * obj))1253 static int b53_fdb_copy(struct net_device *dev, int port,
1254 const struct b53_arl_entry *ent,
1255 struct switchdev_obj_port_fdb *fdb,
1256 int (*cb)(struct switchdev_obj *obj))
1257 {
1258 if (!ent->is_valid)
1259 return 0;
1260
1261 if (port != ent->port)
1262 return 0;
1263
1264 ether_addr_copy(fdb->addr, ent->mac);
1265 fdb->vid = ent->vid;
1266 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1267
1268 return cb(&fdb->obj);
1269 }
1270
b53_fdb_dump(struct dsa_switch * ds,int port,struct switchdev_obj_port_fdb * fdb,int (* cb)(struct switchdev_obj * obj))1271 static int b53_fdb_dump(struct dsa_switch *ds, int port,
1272 struct switchdev_obj_port_fdb *fdb,
1273 int (*cb)(struct switchdev_obj *obj))
1274 {
1275 struct b53_device *priv = ds->priv;
1276 struct net_device *dev = ds->ports[port].netdev;
1277 struct b53_arl_entry results[2];
1278 unsigned int count = 0;
1279 int ret;
1280 u8 reg;
1281
1282 /* Start search operation */
1283 reg = ARL_SRCH_STDN;
1284 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1285
1286 do {
1287 ret = b53_arl_search_wait(priv);
1288 if (ret)
1289 return ret;
1290
1291 b53_arl_search_rd(priv, 0, &results[0]);
1292 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1293 if (ret)
1294 return ret;
1295
1296 if (priv->num_arl_entries > 2) {
1297 b53_arl_search_rd(priv, 1, &results[1]);
1298 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1299 if (ret)
1300 return ret;
1301
1302 if (!results[0].is_valid && !results[1].is_valid)
1303 break;
1304 }
1305
1306 } while (count++ < 1024);
1307
1308 return 0;
1309 }
1310
b53_br_join(struct dsa_switch * ds,int port,struct net_device * bridge)1311 static int b53_br_join(struct dsa_switch *ds, int port,
1312 struct net_device *bridge)
1313 {
1314 struct b53_device *dev = ds->priv;
1315 s8 cpu_port = ds->dst->cpu_port;
1316 u16 pvlan, reg;
1317 unsigned int i;
1318
1319 /* Make this port leave the all VLANs join since we will have proper
1320 * VLAN entries from now on
1321 */
1322 if (is58xx(dev)) {
1323 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1324 reg &= ~BIT(port);
1325 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1326 reg &= ~BIT(cpu_port);
1327 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1328 }
1329
1330 dev->ports[port].bridge_dev = bridge;
1331 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1332
1333 b53_for_each_port(dev, i) {
1334 if (dev->ports[i].bridge_dev != bridge)
1335 continue;
1336
1337 /* Add this local port to the remote port VLAN control
1338 * membership and update the remote port bitmask
1339 */
1340 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1341 reg |= BIT(port);
1342 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1343 dev->ports[i].vlan_ctl_mask = reg;
1344
1345 pvlan |= BIT(i);
1346 }
1347
1348 /* Configure the local port VLAN control membership to include
1349 * remote ports and update the local port bitmask
1350 */
1351 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1352 dev->ports[port].vlan_ctl_mask = pvlan;
1353
1354 return 0;
1355 }
1356
b53_br_leave(struct dsa_switch * ds,int port)1357 static void b53_br_leave(struct dsa_switch *ds, int port)
1358 {
1359 struct b53_device *dev = ds->priv;
1360 struct net_device *bridge = dev->ports[port].bridge_dev;
1361 struct b53_vlan *vl = &dev->vlans[0];
1362 s8 cpu_port = ds->dst->cpu_port;
1363 unsigned int i;
1364 u16 pvlan, reg, pvid;
1365
1366 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1367
1368 b53_for_each_port(dev, i) {
1369 /* Don't touch the remaining ports */
1370 if (dev->ports[i].bridge_dev != bridge)
1371 continue;
1372
1373 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1374 reg &= ~BIT(port);
1375 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1376 dev->ports[port].vlan_ctl_mask = reg;
1377
1378 /* Prevent self removal to preserve isolation */
1379 if (port != i)
1380 pvlan &= ~BIT(i);
1381 }
1382
1383 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1384 dev->ports[port].vlan_ctl_mask = pvlan;
1385 dev->ports[port].bridge_dev = NULL;
1386
1387 if (is5325(dev) || is5365(dev))
1388 pvid = 1;
1389 else
1390 pvid = 0;
1391
1392 /* Make this port join all VLANs without VLAN entries */
1393 if (is58xx(dev)) {
1394 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1395 reg |= BIT(port);
1396 if (!(reg & BIT(cpu_port)))
1397 reg |= BIT(cpu_port);
1398 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1399 } else {
1400 b53_get_vlan_entry(dev, pvid, vl);
1401 vl->members |= BIT(port) | BIT(dev->cpu_port);
1402 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1403 b53_set_vlan_entry(dev, pvid, vl);
1404 }
1405 }
1406
b53_br_set_stp_state(struct dsa_switch * ds,int port,u8 state)1407 static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1408 {
1409 struct b53_device *dev = ds->priv;
1410 u8 hw_state;
1411 u8 reg;
1412
1413 switch (state) {
1414 case BR_STATE_DISABLED:
1415 hw_state = PORT_CTRL_DIS_STATE;
1416 break;
1417 case BR_STATE_LISTENING:
1418 hw_state = PORT_CTRL_LISTEN_STATE;
1419 break;
1420 case BR_STATE_LEARNING:
1421 hw_state = PORT_CTRL_LEARN_STATE;
1422 break;
1423 case BR_STATE_FORWARDING:
1424 hw_state = PORT_CTRL_FWD_STATE;
1425 break;
1426 case BR_STATE_BLOCKING:
1427 hw_state = PORT_CTRL_BLOCK_STATE;
1428 break;
1429 default:
1430 dev_err(ds->dev, "invalid STP state: %d\n", state);
1431 return;
1432 }
1433
1434 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1435 reg &= ~PORT_CTRL_STP_STATE_MASK;
1436 reg |= hw_state;
1437 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1438 }
1439
b53_br_fast_age(struct dsa_switch * ds,int port)1440 static void b53_br_fast_age(struct dsa_switch *ds, int port)
1441 {
1442 struct b53_device *dev = ds->priv;
1443
1444 if (b53_fast_age_port(dev, port))
1445 dev_err(ds->dev, "fast ageing failed\n");
1446 }
1447
b53_get_tag_protocol(struct dsa_switch * ds)1448 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1449 {
1450 return DSA_TAG_PROTO_NONE;
1451 }
1452
1453 static struct dsa_switch_ops b53_switch_ops = {
1454 .get_tag_protocol = b53_get_tag_protocol,
1455 .setup = b53_setup,
1456 .get_strings = b53_get_strings,
1457 .get_ethtool_stats = b53_get_ethtool_stats,
1458 .get_sset_count = b53_get_sset_count,
1459 .phy_read = b53_phy_read16,
1460 .phy_write = b53_phy_write16,
1461 .adjust_link = b53_adjust_link,
1462 .port_enable = b53_enable_port,
1463 .port_disable = b53_disable_port,
1464 .port_bridge_join = b53_br_join,
1465 .port_bridge_leave = b53_br_leave,
1466 .port_stp_state_set = b53_br_set_stp_state,
1467 .port_fast_age = b53_br_fast_age,
1468 .port_vlan_filtering = b53_vlan_filtering,
1469 .port_vlan_prepare = b53_vlan_prepare,
1470 .port_vlan_add = b53_vlan_add,
1471 .port_vlan_del = b53_vlan_del,
1472 .port_vlan_dump = b53_vlan_dump,
1473 .port_fdb_prepare = b53_fdb_prepare,
1474 .port_fdb_dump = b53_fdb_dump,
1475 .port_fdb_add = b53_fdb_add,
1476 .port_fdb_del = b53_fdb_del,
1477 };
1478
1479 struct b53_chip_data {
1480 u32 chip_id;
1481 const char *dev_name;
1482 u16 vlans;
1483 u16 enabled_ports;
1484 u8 cpu_port;
1485 u8 vta_regs[3];
1486 u8 arl_entries;
1487 u8 duplex_reg;
1488 u8 jumbo_pm_reg;
1489 u8 jumbo_size_reg;
1490 };
1491
1492 #define B53_VTA_REGS \
1493 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1494 #define B53_VTA_REGS_9798 \
1495 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1496 #define B53_VTA_REGS_63XX \
1497 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1498
1499 static const struct b53_chip_data b53_switch_chips[] = {
1500 {
1501 .chip_id = BCM5325_DEVICE_ID,
1502 .dev_name = "BCM5325",
1503 .vlans = 16,
1504 .enabled_ports = 0x1f,
1505 .arl_entries = 2,
1506 .cpu_port = B53_CPU_PORT_25,
1507 .duplex_reg = B53_DUPLEX_STAT_FE,
1508 },
1509 {
1510 .chip_id = BCM5365_DEVICE_ID,
1511 .dev_name = "BCM5365",
1512 .vlans = 256,
1513 .enabled_ports = 0x1f,
1514 .arl_entries = 2,
1515 .cpu_port = B53_CPU_PORT_25,
1516 .duplex_reg = B53_DUPLEX_STAT_FE,
1517 },
1518 {
1519 .chip_id = BCM5395_DEVICE_ID,
1520 .dev_name = "BCM5395",
1521 .vlans = 4096,
1522 .enabled_ports = 0x1f,
1523 .arl_entries = 4,
1524 .cpu_port = B53_CPU_PORT,
1525 .vta_regs = B53_VTA_REGS,
1526 .duplex_reg = B53_DUPLEX_STAT_GE,
1527 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1528 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1529 },
1530 {
1531 .chip_id = BCM5397_DEVICE_ID,
1532 .dev_name = "BCM5397",
1533 .vlans = 4096,
1534 .enabled_ports = 0x1f,
1535 .arl_entries = 4,
1536 .cpu_port = B53_CPU_PORT,
1537 .vta_regs = B53_VTA_REGS_9798,
1538 .duplex_reg = B53_DUPLEX_STAT_GE,
1539 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1540 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1541 },
1542 {
1543 .chip_id = BCM5398_DEVICE_ID,
1544 .dev_name = "BCM5398",
1545 .vlans = 4096,
1546 .enabled_ports = 0x7f,
1547 .arl_entries = 4,
1548 .cpu_port = B53_CPU_PORT,
1549 .vta_regs = B53_VTA_REGS_9798,
1550 .duplex_reg = B53_DUPLEX_STAT_GE,
1551 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1552 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1553 },
1554 {
1555 .chip_id = BCM53115_DEVICE_ID,
1556 .dev_name = "BCM53115",
1557 .vlans = 4096,
1558 .enabled_ports = 0x1f,
1559 .arl_entries = 4,
1560 .vta_regs = B53_VTA_REGS,
1561 .cpu_port = B53_CPU_PORT,
1562 .duplex_reg = B53_DUPLEX_STAT_GE,
1563 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1564 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1565 },
1566 {
1567 .chip_id = BCM53125_DEVICE_ID,
1568 .dev_name = "BCM53125",
1569 .vlans = 4096,
1570 .enabled_ports = 0xff,
1571 .arl_entries = 4,
1572 .cpu_port = B53_CPU_PORT,
1573 .vta_regs = B53_VTA_REGS,
1574 .duplex_reg = B53_DUPLEX_STAT_GE,
1575 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1576 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1577 },
1578 {
1579 .chip_id = BCM53128_DEVICE_ID,
1580 .dev_name = "BCM53128",
1581 .vlans = 4096,
1582 .enabled_ports = 0x1ff,
1583 .arl_entries = 4,
1584 .cpu_port = B53_CPU_PORT,
1585 .vta_regs = B53_VTA_REGS,
1586 .duplex_reg = B53_DUPLEX_STAT_GE,
1587 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1588 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1589 },
1590 {
1591 .chip_id = BCM63XX_DEVICE_ID,
1592 .dev_name = "BCM63xx",
1593 .vlans = 4096,
1594 .enabled_ports = 0, /* pdata must provide them */
1595 .arl_entries = 4,
1596 .cpu_port = B53_CPU_PORT,
1597 .vta_regs = B53_VTA_REGS_63XX,
1598 .duplex_reg = B53_DUPLEX_STAT_63XX,
1599 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1600 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1601 },
1602 {
1603 .chip_id = BCM53010_DEVICE_ID,
1604 .dev_name = "BCM53010",
1605 .vlans = 4096,
1606 .enabled_ports = 0x1f,
1607 .arl_entries = 4,
1608 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1609 .vta_regs = B53_VTA_REGS,
1610 .duplex_reg = B53_DUPLEX_STAT_GE,
1611 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1612 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1613 },
1614 {
1615 .chip_id = BCM53011_DEVICE_ID,
1616 .dev_name = "BCM53011",
1617 .vlans = 4096,
1618 .enabled_ports = 0x1bf,
1619 .arl_entries = 4,
1620 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1621 .vta_regs = B53_VTA_REGS,
1622 .duplex_reg = B53_DUPLEX_STAT_GE,
1623 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1624 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1625 },
1626 {
1627 .chip_id = BCM53012_DEVICE_ID,
1628 .dev_name = "BCM53012",
1629 .vlans = 4096,
1630 .enabled_ports = 0x1bf,
1631 .arl_entries = 4,
1632 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1633 .vta_regs = B53_VTA_REGS,
1634 .duplex_reg = B53_DUPLEX_STAT_GE,
1635 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1636 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1637 },
1638 {
1639 .chip_id = BCM53018_DEVICE_ID,
1640 .dev_name = "BCM53018",
1641 .vlans = 4096,
1642 .enabled_ports = 0x1f,
1643 .arl_entries = 4,
1644 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1645 .vta_regs = B53_VTA_REGS,
1646 .duplex_reg = B53_DUPLEX_STAT_GE,
1647 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1648 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1649 },
1650 {
1651 .chip_id = BCM53019_DEVICE_ID,
1652 .dev_name = "BCM53019",
1653 .vlans = 4096,
1654 .enabled_ports = 0x1f,
1655 .arl_entries = 4,
1656 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1657 .vta_regs = B53_VTA_REGS,
1658 .duplex_reg = B53_DUPLEX_STAT_GE,
1659 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1660 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1661 },
1662 {
1663 .chip_id = BCM58XX_DEVICE_ID,
1664 .dev_name = "BCM585xx/586xx/88312",
1665 .vlans = 4096,
1666 .enabled_ports = 0x1ff,
1667 .arl_entries = 4,
1668 .cpu_port = B53_CPU_PORT_25,
1669 .vta_regs = B53_VTA_REGS,
1670 .duplex_reg = B53_DUPLEX_STAT_GE,
1671 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1672 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1673 },
1674 {
1675 .chip_id = BCM7445_DEVICE_ID,
1676 .dev_name = "BCM7445",
1677 .vlans = 4096,
1678 .enabled_ports = 0x1ff,
1679 .arl_entries = 4,
1680 .cpu_port = B53_CPU_PORT,
1681 .vta_regs = B53_VTA_REGS,
1682 .duplex_reg = B53_DUPLEX_STAT_GE,
1683 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1684 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1685 },
1686 };
1687
b53_switch_init(struct b53_device * dev)1688 static int b53_switch_init(struct b53_device *dev)
1689 {
1690 unsigned int i;
1691 int ret;
1692
1693 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1694 const struct b53_chip_data *chip = &b53_switch_chips[i];
1695
1696 if (chip->chip_id == dev->chip_id) {
1697 if (!dev->enabled_ports)
1698 dev->enabled_ports = chip->enabled_ports;
1699 dev->name = chip->dev_name;
1700 dev->duplex_reg = chip->duplex_reg;
1701 dev->vta_regs[0] = chip->vta_regs[0];
1702 dev->vta_regs[1] = chip->vta_regs[1];
1703 dev->vta_regs[2] = chip->vta_regs[2];
1704 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1705 dev->cpu_port = chip->cpu_port;
1706 dev->num_vlans = chip->vlans;
1707 dev->num_arl_entries = chip->arl_entries;
1708 break;
1709 }
1710 }
1711
1712 /* check which BCM5325x version we have */
1713 if (is5325(dev)) {
1714 u8 vc4;
1715
1716 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1717
1718 /* check reserved bits */
1719 switch (vc4 & 3) {
1720 case 1:
1721 /* BCM5325E */
1722 break;
1723 case 3:
1724 /* BCM5325F - do not use port 4 */
1725 dev->enabled_ports &= ~BIT(4);
1726 break;
1727 default:
1728 /* On the BCM47XX SoCs this is the supported internal switch.*/
1729 #ifndef CONFIG_BCM47XX
1730 /* BCM5325M */
1731 return -EINVAL;
1732 #else
1733 break;
1734 #endif
1735 }
1736 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1737 u64 strap_value;
1738
1739 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1740 /* use second IMP port if GMII is enabled */
1741 if (strap_value & SV_GMII_CTRL_115)
1742 dev->cpu_port = 5;
1743 }
1744
1745 /* cpu port is always last */
1746 dev->num_ports = dev->cpu_port + 1;
1747 dev->enabled_ports |= BIT(dev->cpu_port);
1748
1749 dev->ports = devm_kzalloc(dev->dev,
1750 sizeof(struct b53_port) * dev->num_ports,
1751 GFP_KERNEL);
1752 if (!dev->ports)
1753 return -ENOMEM;
1754
1755 dev->vlans = devm_kzalloc(dev->dev,
1756 sizeof(struct b53_vlan) * dev->num_vlans,
1757 GFP_KERNEL);
1758 if (!dev->vlans)
1759 return -ENOMEM;
1760
1761 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1762 if (dev->reset_gpio >= 0) {
1763 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1764 GPIOF_OUT_INIT_HIGH, "robo_reset");
1765 if (ret)
1766 return ret;
1767 }
1768
1769 return 0;
1770 }
1771
b53_switch_alloc(struct device * base,const struct b53_io_ops * ops,void * priv)1772 struct b53_device *b53_switch_alloc(struct device *base,
1773 const struct b53_io_ops *ops,
1774 void *priv)
1775 {
1776 struct dsa_switch *ds;
1777 struct b53_device *dev;
1778
1779 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1780 if (!ds)
1781 return NULL;
1782
1783 dev = (struct b53_device *)(ds + 1);
1784
1785 ds->priv = dev;
1786 ds->dev = base;
1787 dev->dev = base;
1788
1789 dev->ds = ds;
1790 dev->priv = priv;
1791 dev->ops = ops;
1792 ds->ops = &b53_switch_ops;
1793 mutex_init(&dev->reg_mutex);
1794 mutex_init(&dev->stats_mutex);
1795
1796 return dev;
1797 }
1798 EXPORT_SYMBOL(b53_switch_alloc);
1799
b53_switch_detect(struct b53_device * dev)1800 int b53_switch_detect(struct b53_device *dev)
1801 {
1802 u32 id32;
1803 u16 tmp;
1804 u8 id8;
1805 int ret;
1806
1807 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1808 if (ret)
1809 return ret;
1810
1811 switch (id8) {
1812 case 0:
1813 /* BCM5325 and BCM5365 do not have this register so reads
1814 * return 0. But the read operation did succeed, so assume this
1815 * is one of them.
1816 *
1817 * Next check if we can write to the 5325's VTA register; for
1818 * 5365 it is read only.
1819 */
1820 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1821 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1822
1823 if (tmp == 0xf)
1824 dev->chip_id = BCM5325_DEVICE_ID;
1825 else
1826 dev->chip_id = BCM5365_DEVICE_ID;
1827 break;
1828 case BCM5395_DEVICE_ID:
1829 case BCM5397_DEVICE_ID:
1830 case BCM5398_DEVICE_ID:
1831 dev->chip_id = id8;
1832 break;
1833 default:
1834 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1835 if (ret)
1836 return ret;
1837
1838 switch (id32) {
1839 case BCM53115_DEVICE_ID:
1840 case BCM53125_DEVICE_ID:
1841 case BCM53128_DEVICE_ID:
1842 case BCM53010_DEVICE_ID:
1843 case BCM53011_DEVICE_ID:
1844 case BCM53012_DEVICE_ID:
1845 case BCM53018_DEVICE_ID:
1846 case BCM53019_DEVICE_ID:
1847 dev->chip_id = id32;
1848 break;
1849 default:
1850 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1851 id8, id32);
1852 return -ENODEV;
1853 }
1854 }
1855
1856 if (dev->chip_id == BCM5325_DEVICE_ID)
1857 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1858 &dev->core_rev);
1859 else
1860 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1861 &dev->core_rev);
1862 }
1863 EXPORT_SYMBOL(b53_switch_detect);
1864
b53_switch_register(struct b53_device * dev)1865 int b53_switch_register(struct b53_device *dev)
1866 {
1867 int ret;
1868
1869 if (dev->pdata) {
1870 dev->chip_id = dev->pdata->chip_id;
1871 dev->enabled_ports = dev->pdata->enabled_ports;
1872 }
1873
1874 if (!dev->chip_id && b53_switch_detect(dev))
1875 return -EINVAL;
1876
1877 ret = b53_switch_init(dev);
1878 if (ret)
1879 return ret;
1880
1881 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1882
1883 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1884 }
1885 EXPORT_SYMBOL(b53_switch_register);
1886
1887 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1888 MODULE_DESCRIPTION("B53 switch library");
1889 MODULE_LICENSE("Dual BSD/GPL");
1890