1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _HWMGR_H_ 24 #define _HWMGR_H_ 25 26 #include <linux/seq_file.h> 27 #include "amd_powerplay.h" 28 #include "pp_instance.h" 29 #include "hardwaremanager.h" 30 #include "pp_power_source.h" 31 #include "hwmgr_ppt.h" 32 #include "ppatomctrl.h" 33 #include "hwmgr_ppt.h" 34 #include "power_state.h" 35 36 struct pp_instance; 37 struct pp_hwmgr; 38 struct phm_fan_speed_info; 39 struct pp_atomctrl_voltage_table; 40 41 extern int amdgpu_powercontainment; 42 extern int amdgpu_sclk_deep_sleep_en; 43 extern unsigned amdgpu_pp_feature_mask; 44 45 #define VOLTAGE_SCALE 4 46 47 uint8_t convert_to_vid(uint16_t vddc); 48 49 enum DISPLAY_GAP { 50 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 51 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 52 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ 53 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ 54 }; 55 typedef enum DISPLAY_GAP DISPLAY_GAP; 56 57 struct vi_dpm_level { 58 bool enabled; 59 uint32_t value; 60 uint32_t param1; 61 }; 62 63 struct vi_dpm_table { 64 uint32_t count; 65 struct vi_dpm_level dpm_level[1]; 66 }; 67 68 enum PP_Result { 69 PP_Result_TableImmediateExit = 0x13, 70 }; 71 72 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 73 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 74 #define PCIE_PERF_REQ_GEN1 2 75 #define PCIE_PERF_REQ_GEN2 3 76 #define PCIE_PERF_REQ_GEN3 4 77 78 enum PP_FEATURE_MASK { 79 PP_SCLK_DPM_MASK = 0x1, 80 PP_MCLK_DPM_MASK = 0x2, 81 PP_PCIE_DPM_MASK = 0x4, 82 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 83 PP_POWER_CONTAINMENT_MASK = 0x10, 84 PP_UVD_HANDSHAKE_MASK = 0x20, 85 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 86 PP_VBI_TIME_SUPPORT_MASK = 0x80, 87 PP_ULV_MASK = 0x100, 88 PP_ENABLE_GFX_CG_THRU_SMU = 0x200 89 }; 90 91 enum PHM_BackEnd_Magic { 92 PHM_Dummy_Magic = 0xAA5555AA, 93 PHM_RV770_Magic = 0xDCBAABCD, 94 PHM_Kong_Magic = 0x239478DF, 95 PHM_NIslands_Magic = 0x736C494E, 96 PHM_Sumo_Magic = 0x8339FA11, 97 PHM_SIslands_Magic = 0x369431AC, 98 PHM_Trinity_Magic = 0x96751873, 99 PHM_CIslands_Magic = 0x38AC78B0, 100 PHM_Kv_Magic = 0xDCBBABC0, 101 PHM_VIslands_Magic = 0x20130307, 102 PHM_Cz_Magic = 0x67DCBA25 103 }; 104 105 106 #define PHM_PCIE_POWERGATING_TARGET_GFX 0 107 #define PHM_PCIE_POWERGATING_TARGET_DDI 1 108 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 109 #define PHM_PCIE_POWERGATING_TARGET_PHY 3 110 111 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, 112 void *output, void *storage, int result); 113 114 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); 115 116 struct phm_set_power_state_input { 117 const struct pp_hw_power_state *pcurrent_state; 118 const struct pp_hw_power_state *pnew_state; 119 }; 120 121 struct phm_acp_arbiter { 122 uint32_t acpclk; 123 }; 124 125 struct phm_uvd_arbiter { 126 uint32_t vclk; 127 uint32_t dclk; 128 uint32_t vclk_ceiling; 129 uint32_t dclk_ceiling; 130 }; 131 132 struct phm_vce_arbiter { 133 uint32_t evclk; 134 uint32_t ecclk; 135 }; 136 137 struct phm_gfx_arbiter { 138 uint32_t sclk; 139 uint32_t mclk; 140 uint32_t sclk_over_drive; 141 uint32_t mclk_over_drive; 142 uint32_t sclk_threshold; 143 uint32_t num_cus; 144 }; 145 146 /* Entries in the master tables */ 147 struct phm_master_table_item { 148 phm_check_function isFunctionNeededInRuntimeTable; 149 phm_table_function tableFunction; 150 }; 151 152 enum phm_master_table_flag { 153 PHM_MasterTableFlag_None = 0, 154 PHM_MasterTableFlag_ExitOnError = 1, 155 }; 156 157 /* The header of the master tables */ 158 struct phm_master_table_header { 159 uint32_t storage_size; 160 uint32_t flags; 161 const struct phm_master_table_item *master_list; 162 }; 163 164 struct phm_runtime_table_header { 165 uint32_t storage_size; 166 bool exit_error; 167 phm_table_function *function_list; 168 }; 169 170 struct phm_clock_array { 171 uint32_t count; 172 uint32_t values[1]; 173 }; 174 175 struct phm_clock_voltage_dependency_record { 176 uint32_t clk; 177 uint32_t v; 178 }; 179 180 struct phm_vceclock_voltage_dependency_record { 181 uint32_t ecclk; 182 uint32_t evclk; 183 uint32_t v; 184 }; 185 186 struct phm_uvdclock_voltage_dependency_record { 187 uint32_t vclk; 188 uint32_t dclk; 189 uint32_t v; 190 }; 191 192 struct phm_samuclock_voltage_dependency_record { 193 uint32_t samclk; 194 uint32_t v; 195 }; 196 197 struct phm_acpclock_voltage_dependency_record { 198 uint32_t acpclk; 199 uint32_t v; 200 }; 201 202 struct phm_clock_voltage_dependency_table { 203 uint32_t count; /* Number of entries. */ 204 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 205 }; 206 207 struct phm_phase_shedding_limits_record { 208 uint32_t Voltage; 209 uint32_t Sclk; 210 uint32_t Mclk; 211 }; 212 213 214 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, 215 struct phm_runtime_table_header *rt_table, 216 void *input, void *output); 217 218 extern int phm_construct_table(struct pp_hwmgr *hwmgr, 219 const struct phm_master_table_header *master_table, 220 struct phm_runtime_table_header *rt_table); 221 222 extern int phm_destroy_table(struct pp_hwmgr *hwmgr, 223 struct phm_runtime_table_header *rt_table); 224 225 226 struct phm_uvd_clock_voltage_dependency_record { 227 uint32_t vclk; 228 uint32_t dclk; 229 uint32_t v; 230 }; 231 232 struct phm_uvd_clock_voltage_dependency_table { 233 uint8_t count; 234 struct phm_uvd_clock_voltage_dependency_record entries[1]; 235 }; 236 237 struct phm_acp_clock_voltage_dependency_record { 238 uint32_t acpclk; 239 uint32_t v; 240 }; 241 242 struct phm_acp_clock_voltage_dependency_table { 243 uint32_t count; 244 struct phm_acp_clock_voltage_dependency_record entries[1]; 245 }; 246 247 struct phm_vce_clock_voltage_dependency_record { 248 uint32_t ecclk; 249 uint32_t evclk; 250 uint32_t v; 251 }; 252 253 struct phm_phase_shedding_limits_table { 254 uint32_t count; 255 struct phm_phase_shedding_limits_record entries[1]; 256 }; 257 258 struct phm_vceclock_voltage_dependency_table { 259 uint8_t count; /* Number of entries. */ 260 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 261 }; 262 263 struct phm_uvdclock_voltage_dependency_table { 264 uint8_t count; /* Number of entries. */ 265 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 266 }; 267 268 struct phm_samuclock_voltage_dependency_table { 269 uint8_t count; /* Number of entries. */ 270 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 271 }; 272 273 struct phm_acpclock_voltage_dependency_table { 274 uint32_t count; /* Number of entries. */ 275 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 276 }; 277 278 struct phm_vce_clock_voltage_dependency_table { 279 uint8_t count; 280 struct phm_vce_clock_voltage_dependency_record entries[1]; 281 }; 282 283 struct pp_hwmgr_func { 284 int (*backend_init)(struct pp_hwmgr *hw_mgr); 285 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 286 int (*asic_setup)(struct pp_hwmgr *hw_mgr); 287 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); 288 289 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, 290 struct pp_power_state *prequest_ps, 291 const struct pp_power_state *pcurrent_ps); 292 293 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, 294 enum amd_dpm_forced_level level); 295 296 int (*dynamic_state_management_enable)( 297 struct pp_hwmgr *hw_mgr); 298 int (*dynamic_state_management_disable)( 299 struct pp_hwmgr *hw_mgr); 300 301 int (*patch_boot_state)(struct pp_hwmgr *hwmgr, 302 struct pp_hw_power_state *hw_ps); 303 304 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, 305 unsigned long, struct pp_power_state *); 306 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); 307 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); 308 int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); 309 int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); 310 int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); 311 int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); 312 int (*power_state_set)(struct pp_hwmgr *hwmgr, 313 const void *state); 314 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); 315 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); 316 int (*display_config_changed)(struct pp_hwmgr *hwmgr); 317 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); 318 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, 319 const uint32_t *msg_id); 320 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 321 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 322 int (*get_temperature)(struct pp_hwmgr *hwmgr); 323 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); 324 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); 325 int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); 326 int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); 327 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); 328 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); 329 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); 330 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 331 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); 332 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); 333 int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr, 334 const void *thermal_interrupt_info); 335 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); 336 int (*check_states_equal)(struct pp_hwmgr *hwmgr, 337 const struct pp_hw_power_state *pstate1, 338 const struct pp_hw_power_state *pstate2, 339 bool *equal); 340 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); 341 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, 342 bool cc6_disable, bool pstate_disable, 343 bool pstate_switch_disable); 344 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, 345 struct amd_pp_simple_clock_info *info); 346 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, 347 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); 348 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, 349 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); 350 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); 351 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); 352 int (*power_off_asic)(struct pp_hwmgr *hwmgr); 353 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); 354 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); 355 int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable); 356 int (*get_sclk_od)(struct pp_hwmgr *hwmgr); 357 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 358 int (*get_mclk_od)(struct pp_hwmgr *hwmgr); 359 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 360 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, int32_t *value); 361 }; 362 363 struct pp_table_func { 364 int (*pptable_init)(struct pp_hwmgr *hw_mgr); 365 int (*pptable_fini)(struct pp_hwmgr *hw_mgr); 366 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); 367 int (*pptable_get_vce_state_table_entry)( 368 struct pp_hwmgr *hwmgr, 369 unsigned long i, 370 struct pp_vce_state *vce_state, 371 void **clock_info, 372 unsigned long *flag); 373 }; 374 375 union phm_cac_leakage_record { 376 struct { 377 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ 378 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ 379 }; 380 struct { 381 uint16_t Vddc1; 382 uint16_t Vddc2; 383 uint16_t Vddc3; 384 }; 385 }; 386 387 struct phm_cac_leakage_table { 388 uint32_t count; 389 union phm_cac_leakage_record entries[1]; 390 }; 391 392 struct phm_samu_clock_voltage_dependency_record { 393 uint32_t samclk; 394 uint32_t v; 395 }; 396 397 398 struct phm_samu_clock_voltage_dependency_table { 399 uint8_t count; 400 struct phm_samu_clock_voltage_dependency_record entries[1]; 401 }; 402 403 struct phm_cac_tdp_table { 404 uint16_t usTDP; 405 uint16_t usConfigurableTDP; 406 uint16_t usTDC; 407 uint16_t usBatteryPowerLimit; 408 uint16_t usSmallPowerLimit; 409 uint16_t usLowCACLeakage; 410 uint16_t usHighCACLeakage; 411 uint16_t usMaximumPowerDeliveryLimit; 412 uint16_t usOperatingTempMinLimit; 413 uint16_t usOperatingTempMaxLimit; 414 uint16_t usOperatingTempStep; 415 uint16_t usOperatingTempHyst; 416 uint16_t usDefaultTargetOperatingTemp; 417 uint16_t usTargetOperatingTemp; 418 uint16_t usPowerTuneDataSetID; 419 uint16_t usSoftwareShutdownTemp; 420 uint16_t usClockStretchAmount; 421 uint16_t usTemperatureLimitHotspot; 422 uint16_t usTemperatureLimitLiquid1; 423 uint16_t usTemperatureLimitLiquid2; 424 uint16_t usTemperatureLimitVrVddc; 425 uint16_t usTemperatureLimitVrMvdd; 426 uint16_t usTemperatureLimitPlx; 427 uint8_t ucLiquid1_I2C_address; 428 uint8_t ucLiquid2_I2C_address; 429 uint8_t ucLiquid_I2C_Line; 430 uint8_t ucVr_I2C_address; 431 uint8_t ucVr_I2C_Line; 432 uint8_t ucPlx_I2C_address; 433 uint8_t ucPlx_I2C_Line; 434 uint32_t usBoostPowerLimit; 435 uint8_t ucCKS_LDO_REFSEL; 436 }; 437 438 struct phm_ppm_table { 439 uint8_t ppm_design; 440 uint16_t cpu_core_number; 441 uint32_t platform_tdp; 442 uint32_t small_ac_platform_tdp; 443 uint32_t platform_tdc; 444 uint32_t small_ac_platform_tdc; 445 uint32_t apu_tdp; 446 uint32_t dgpu_tdp; 447 uint32_t dgpu_ulv_power; 448 uint32_t tj_max; 449 }; 450 451 struct phm_vq_budgeting_record { 452 uint32_t ulCUs; 453 uint32_t ulSustainableSOCPowerLimitLow; 454 uint32_t ulSustainableSOCPowerLimitHigh; 455 uint32_t ulMinSclkLow; 456 uint32_t ulMinSclkHigh; 457 uint8_t ucDispConfig; 458 uint32_t ulDClk; 459 uint32_t ulEClk; 460 uint32_t ulSustainableSclk; 461 uint32_t ulSustainableCUs; 462 }; 463 464 struct phm_vq_budgeting_table { 465 uint8_t numEntries; 466 struct phm_vq_budgeting_record entries[1]; 467 }; 468 469 struct phm_clock_and_voltage_limits { 470 uint32_t sclk; 471 uint32_t mclk; 472 uint16_t vddc; 473 uint16_t vddci; 474 uint16_t vddgfx; 475 }; 476 477 /* Structure to hold PPTable information */ 478 479 struct phm_ppt_v1_information { 480 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 481 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 482 struct phm_clock_array *valid_sclk_values; 483 struct phm_clock_array *valid_mclk_values; 484 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 485 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 486 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 487 struct phm_ppm_table *ppm_parameter_table; 488 struct phm_cac_tdp_table *cac_dtp_table; 489 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 490 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 491 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 492 struct phm_ppt_v1_pcie_table *pcie_table; 493 uint16_t us_ulv_voltage_offset; 494 }; 495 496 struct phm_dynamic_state_info { 497 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; 498 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; 499 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; 500 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; 501 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 502 struct phm_clock_array *valid_sclk_values; 503 struct phm_clock_array *valid_mclk_values; 504 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 505 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 506 uint32_t mclk_sclk_ratio; 507 uint32_t sclk_mclk_delta; 508 uint32_t vddc_vddci_delta; 509 uint32_t min_vddc_for_pcie_gen2; 510 struct phm_cac_leakage_table *cac_leakage_table; 511 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; 512 513 struct phm_vce_clock_voltage_dependency_table 514 *vce_clock_voltage_dependency_table; 515 struct phm_uvd_clock_voltage_dependency_table 516 *uvd_clock_voltage_dependency_table; 517 struct phm_acp_clock_voltage_dependency_table 518 *acp_clock_voltage_dependency_table; 519 struct phm_samu_clock_voltage_dependency_table 520 *samu_clock_voltage_dependency_table; 521 522 struct phm_ppm_table *ppm_parameter_table; 523 struct phm_cac_tdp_table *cac_dtp_table; 524 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; 525 struct phm_vq_budgeting_table *vq_budgeting_table; 526 }; 527 528 struct pp_fan_info { 529 bool bNoFan; 530 uint8_t ucTachometerPulsesPerRevolution; 531 uint32_t ulMinRPM; 532 uint32_t ulMaxRPM; 533 }; 534 535 struct pp_advance_fan_control_parameters { 536 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ 537 uint16_t usTMed; /* The middle temperature where we change slopes. */ 538 uint16_t usTHigh; /* The high temperature for setting the second slope. */ 539 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ 540 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ 541 uint16_t usPWMHigh; /* The PWM value at THigh. */ 542 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ 543 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ 544 uint16_t usTMax; /* The max temperature */ 545 uint8_t ucFanControlMode; 546 uint16_t usFanPWMMinLimit; 547 uint16_t usFanPWMMaxLimit; 548 uint16_t usFanPWMStep; 549 uint16_t usDefaultMaxFanPWM; 550 uint16_t usFanOutputSensitivity; 551 uint16_t usDefaultFanOutputSensitivity; 552 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ 553 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ 554 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ 555 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ 556 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ 557 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ 558 uint16_t usFanCurrentLow; /* Low current */ 559 uint16_t usFanCurrentHigh; /* High current */ 560 uint16_t usFanRPMLow; /* Low RPM */ 561 uint16_t usFanRPMHigh; /* High RPM */ 562 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ 563 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ 564 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ 565 uint16_t usFanGainEdge; /* The following is added for Fiji */ 566 uint16_t usFanGainHotspot; 567 uint16_t usFanGainLiquid; 568 uint16_t usFanGainVrVddc; 569 uint16_t usFanGainVrMvdd; 570 uint16_t usFanGainPlx; 571 uint16_t usFanGainHbm; 572 }; 573 574 struct pp_thermal_controller_info { 575 uint8_t ucType; 576 uint8_t ucI2cLine; 577 uint8_t ucI2cAddress; 578 struct pp_fan_info fanInfo; 579 struct pp_advance_fan_control_parameters advanceFanControlParameters; 580 }; 581 582 struct phm_microcode_version_info { 583 uint32_t SMC; 584 uint32_t DMCU; 585 uint32_t MC; 586 uint32_t NB; 587 }; 588 589 #define PP_MAX_VCE_LEVELS 6 590 591 enum PP_VCE_LEVEL { 592 PP_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 593 PP_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 594 PP_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 595 PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 596 PP_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 597 PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 598 }; 599 600 601 enum PP_TABLE_VERSION { 602 PP_TABLE_V0 = 0, 603 PP_TABLE_V1, 604 PP_TABLE_V2, 605 PP_TABLE_MAX 606 }; 607 608 /** 609 * The main hardware manager structure. 610 */ 611 struct pp_hwmgr { 612 uint32_t chip_family; 613 uint32_t chip_id; 614 615 uint32_t pp_table_version; 616 void *device; 617 struct pp_smumgr *smumgr; 618 const void *soft_pp_table; 619 uint32_t soft_pp_table_size; 620 void *hardcode_pp_table; 621 bool need_pp_table_upload; 622 623 struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS]; 624 uint32_t num_vce_state_tables; 625 626 enum amd_dpm_forced_level dpm_level; 627 bool block_hw_access; 628 struct phm_gfx_arbiter gfx_arbiter; 629 struct phm_acp_arbiter acp_arbiter; 630 struct phm_uvd_arbiter uvd_arbiter; 631 struct phm_vce_arbiter vce_arbiter; 632 uint32_t usec_timeout; 633 void *pptable; 634 struct phm_platform_descriptor platform_descriptor; 635 void *backend; 636 enum PP_DAL_POWERLEVEL dal_power_level; 637 struct phm_dynamic_state_info dyn_state; 638 struct phm_runtime_table_header setup_asic; 639 struct phm_runtime_table_header power_down_asic; 640 struct phm_runtime_table_header disable_dynamic_state_management; 641 struct phm_runtime_table_header enable_dynamic_state_management; 642 struct phm_runtime_table_header set_power_state; 643 struct phm_runtime_table_header enable_clock_power_gatings; 644 struct phm_runtime_table_header display_configuration_changed; 645 struct phm_runtime_table_header start_thermal_controller; 646 struct phm_runtime_table_header set_temperature_range; 647 const struct pp_hwmgr_func *hwmgr_func; 648 const struct pp_table_func *pptable_func; 649 struct pp_power_state *ps; 650 enum pp_power_source power_source; 651 uint32_t num_ps; 652 struct pp_thermal_controller_info thermal_controller; 653 bool fan_ctrl_is_in_default_mode; 654 uint32_t fan_ctrl_default_mode; 655 uint32_t tmin; 656 struct phm_microcode_version_info microcode_version_info; 657 uint32_t ps_size; 658 struct pp_power_state *current_ps; 659 struct pp_power_state *request_ps; 660 struct pp_power_state *boot_ps; 661 struct pp_power_state *uvd_ps; 662 struct amd_pp_display_configuration display_config; 663 uint32_t feature_mask; 664 }; 665 666 667 extern int hwmgr_init(struct amd_pp_init *pp_init, 668 struct pp_instance *handle); 669 670 extern int hwmgr_fini(struct pp_hwmgr *hwmgr); 671 672 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr); 673 674 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, 675 uint32_t value, uint32_t mask); 676 677 678 679 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, 680 uint32_t indirect_port, 681 uint32_t index, 682 uint32_t value, 683 uint32_t mask); 684 685 686 687 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); 688 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); 689 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); 690 691 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); 692 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); 693 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); 694 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); 695 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); 696 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); 697 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); 698 extern int32_t phm_get_dpm_level_enable_mask_value(void *table); 699 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table, 700 uint32_t voltage); 701 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); 702 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); 703 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); 704 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, 705 uint16_t virtual_voltage_id, int32_t *sclk); 706 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 707 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); 708 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); 709 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); 710 711 extern int smu7_hwmgr_init(struct pp_hwmgr *hwmgr); 712 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 713 uint32_t sclk, uint16_t id, uint16_t *voltage); 714 715 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU 716 717 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 718 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK 719 720 #define PHM_SET_FIELD(origval, reg, field, fieldval) \ 721 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ 722 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) 723 724 #define PHM_GET_FIELD(value, reg, field) \ 725 (((value) & PHM_FIELD_MASK(reg, field)) >> \ 726 PHM_FIELD_SHIFT(reg, field)) 727 728 729 /* Operations on named fields. */ 730 731 #define PHM_READ_FIELD(device, reg, field) \ 732 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) 733 734 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ 735 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 736 reg, field) 737 738 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ 739 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 740 reg, field) 741 742 #define PHM_WRITE_FIELD(device, reg, field, fieldval) \ 743 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ 744 cgs_read_register(device, mm##reg), reg, field, fieldval)) 745 746 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ 747 cgs_write_ind_register(device, port, ix##reg, \ 748 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 749 reg, field, fieldval)) 750 751 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ 752 cgs_write_ind_register(device, port, ix##reg, \ 753 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 754 reg, field, fieldval)) 755 756 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ 757 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) 758 759 760 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ 761 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) 762 763 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ 764 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ 765 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) 766 767 768 #endif /* _HWMGR_H_ */ 769