1 #ifndef DRIVERS_PCI_H
2 #define DRIVERS_PCI_H
3
4 #define PCI_CFG_SPACE_SIZE 256
5 #define PCI_CFG_SPACE_EXP_SIZE 4096
6
7 #define PCI_FIND_CAP_TTL 48
8
9 extern const unsigned char pcie_link_speed[];
10
11 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
13 /* Functions internal to the PCI core code */
14
15 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
17 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
pci_create_firmware_label_files(struct pci_dev * pdev)18 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19 { return; }
pci_remove_firmware_label_files(struct pci_dev * pdev)20 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
21 { return; }
22 #else
23 void pci_create_firmware_label_files(struct pci_dev *pdev);
24 void pci_remove_firmware_label_files(struct pci_dev *pdev);
25 #endif
26 void pci_cleanup_rom(struct pci_dev *dev);
27 #ifdef HAVE_PCI_MMAP
28 enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31 };
32 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
34 #endif
35 int pci_probe_reset_function(struct pci_dev *dev);
36
37 /**
38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
42 *
43 * @set_state: invokes the platform firmware to set the device's power state
44 *
45 * @get_state: queries the platform firmware for a device's current power state
46 *
47 * @choose_state: returns PCI power state of given device preferred by the
48 * platform; to be used during system-wide transitions from a
49 * sleeping state to the working state and vice versa
50 *
51 * @sleep_wake: enables/disables the system wake up capability of given device
52 *
53 * @run_wake: enables/disables the platform to generate run-time wake-up events
54 * for given device (the device's wake-up capability has to be
55 * enabled by @sleep_wake for this feature to work)
56 *
57 * @need_resume: returns 'true' if the given device (which is currently
58 * suspended) needs to be resumed to be configured for system
59 * wakeup.
60 *
61 * If given platform is generally capable of power managing PCI devices, all of
62 * these callbacks are mandatory.
63 */
64 struct pci_platform_pm_ops {
65 bool (*is_manageable)(struct pci_dev *dev);
66 int (*set_state)(struct pci_dev *dev, pci_power_t state);
67 pci_power_t (*get_state)(struct pci_dev *dev);
68 pci_power_t (*choose_state)(struct pci_dev *dev);
69 int (*sleep_wake)(struct pci_dev *dev, bool enable);
70 int (*run_wake)(struct pci_dev *dev, bool enable);
71 bool (*need_resume)(struct pci_dev *dev);
72 };
73
74 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
75 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
76 void pci_power_up(struct pci_dev *dev);
77 void pci_disable_enabled_device(struct pci_dev *dev);
78 int pci_finish_runtime_suspend(struct pci_dev *dev);
79 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
80 bool pci_dev_keep_suspended(struct pci_dev *dev);
81 void pci_dev_complete_resume(struct pci_dev *pci_dev);
82 void pci_config_pm_runtime_get(struct pci_dev *dev);
83 void pci_config_pm_runtime_put(struct pci_dev *dev);
84 void pci_pm_init(struct pci_dev *dev);
85 void pci_ea_init(struct pci_dev *dev);
86 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
87 void pci_free_cap_save_buffers(struct pci_dev *dev);
88 void pci_bridge_d3_device_changed(struct pci_dev *dev);
89 void pci_bridge_d3_device_removed(struct pci_dev *dev);
90
pci_wakeup_event(struct pci_dev * dev)91 static inline void pci_wakeup_event(struct pci_dev *dev)
92 {
93 /* Wait 100 ms before the system can be put into a sleep state. */
94 pm_wakeup_event(&dev->dev, 100);
95 }
96
pci_has_subordinate(struct pci_dev * pci_dev)97 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
98 {
99 return !!(pci_dev->subordinate);
100 }
101
pci_power_manageable(struct pci_dev * pci_dev)102 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
103 {
104 /*
105 * Currently we allow normal PCI devices and PCI bridges transition
106 * into D3 if their bridge_d3 is set.
107 */
108 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
109 }
110
111 struct pci_vpd_ops {
112 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
113 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
114 int (*set_size)(struct pci_dev *dev, size_t len);
115 };
116
117 struct pci_vpd {
118 const struct pci_vpd_ops *ops;
119 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
120 struct mutex lock;
121 unsigned int len;
122 u16 flag;
123 u8 cap;
124 u8 busy:1;
125 u8 valid:1;
126 };
127
128 int pci_vpd_init(struct pci_dev *dev);
129 void pci_vpd_release(struct pci_dev *dev);
130
131 /* PCI /proc functions */
132 #ifdef CONFIG_PROC_FS
133 int pci_proc_attach_device(struct pci_dev *dev);
134 int pci_proc_detach_device(struct pci_dev *dev);
135 int pci_proc_detach_bus(struct pci_bus *bus);
136 #else
pci_proc_attach_device(struct pci_dev * dev)137 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)138 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)139 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
140 #endif
141
142 /* Functions for PCI Hotplug drivers to use */
143 int pci_hp_add_bridge(struct pci_dev *dev);
144
145 #ifdef HAVE_PCI_LEGACY
146 void pci_create_legacy_files(struct pci_bus *bus);
147 void pci_remove_legacy_files(struct pci_bus *bus);
148 #else
pci_create_legacy_files(struct pci_bus * bus)149 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
pci_remove_legacy_files(struct pci_bus * bus)150 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
151 #endif
152
153 /* Lock for read/write access to pci device and bus lists */
154 extern struct rw_semaphore pci_bus_sem;
155
156 extern raw_spinlock_t pci_lock;
157
158 extern unsigned int pci_pm_d3_delay;
159
160 #ifdef CONFIG_PCI_MSI
161 void pci_no_msi(void);
162 #else
pci_no_msi(void)163 static inline void pci_no_msi(void) { }
164 #endif
165
pci_msi_set_enable(struct pci_dev * dev,int enable)166 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
167 {
168 u16 control;
169
170 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
171 control &= ~PCI_MSI_FLAGS_ENABLE;
172 if (enable)
173 control |= PCI_MSI_FLAGS_ENABLE;
174 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
175 }
176
pci_msix_clear_and_set_ctrl(struct pci_dev * dev,u16 clear,u16 set)177 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
178 {
179 u16 ctrl;
180
181 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
182 ctrl &= ~clear;
183 ctrl |= set;
184 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
185 }
186
187 void pci_realloc_get_opt(char *);
188
pci_no_d1d2(struct pci_dev * dev)189 static inline int pci_no_d1d2(struct pci_dev *dev)
190 {
191 unsigned int parent_dstates = 0;
192
193 if (dev->bus->self)
194 parent_dstates = dev->bus->self->no_d1d2;
195 return (dev->no_d1d2 || parent_dstates);
196
197 }
198 extern const struct attribute_group *pci_dev_groups[];
199 extern const struct attribute_group *pcibus_groups[];
200 extern struct device_type pci_dev_type;
201 extern const struct attribute_group *pci_bus_groups[];
202
203
204 /**
205 * pci_match_one_device - Tell if a PCI device structure has a matching
206 * PCI device id structure
207 * @id: single PCI device id structure to match
208 * @dev: the PCI device structure to match against
209 *
210 * Returns the matching pci_device_id structure or %NULL if there is no match.
211 */
212 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)213 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
214 {
215 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
216 (id->device == PCI_ANY_ID || id->device == dev->device) &&
217 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
218 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
219 !((id->class ^ dev->class) & id->class_mask))
220 return id;
221 return NULL;
222 }
223
224 /* PCI slot sysfs helper code */
225 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
226
227 extern struct kset *pci_slots_kset;
228
229 struct pci_slot_attribute {
230 struct attribute attr;
231 ssize_t (*show)(struct pci_slot *, char *);
232 ssize_t (*store)(struct pci_slot *, const char *, size_t);
233 };
234 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
235
236 enum pci_bar_type {
237 pci_bar_unknown, /* Standard PCI BAR probe */
238 pci_bar_io, /* An io port BAR */
239 pci_bar_mem32, /* A 32-bit memory BAR */
240 pci_bar_mem64, /* A 64-bit memory BAR */
241 };
242
243 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
244 int crs_timeout);
245 int pci_setup_device(struct pci_dev *dev);
246 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
247 struct resource *res, unsigned int reg);
248 void pci_configure_ari(struct pci_dev *dev);
249 void __pci_bus_size_bridges(struct pci_bus *bus,
250 struct list_head *realloc_head);
251 void __pci_bus_assign_resources(const struct pci_bus *bus,
252 struct list_head *realloc_head,
253 struct list_head *fail_head);
254 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
255
256 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
257 void pci_disable_bridge_window(struct pci_dev *dev);
258
259 /* Single Root I/O Virtualization */
260 struct pci_sriov {
261 int pos; /* capability position */
262 int nres; /* number of resources */
263 u32 cap; /* SR-IOV Capabilities */
264 u16 ctrl; /* SR-IOV Control */
265 u16 total_VFs; /* total VFs associated with the PF */
266 u16 initial_VFs; /* initial VFs associated with the PF */
267 u16 num_VFs; /* number of VFs available */
268 u16 offset; /* first VF Routing ID offset */
269 u16 stride; /* following VF stride */
270 u32 pgsz; /* page size for BAR alignment */
271 u8 link; /* Function Dependency Link */
272 u8 max_VF_buses; /* max buses consumed by VFs */
273 u16 driver_max_VFs; /* max num VFs driver supports */
274 struct pci_dev *dev; /* lowest numbered PF */
275 struct pci_dev *self; /* this PF */
276 struct mutex lock; /* lock for VF bus */
277 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
278 };
279
280 #ifdef CONFIG_PCI_ATS
281 void pci_restore_ats_state(struct pci_dev *dev);
282 #else
pci_restore_ats_state(struct pci_dev * dev)283 static inline void pci_restore_ats_state(struct pci_dev *dev)
284 {
285 }
286 #endif /* CONFIG_PCI_ATS */
287
288 #ifdef CONFIG_PCI_IOV
289 int pci_iov_init(struct pci_dev *dev);
290 void pci_iov_release(struct pci_dev *dev);
291 void pci_iov_update_resource(struct pci_dev *dev, int resno);
292 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
293 void pci_restore_iov_state(struct pci_dev *dev);
294 int pci_iov_bus_range(struct pci_bus *bus);
295
296 #else
pci_iov_init(struct pci_dev * dev)297 static inline int pci_iov_init(struct pci_dev *dev)
298 {
299 return -ENODEV;
300 }
pci_iov_release(struct pci_dev * dev)301 static inline void pci_iov_release(struct pci_dev *dev)
302
303 {
304 }
pci_restore_iov_state(struct pci_dev * dev)305 static inline void pci_restore_iov_state(struct pci_dev *dev)
306 {
307 }
pci_iov_bus_range(struct pci_bus * bus)308 static inline int pci_iov_bus_range(struct pci_bus *bus)
309 {
310 return 0;
311 }
312
313 #endif /* CONFIG_PCI_IOV */
314
315 unsigned long pci_cardbus_resource_alignment(struct resource *);
316
pci_resource_alignment(struct pci_dev * dev,struct resource * res)317 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
318 struct resource *res)
319 {
320 #ifdef CONFIG_PCI_IOV
321 int resno = res - dev->resource;
322
323 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
324 return pci_sriov_resource_alignment(dev, resno);
325 #endif
326 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
327 return pci_cardbus_resource_alignment(res);
328 return resource_alignment(res);
329 }
330
331 void pci_enable_acs(struct pci_dev *dev);
332
333 #ifdef CONFIG_PCIE_PTM
334 void pci_ptm_init(struct pci_dev *dev);
335 #else
pci_ptm_init(struct pci_dev * dev)336 static inline void pci_ptm_init(struct pci_dev *dev) { }
337 #endif
338
339 struct pci_dev_reset_methods {
340 u16 vendor;
341 u16 device;
342 int (*reset)(struct pci_dev *dev, int probe);
343 };
344
345 #ifdef CONFIG_PCI_QUIRKS
346 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
347 #else
pci_dev_specific_reset(struct pci_dev * dev,int probe)348 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
349 {
350 return -ENOTTY;
351 }
352 #endif
353
354 #endif /* DRIVERS_PCI_H */
355