1 /*
2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
4
5 GPL LICENSE SUMMARY
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 Contact Information:
17 qat-linux@intel.com
18
19 BSD LICENSE
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
23 are met:
24
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
30 distribution.
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
34
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 */
47 #include <linux/kernel.h>
48 #include <linux/pci.h>
49 #include <linux/aer.h>
50 #include <linux/completion.h>
51 #include <linux/workqueue.h>
52 #include <linux/delay.h>
53 #include "adf_accel_devices.h"
54 #include "adf_common_drv.h"
55
56 static struct workqueue_struct *device_reset_wq;
57
adf_error_detected(struct pci_dev * pdev,pci_channel_state_t state)58 static pci_ers_result_t adf_error_detected(struct pci_dev *pdev,
59 pci_channel_state_t state)
60 {
61 struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
62
63 dev_info(&pdev->dev, "Acceleration driver hardware error detected.\n");
64 if (!accel_dev) {
65 dev_err(&pdev->dev, "Can't find acceleration device\n");
66 return PCI_ERS_RESULT_DISCONNECT;
67 }
68
69 if (state == pci_channel_io_perm_failure) {
70 dev_err(&pdev->dev, "Can't recover from device error\n");
71 return PCI_ERS_RESULT_DISCONNECT;
72 }
73
74 return PCI_ERS_RESULT_NEED_RESET;
75 }
76
77 /* reset dev data */
78 struct adf_reset_dev_data {
79 int mode;
80 struct adf_accel_dev *accel_dev;
81 struct completion compl;
82 struct work_struct reset_work;
83 };
84
adf_reset_sbr(struct adf_accel_dev * accel_dev)85 void adf_reset_sbr(struct adf_accel_dev *accel_dev)
86 {
87 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
88 struct pci_dev *parent = pdev->bus->self;
89 uint16_t bridge_ctl = 0;
90
91 if (!parent)
92 parent = pdev;
93
94 if (!pci_wait_for_pending_transaction(pdev))
95 dev_info(&GET_DEV(accel_dev),
96 "Transaction still in progress. Proceeding\n");
97
98 dev_info(&GET_DEV(accel_dev), "Secondary bus reset\n");
99
100 pci_read_config_word(parent, PCI_BRIDGE_CONTROL, &bridge_ctl);
101 bridge_ctl |= PCI_BRIDGE_CTL_BUS_RESET;
102 pci_write_config_word(parent, PCI_BRIDGE_CONTROL, bridge_ctl);
103 msleep(100);
104 bridge_ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
105 pci_write_config_word(parent, PCI_BRIDGE_CONTROL, bridge_ctl);
106 msleep(100);
107 }
108 EXPORT_SYMBOL_GPL(adf_reset_sbr);
109
adf_reset_flr(struct adf_accel_dev * accel_dev)110 void adf_reset_flr(struct adf_accel_dev *accel_dev)
111 {
112 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
113 u16 control = 0;
114 int pos = 0;
115
116 dev_info(&GET_DEV(accel_dev), "Function level reset\n");
117 pos = pci_pcie_cap(pdev);
118 if (!pos) {
119 dev_err(&GET_DEV(accel_dev), "Restart device failed\n");
120 return;
121 }
122 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &control);
123 control |= PCI_EXP_DEVCTL_BCR_FLR;
124 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, control);
125 msleep(100);
126 }
127 EXPORT_SYMBOL_GPL(adf_reset_flr);
128
adf_dev_restore(struct adf_accel_dev * accel_dev)129 void adf_dev_restore(struct adf_accel_dev *accel_dev)
130 {
131 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
132 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
133
134 if (hw_device->reset_device) {
135 dev_info(&GET_DEV(accel_dev), "Resetting device qat_dev%d\n",
136 accel_dev->accel_id);
137 hw_device->reset_device(accel_dev);
138 pci_restore_state(pdev);
139 pci_save_state(pdev);
140 }
141 }
142
adf_device_reset_worker(struct work_struct * work)143 static void adf_device_reset_worker(struct work_struct *work)
144 {
145 struct adf_reset_dev_data *reset_data =
146 container_of(work, struct adf_reset_dev_data, reset_work);
147 struct adf_accel_dev *accel_dev = reset_data->accel_dev;
148
149 adf_dev_restarting_notify(accel_dev);
150 adf_dev_stop(accel_dev);
151 adf_dev_shutdown(accel_dev);
152 if (adf_dev_init(accel_dev) || adf_dev_start(accel_dev)) {
153 /* The device hanged and we can't restart it so stop here */
154 dev_err(&GET_DEV(accel_dev), "Restart device failed\n");
155 kfree(reset_data);
156 WARN(1, "QAT: device restart failed. Device is unusable\n");
157 return;
158 }
159 adf_dev_restarted_notify(accel_dev);
160 clear_bit(ADF_STATUS_RESTARTING, &accel_dev->status);
161
162 /* The dev is back alive. Notify the caller if in sync mode */
163 if (reset_data->mode == ADF_DEV_RESET_SYNC)
164 complete(&reset_data->compl);
165 else
166 kfree(reset_data);
167 }
168
adf_dev_aer_schedule_reset(struct adf_accel_dev * accel_dev,enum adf_dev_reset_mode mode)169 static int adf_dev_aer_schedule_reset(struct adf_accel_dev *accel_dev,
170 enum adf_dev_reset_mode mode)
171 {
172 struct adf_reset_dev_data *reset_data;
173
174 if (!adf_dev_started(accel_dev) ||
175 test_bit(ADF_STATUS_RESTARTING, &accel_dev->status))
176 return 0;
177
178 set_bit(ADF_STATUS_RESTARTING, &accel_dev->status);
179 reset_data = kzalloc(sizeof(*reset_data), GFP_ATOMIC);
180 if (!reset_data)
181 return -ENOMEM;
182 reset_data->accel_dev = accel_dev;
183 init_completion(&reset_data->compl);
184 reset_data->mode = mode;
185 INIT_WORK(&reset_data->reset_work, adf_device_reset_worker);
186 queue_work(device_reset_wq, &reset_data->reset_work);
187
188 /* If in sync mode wait for the result */
189 if (mode == ADF_DEV_RESET_SYNC) {
190 int ret = 0;
191 /* Maximum device reset time is 10 seconds */
192 unsigned long wait_jiffies = msecs_to_jiffies(10000);
193 unsigned long timeout = wait_for_completion_timeout(
194 &reset_data->compl, wait_jiffies);
195 if (!timeout) {
196 dev_err(&GET_DEV(accel_dev),
197 "Reset device timeout expired\n");
198 ret = -EFAULT;
199 }
200 kfree(reset_data);
201 return ret;
202 }
203 return 0;
204 }
205
adf_slot_reset(struct pci_dev * pdev)206 static pci_ers_result_t adf_slot_reset(struct pci_dev *pdev)
207 {
208 struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
209
210 if (!accel_dev) {
211 pr_err("QAT: Can't find acceleration device\n");
212 return PCI_ERS_RESULT_DISCONNECT;
213 }
214 pci_cleanup_aer_uncorrect_error_status(pdev);
215 if (adf_dev_aer_schedule_reset(accel_dev, ADF_DEV_RESET_SYNC))
216 return PCI_ERS_RESULT_DISCONNECT;
217
218 return PCI_ERS_RESULT_RECOVERED;
219 }
220
adf_resume(struct pci_dev * pdev)221 static void adf_resume(struct pci_dev *pdev)
222 {
223 dev_info(&pdev->dev, "Acceleration driver reset completed\n");
224 dev_info(&pdev->dev, "Device is up and runnig\n");
225 }
226
227 static const struct pci_error_handlers adf_err_handler = {
228 .error_detected = adf_error_detected,
229 .slot_reset = adf_slot_reset,
230 .resume = adf_resume,
231 };
232
233 /**
234 * adf_enable_aer() - Enable Advance Error Reporting for acceleration device
235 * @accel_dev: Pointer to acceleration device.
236 * @adf: PCI device driver owning the given acceleration device.
237 *
238 * Function enables PCI Advance Error Reporting for the
239 * QAT acceleration device accel_dev.
240 * To be used by QAT device specific drivers.
241 *
242 * Return: 0 on success, error code otherwise.
243 */
adf_enable_aer(struct adf_accel_dev * accel_dev,struct pci_driver * adf)244 int adf_enable_aer(struct adf_accel_dev *accel_dev, struct pci_driver *adf)
245 {
246 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
247
248 adf->err_handler = &adf_err_handler;
249 pci_enable_pcie_error_reporting(pdev);
250 return 0;
251 }
252 EXPORT_SYMBOL_GPL(adf_enable_aer);
253
254 /**
255 * adf_disable_aer() - Enable Advance Error Reporting for acceleration device
256 * @accel_dev: Pointer to acceleration device.
257 *
258 * Function disables PCI Advance Error Reporting for the
259 * QAT acceleration device accel_dev.
260 * To be used by QAT device specific drivers.
261 *
262 * Return: void
263 */
adf_disable_aer(struct adf_accel_dev * accel_dev)264 void adf_disable_aer(struct adf_accel_dev *accel_dev)
265 {
266 struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
267
268 pci_disable_pcie_error_reporting(pdev);
269 }
270 EXPORT_SYMBOL_GPL(adf_disable_aer);
271
adf_init_aer(void)272 int adf_init_aer(void)
273 {
274 device_reset_wq = alloc_workqueue("qat_device_reset_wq",
275 WQ_MEM_RECLAIM, 0);
276 return !device_reset_wq ? -EFAULT : 0;
277 }
278
adf_exit_aer(void)279 void adf_exit_aer(void)
280 {
281 if (device_reset_wq)
282 destroy_workqueue(device_reset_wq);
283 device_reset_wq = NULL;
284 }
285