1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __IW_CXGB4_H__
32 #define __IW_CXGB4_H__
33
34 #include <linux/mutex.h>
35 #include <linux/list.h>
36 #include <linux/spinlock.h>
37 #include <linux/idr.h>
38 #include <linux/completion.h>
39 #include <linux/netdevice.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/inet.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
47 #include <linux/io.h>
48 #include <linux/workqueue.h>
49
50 #include <asm/byteorder.h>
51
52 #include <net/net_namespace.h>
53
54 #include <rdma/ib_verbs.h>
55 #include <rdma/iw_cm.h>
56 #include <rdma/rdma_netlink.h>
57 #include <rdma/iw_portmap.h>
58
59 #include "cxgb4.h"
60 #include "cxgb4_uld.h"
61 #include "l2t.h"
62 #include <rdma/cxgb4-abi.h>
63
64 #define DRV_NAME "iw_cxgb4"
65 #define MOD DRV_NAME ":"
66
67 extern int c4iw_debug;
68 #define PDBG(fmt, args...) \
69 do { \
70 if (c4iw_debug) \
71 printk(MOD fmt, ## args); \
72 } while (0)
73
74 #include "t4.h"
75
76 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
77 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
78
cplhdr(struct sk_buff * skb)79 static inline void *cplhdr(struct sk_buff *skb)
80 {
81 return skb->data;
82 }
83
84 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
85 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
86
87 struct c4iw_id_table {
88 u32 flags;
89 u32 start; /* logical minimal id */
90 u32 last; /* hint for find */
91 u32 max;
92 spinlock_t lock;
93 unsigned long *table;
94 };
95
96 struct c4iw_resource {
97 struct c4iw_id_table tpt_table;
98 struct c4iw_id_table qid_table;
99 struct c4iw_id_table pdid_table;
100 };
101
102 struct c4iw_qid_list {
103 struct list_head entry;
104 u32 qid;
105 };
106
107 struct c4iw_dev_ucontext {
108 struct list_head qpids;
109 struct list_head cqids;
110 struct mutex lock;
111 struct kref kref;
112 };
113
114 enum c4iw_rdev_flags {
115 T4_FATAL_ERROR = (1<<0),
116 T4_STATUS_PAGE_DISABLED = (1<<1),
117 };
118
119 struct c4iw_stat {
120 u64 total;
121 u64 cur;
122 u64 max;
123 u64 fail;
124 };
125
126 struct c4iw_stats {
127 struct mutex lock;
128 struct c4iw_stat qid;
129 struct c4iw_stat pd;
130 struct c4iw_stat stag;
131 struct c4iw_stat pbl;
132 struct c4iw_stat rqt;
133 struct c4iw_stat ocqp;
134 u64 db_full;
135 u64 db_empty;
136 u64 db_drop;
137 u64 db_state_transitions;
138 u64 db_fc_interruptions;
139 u64 tcam_full;
140 u64 act_ofld_conn_fails;
141 u64 pas_ofld_conn_fails;
142 u64 neg_adv;
143 };
144
145 struct c4iw_hw_queue {
146 int t4_eq_status_entries;
147 int t4_max_eq_size;
148 int t4_max_iq_size;
149 int t4_max_rq_size;
150 int t4_max_sq_size;
151 int t4_max_qp_depth;
152 int t4_max_cq_depth;
153 int t4_stat_len;
154 };
155
156 struct wr_log_entry {
157 struct timespec post_host_ts;
158 struct timespec poll_host_ts;
159 u64 post_sge_ts;
160 u64 cqe_sge_ts;
161 u64 poll_sge_ts;
162 u16 qid;
163 u16 wr_id;
164 u8 opcode;
165 u8 valid;
166 };
167
168 struct c4iw_rdev {
169 struct c4iw_resource resource;
170 u32 qpmask;
171 u32 cqmask;
172 struct c4iw_dev_ucontext uctx;
173 struct gen_pool *pbl_pool;
174 struct gen_pool *rqt_pool;
175 struct gen_pool *ocqp_pool;
176 u32 flags;
177 struct cxgb4_lld_info lldi;
178 unsigned long bar2_pa;
179 void __iomem *bar2_kva;
180 unsigned long oc_mw_pa;
181 void __iomem *oc_mw_kva;
182 struct c4iw_stats stats;
183 struct c4iw_hw_queue hw_queue;
184 struct t4_dev_status_page *status_page;
185 atomic_t wr_log_idx;
186 struct wr_log_entry *wr_log;
187 int wr_log_size;
188 struct workqueue_struct *free_workq;
189 };
190
c4iw_fatal_error(struct c4iw_rdev * rdev)191 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
192 {
193 return rdev->flags & T4_FATAL_ERROR;
194 }
195
c4iw_num_stags(struct c4iw_rdev * rdev)196 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
197 {
198 return (int)(rdev->lldi.vr->stag.size >> 5);
199 }
200
201 #define C4IW_WR_TO (60*HZ)
202
203 struct c4iw_wr_wait {
204 struct completion completion;
205 int ret;
206 };
207
c4iw_init_wr_wait(struct c4iw_wr_wait * wr_waitp)208 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
209 {
210 wr_waitp->ret = 0;
211 init_completion(&wr_waitp->completion);
212 }
213
c4iw_wake_up(struct c4iw_wr_wait * wr_waitp,int ret)214 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
215 {
216 wr_waitp->ret = ret;
217 complete(&wr_waitp->completion);
218 }
219
c4iw_wait_for_reply(struct c4iw_rdev * rdev,struct c4iw_wr_wait * wr_waitp,u32 hwtid,u32 qpid,const char * func)220 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
221 struct c4iw_wr_wait *wr_waitp,
222 u32 hwtid, u32 qpid,
223 const char *func)
224 {
225 int ret;
226
227 if (c4iw_fatal_error(rdev)) {
228 wr_waitp->ret = -EIO;
229 goto out;
230 }
231
232 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
233 if (!ret) {
234 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
235 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
236 rdev->flags |= T4_FATAL_ERROR;
237 wr_waitp->ret = -EIO;
238 }
239 out:
240 if (wr_waitp->ret)
241 PDBG("%s: FW reply %d tid %u qpid %u\n",
242 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
243 return wr_waitp->ret;
244 }
245
246 enum db_state {
247 NORMAL = 0,
248 FLOW_CONTROL = 1,
249 RECOVERY = 2,
250 STOPPED = 3
251 };
252
253 struct c4iw_dev {
254 struct ib_device ibdev;
255 struct c4iw_rdev rdev;
256 u32 device_cap_flags;
257 struct idr cqidr;
258 struct idr qpidr;
259 struct idr mmidr;
260 spinlock_t lock;
261 struct mutex db_mutex;
262 struct dentry *debugfs_root;
263 enum db_state db_state;
264 struct idr hwtid_idr;
265 struct idr atid_idr;
266 struct idr stid_idr;
267 struct list_head db_fc_list;
268 u32 avail_ird;
269 wait_queue_head_t wait;
270 };
271
to_c4iw_dev(struct ib_device * ibdev)272 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
273 {
274 return container_of(ibdev, struct c4iw_dev, ibdev);
275 }
276
rdev_to_c4iw_dev(struct c4iw_rdev * rdev)277 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
278 {
279 return container_of(rdev, struct c4iw_dev, rdev);
280 }
281
get_chp(struct c4iw_dev * rhp,u32 cqid)282 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
283 {
284 return idr_find(&rhp->cqidr, cqid);
285 }
286
get_qhp(struct c4iw_dev * rhp,u32 qpid)287 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
288 {
289 return idr_find(&rhp->qpidr, qpid);
290 }
291
get_mhp(struct c4iw_dev * rhp,u32 mmid)292 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
293 {
294 return idr_find(&rhp->mmidr, mmid);
295 }
296
_insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id,int lock)297 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
298 void *handle, u32 id, int lock)
299 {
300 int ret;
301
302 if (lock) {
303 idr_preload(GFP_KERNEL);
304 spin_lock_irq(&rhp->lock);
305 }
306
307 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
308
309 if (lock) {
310 spin_unlock_irq(&rhp->lock);
311 idr_preload_end();
312 }
313
314 BUG_ON(ret == -ENOSPC);
315 return ret < 0 ? ret : 0;
316 }
317
insert_handle(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)318 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
319 void *handle, u32 id)
320 {
321 return _insert_handle(rhp, idr, handle, id, 1);
322 }
323
insert_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,void * handle,u32 id)324 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
325 void *handle, u32 id)
326 {
327 return _insert_handle(rhp, idr, handle, id, 0);
328 }
329
_remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id,int lock)330 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
331 u32 id, int lock)
332 {
333 if (lock)
334 spin_lock_irq(&rhp->lock);
335 idr_remove(idr, id);
336 if (lock)
337 spin_unlock_irq(&rhp->lock);
338 }
339
remove_handle(struct c4iw_dev * rhp,struct idr * idr,u32 id)340 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
341 {
342 _remove_handle(rhp, idr, id, 1);
343 }
344
remove_handle_nolock(struct c4iw_dev * rhp,struct idr * idr,u32 id)345 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
346 struct idr *idr, u32 id)
347 {
348 _remove_handle(rhp, idr, id, 0);
349 }
350
351 extern uint c4iw_max_read_depth;
352
cur_max_read_depth(struct c4iw_dev * dev)353 static inline int cur_max_read_depth(struct c4iw_dev *dev)
354 {
355 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
356 }
357
358 struct c4iw_pd {
359 struct ib_pd ibpd;
360 u32 pdid;
361 struct c4iw_dev *rhp;
362 };
363
to_c4iw_pd(struct ib_pd * ibpd)364 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
365 {
366 return container_of(ibpd, struct c4iw_pd, ibpd);
367 }
368
369 struct tpt_attributes {
370 u64 len;
371 u64 va_fbo;
372 enum fw_ri_mem_perms perms;
373 u32 stag;
374 u32 pdid;
375 u32 qpid;
376 u32 pbl_addr;
377 u32 pbl_size;
378 u32 state:1;
379 u32 type:2;
380 u32 rsvd:1;
381 u32 remote_invaliate_disable:1;
382 u32 zbva:1;
383 u32 mw_bind_enable:1;
384 u32 page_size:5;
385 };
386
387 struct c4iw_mr {
388 struct ib_mr ibmr;
389 struct ib_umem *umem;
390 struct c4iw_dev *rhp;
391 struct sk_buff *dereg_skb;
392 u64 kva;
393 struct tpt_attributes attr;
394 u64 *mpl;
395 dma_addr_t mpl_addr;
396 u32 max_mpl_len;
397 u32 mpl_len;
398 };
399
to_c4iw_mr(struct ib_mr * ibmr)400 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
401 {
402 return container_of(ibmr, struct c4iw_mr, ibmr);
403 }
404
405 struct c4iw_mw {
406 struct ib_mw ibmw;
407 struct c4iw_dev *rhp;
408 struct sk_buff *dereg_skb;
409 u64 kva;
410 struct tpt_attributes attr;
411 };
412
to_c4iw_mw(struct ib_mw * ibmw)413 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
414 {
415 return container_of(ibmw, struct c4iw_mw, ibmw);
416 }
417
418 struct c4iw_cq {
419 struct ib_cq ibcq;
420 struct c4iw_dev *rhp;
421 struct sk_buff *destroy_skb;
422 struct t4_cq cq;
423 spinlock_t lock;
424 spinlock_t comp_handler_lock;
425 atomic_t refcnt;
426 wait_queue_head_t wait;
427 };
428
to_c4iw_cq(struct ib_cq * ibcq)429 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
430 {
431 return container_of(ibcq, struct c4iw_cq, ibcq);
432 }
433
434 struct c4iw_mpa_attributes {
435 u8 initiator;
436 u8 recv_marker_enabled;
437 u8 xmit_marker_enabled;
438 u8 crc_enabled;
439 u8 enhanced_rdma_conn;
440 u8 version;
441 u8 p2p_type;
442 };
443
444 struct c4iw_qp_attributes {
445 u32 scq;
446 u32 rcq;
447 u32 sq_num_entries;
448 u32 rq_num_entries;
449 u32 sq_max_sges;
450 u32 sq_max_sges_rdma_write;
451 u32 rq_max_sges;
452 u32 state;
453 u8 enable_rdma_read;
454 u8 enable_rdma_write;
455 u8 enable_bind;
456 u8 enable_mmid0_fastreg;
457 u32 max_ord;
458 u32 max_ird;
459 u32 pd;
460 u32 next_state;
461 char terminate_buffer[52];
462 u32 terminate_msg_len;
463 u8 is_terminate_local;
464 struct c4iw_mpa_attributes mpa_attr;
465 struct c4iw_ep *llp_stream_handle;
466 u8 layer_etype;
467 u8 ecode;
468 u16 sq_db_inc;
469 u16 rq_db_inc;
470 u8 send_term;
471 };
472
473 struct c4iw_qp {
474 struct ib_qp ibqp;
475 struct list_head db_fc_entry;
476 struct c4iw_dev *rhp;
477 struct c4iw_ep *ep;
478 struct c4iw_qp_attributes attr;
479 struct t4_wq wq;
480 spinlock_t lock;
481 struct mutex mutex;
482 struct kref kref;
483 wait_queue_head_t wait;
484 struct timer_list timer;
485 int sq_sig_all;
486 struct completion rq_drained;
487 struct completion sq_drained;
488 struct work_struct free_work;
489 struct c4iw_ucontext *ucontext;
490 };
491
to_c4iw_qp(struct ib_qp * ibqp)492 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
493 {
494 return container_of(ibqp, struct c4iw_qp, ibqp);
495 }
496
497 struct c4iw_ucontext {
498 struct ib_ucontext ibucontext;
499 struct c4iw_dev_ucontext uctx;
500 u32 key;
501 spinlock_t mmap_lock;
502 struct list_head mmaps;
503 struct kref kref;
504 };
505
to_c4iw_ucontext(struct ib_ucontext * c)506 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
507 {
508 return container_of(c, struct c4iw_ucontext, ibucontext);
509 }
510
511 void _c4iw_free_ucontext(struct kref *kref);
512
c4iw_put_ucontext(struct c4iw_ucontext * ucontext)513 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
514 {
515 kref_put(&ucontext->kref, _c4iw_free_ucontext);
516 }
517
c4iw_get_ucontext(struct c4iw_ucontext * ucontext)518 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
519 {
520 kref_get(&ucontext->kref);
521 }
522
523 struct c4iw_mm_entry {
524 struct list_head entry;
525 u64 addr;
526 u32 key;
527 unsigned len;
528 };
529
remove_mmap(struct c4iw_ucontext * ucontext,u32 key,unsigned len)530 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
531 u32 key, unsigned len)
532 {
533 struct list_head *pos, *nxt;
534 struct c4iw_mm_entry *mm;
535
536 spin_lock(&ucontext->mmap_lock);
537 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
538
539 mm = list_entry(pos, struct c4iw_mm_entry, entry);
540 if (mm->key == key && mm->len == len) {
541 list_del_init(&mm->entry);
542 spin_unlock(&ucontext->mmap_lock);
543 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
544 key, (unsigned long long) mm->addr, mm->len);
545 return mm;
546 }
547 }
548 spin_unlock(&ucontext->mmap_lock);
549 return NULL;
550 }
551
insert_mmap(struct c4iw_ucontext * ucontext,struct c4iw_mm_entry * mm)552 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
553 struct c4iw_mm_entry *mm)
554 {
555 spin_lock(&ucontext->mmap_lock);
556 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
557 mm->key, (unsigned long long) mm->addr, mm->len);
558 list_add_tail(&mm->entry, &ucontext->mmaps);
559 spin_unlock(&ucontext->mmap_lock);
560 }
561
562 enum c4iw_qp_attr_mask {
563 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
564 C4IW_QP_ATTR_SQ_DB = 1<<1,
565 C4IW_QP_ATTR_RQ_DB = 1<<2,
566 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
567 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
568 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
569 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
570 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
571 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
572 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
573 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
574 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
575 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
576 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
577 C4IW_QP_ATTR_MAX_ORD |
578 C4IW_QP_ATTR_MAX_IRD |
579 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
580 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
581 C4IW_QP_ATTR_MPA_ATTR |
582 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
583 };
584
585 int c4iw_modify_qp(struct c4iw_dev *rhp,
586 struct c4iw_qp *qhp,
587 enum c4iw_qp_attr_mask mask,
588 struct c4iw_qp_attributes *attrs,
589 int internal);
590
591 enum c4iw_qp_state {
592 C4IW_QP_STATE_IDLE,
593 C4IW_QP_STATE_RTS,
594 C4IW_QP_STATE_ERROR,
595 C4IW_QP_STATE_TERMINATE,
596 C4IW_QP_STATE_CLOSING,
597 C4IW_QP_STATE_TOT
598 };
599
c4iw_convert_state(enum ib_qp_state ib_state)600 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
601 {
602 switch (ib_state) {
603 case IB_QPS_RESET:
604 case IB_QPS_INIT:
605 return C4IW_QP_STATE_IDLE;
606 case IB_QPS_RTS:
607 return C4IW_QP_STATE_RTS;
608 case IB_QPS_SQD:
609 return C4IW_QP_STATE_CLOSING;
610 case IB_QPS_SQE:
611 return C4IW_QP_STATE_TERMINATE;
612 case IB_QPS_ERR:
613 return C4IW_QP_STATE_ERROR;
614 default:
615 return -1;
616 }
617 }
618
to_ib_qp_state(int c4iw_qp_state)619 static inline int to_ib_qp_state(int c4iw_qp_state)
620 {
621 switch (c4iw_qp_state) {
622 case C4IW_QP_STATE_IDLE:
623 return IB_QPS_INIT;
624 case C4IW_QP_STATE_RTS:
625 return IB_QPS_RTS;
626 case C4IW_QP_STATE_CLOSING:
627 return IB_QPS_SQD;
628 case C4IW_QP_STATE_TERMINATE:
629 return IB_QPS_SQE;
630 case C4IW_QP_STATE_ERROR:
631 return IB_QPS_ERR;
632 }
633 return IB_QPS_ERR;
634 }
635
c4iw_ib_to_tpt_access(int a)636 static inline u32 c4iw_ib_to_tpt_access(int a)
637 {
638 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
639 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
640 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
641 FW_RI_MEM_ACCESS_LOCAL_READ;
642 }
643
c4iw_ib_to_tpt_bind_access(int acc)644 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
645 {
646 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
647 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
648 }
649
650 enum c4iw_mmid_state {
651 C4IW_STAG_STATE_VALID,
652 C4IW_STAG_STATE_INVALID
653 };
654
655 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
656
657 #define MPA_KEY_REQ "MPA ID Req Frame"
658 #define MPA_KEY_REP "MPA ID Rep Frame"
659
660 #define MPA_MAX_PRIVATE_DATA 256
661 #define MPA_ENHANCED_RDMA_CONN 0x10
662 #define MPA_REJECT 0x20
663 #define MPA_CRC 0x40
664 #define MPA_MARKERS 0x80
665 #define MPA_FLAGS_MASK 0xE0
666
667 #define MPA_V2_PEER2PEER_MODEL 0x8000
668 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
669 #define MPA_V2_RDMA_WRITE_RTR 0x8000
670 #define MPA_V2_RDMA_READ_RTR 0x4000
671 #define MPA_V2_IRD_ORD_MASK 0x3FFF
672
673 #define c4iw_put_ep(ep) { \
674 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
675 ep, atomic_read(&((ep)->kref.refcount))); \
676 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
677 kref_put(&((ep)->kref), _c4iw_free_ep); \
678 }
679
680 #define c4iw_get_ep(ep) { \
681 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
682 ep, atomic_read(&((ep)->kref.refcount))); \
683 kref_get(&((ep)->kref)); \
684 }
685 void _c4iw_free_ep(struct kref *kref);
686
687 struct mpa_message {
688 u8 key[16];
689 u8 flags;
690 u8 revision;
691 __be16 private_data_size;
692 u8 private_data[0];
693 };
694
695 struct mpa_v2_conn_params {
696 __be16 ird;
697 __be16 ord;
698 };
699
700 struct terminate_message {
701 u8 layer_etype;
702 u8 ecode;
703 __be16 hdrct_rsvd;
704 u8 len_hdrs[0];
705 };
706
707 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
708
709 enum c4iw_layers_types {
710 LAYER_RDMAP = 0x00,
711 LAYER_DDP = 0x10,
712 LAYER_MPA = 0x20,
713 RDMAP_LOCAL_CATA = 0x00,
714 RDMAP_REMOTE_PROT = 0x01,
715 RDMAP_REMOTE_OP = 0x02,
716 DDP_LOCAL_CATA = 0x00,
717 DDP_TAGGED_ERR = 0x01,
718 DDP_UNTAGGED_ERR = 0x02,
719 DDP_LLP = 0x03
720 };
721
722 enum c4iw_rdma_ecodes {
723 RDMAP_INV_STAG = 0x00,
724 RDMAP_BASE_BOUNDS = 0x01,
725 RDMAP_ACC_VIOL = 0x02,
726 RDMAP_STAG_NOT_ASSOC = 0x03,
727 RDMAP_TO_WRAP = 0x04,
728 RDMAP_INV_VERS = 0x05,
729 RDMAP_INV_OPCODE = 0x06,
730 RDMAP_STREAM_CATA = 0x07,
731 RDMAP_GLOBAL_CATA = 0x08,
732 RDMAP_CANT_INV_STAG = 0x09,
733 RDMAP_UNSPECIFIED = 0xff
734 };
735
736 enum c4iw_ddp_ecodes {
737 DDPT_INV_STAG = 0x00,
738 DDPT_BASE_BOUNDS = 0x01,
739 DDPT_STAG_NOT_ASSOC = 0x02,
740 DDPT_TO_WRAP = 0x03,
741 DDPT_INV_VERS = 0x04,
742 DDPU_INV_QN = 0x01,
743 DDPU_INV_MSN_NOBUF = 0x02,
744 DDPU_INV_MSN_RANGE = 0x03,
745 DDPU_INV_MO = 0x04,
746 DDPU_MSG_TOOBIG = 0x05,
747 DDPU_INV_VERS = 0x06
748 };
749
750 enum c4iw_mpa_ecodes {
751 MPA_CRC_ERR = 0x02,
752 MPA_MARKER_ERR = 0x03,
753 MPA_LOCAL_CATA = 0x05,
754 MPA_INSUFF_IRD = 0x06,
755 MPA_NOMATCH_RTR = 0x07,
756 };
757
758 enum c4iw_ep_state {
759 IDLE = 0,
760 LISTEN,
761 CONNECTING,
762 MPA_REQ_WAIT,
763 MPA_REQ_SENT,
764 MPA_REQ_RCVD,
765 MPA_REP_SENT,
766 FPDU_MODE,
767 ABORTING,
768 CLOSING,
769 MORIBUND,
770 DEAD,
771 };
772
773 enum c4iw_ep_flags {
774 PEER_ABORT_IN_PROGRESS = 0,
775 ABORT_REQ_IN_PROGRESS = 1,
776 RELEASE_RESOURCES = 2,
777 CLOSE_SENT = 3,
778 TIMEOUT = 4,
779 QP_REFERENCED = 5,
780 STOP_MPA_TIMER = 7,
781 };
782
783 enum c4iw_ep_history {
784 ACT_OPEN_REQ = 0,
785 ACT_OFLD_CONN = 1,
786 ACT_OPEN_RPL = 2,
787 ACT_ESTAB = 3,
788 PASS_ACCEPT_REQ = 4,
789 PASS_ESTAB = 5,
790 ABORT_UPCALL = 6,
791 ESTAB_UPCALL = 7,
792 CLOSE_UPCALL = 8,
793 ULP_ACCEPT = 9,
794 ULP_REJECT = 10,
795 TIMEDOUT = 11,
796 PEER_ABORT = 12,
797 PEER_CLOSE = 13,
798 CONNREQ_UPCALL = 14,
799 ABORT_CONN = 15,
800 DISCONN_UPCALL = 16,
801 EP_DISC_CLOSE = 17,
802 EP_DISC_ABORT = 18,
803 CONN_RPL_UPCALL = 19,
804 ACT_RETRY_NOMEM = 20,
805 ACT_RETRY_INUSE = 21,
806 CLOSE_CON_RPL = 22,
807 EP_DISC_FAIL = 24,
808 QP_REFED = 25,
809 QP_DEREFED = 26,
810 CM_ID_REFED = 27,
811 CM_ID_DEREFED = 28,
812 };
813
814 enum conn_pre_alloc_buffers {
815 CN_ABORT_REQ_BUF,
816 CN_ABORT_RPL_BUF,
817 CN_CLOSE_CON_REQ_BUF,
818 CN_DESTROY_BUF,
819 CN_FLOWC_BUF,
820 CN_MAX_CON_BUF
821 };
822
823 #define FLOWC_LEN 80
824 union cpl_wr_size {
825 struct cpl_abort_req abrt_req;
826 struct cpl_abort_rpl abrt_rpl;
827 struct fw_ri_wr ri_req;
828 struct cpl_close_con_req close_req;
829 char flowc_buf[FLOWC_LEN];
830 };
831
832 struct c4iw_ep_common {
833 struct iw_cm_id *cm_id;
834 struct c4iw_qp *qp;
835 struct c4iw_dev *dev;
836 struct sk_buff_head ep_skb_list;
837 enum c4iw_ep_state state;
838 struct kref kref;
839 struct mutex mutex;
840 struct sockaddr_storage local_addr;
841 struct sockaddr_storage remote_addr;
842 struct c4iw_wr_wait wr_wait;
843 unsigned long flags;
844 unsigned long history;
845 };
846
847 struct c4iw_listen_ep {
848 struct c4iw_ep_common com;
849 unsigned int stid;
850 int backlog;
851 };
852
853 struct c4iw_ep_stats {
854 unsigned connect_neg_adv;
855 unsigned abort_neg_adv;
856 };
857
858 struct c4iw_ep {
859 struct c4iw_ep_common com;
860 struct c4iw_ep *parent_ep;
861 struct timer_list timer;
862 struct list_head entry;
863 unsigned int atid;
864 u32 hwtid;
865 u32 snd_seq;
866 u32 rcv_seq;
867 struct l2t_entry *l2t;
868 struct dst_entry *dst;
869 struct sk_buff *mpa_skb;
870 struct c4iw_mpa_attributes mpa_attr;
871 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
872 unsigned int mpa_pkt_len;
873 u32 ird;
874 u32 ord;
875 u32 smac_idx;
876 u32 tx_chan;
877 u32 mtu;
878 u16 mss;
879 u16 emss;
880 u16 plen;
881 u16 rss_qid;
882 u16 txq_idx;
883 u16 ctrlq_idx;
884 u8 tos;
885 u8 retry_with_mpa_v1;
886 u8 tried_with_mpa_v1;
887 unsigned int retry_count;
888 int snd_win;
889 int rcv_win;
890 struct c4iw_ep_stats stats;
891 };
892
to_ep(struct iw_cm_id * cm_id)893 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
894 {
895 return cm_id->provider_data;
896 }
897
to_listen_ep(struct iw_cm_id * cm_id)898 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
899 {
900 return cm_id->provider_data;
901 }
902
ocqp_supported(const struct cxgb4_lld_info * infop)903 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
904 {
905 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
906 return infop->vr->ocq.size > 0;
907 #else
908 return 0;
909 #endif
910 }
911
912 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
913 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
914 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
915 u32 reserved, u32 flags);
916 void c4iw_id_table_free(struct c4iw_id_table *alloc);
917
918 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
919
920 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
921 struct l2t_entry *l2t);
922 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
923 struct c4iw_dev_ucontext *uctx);
924 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
925 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
926 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
927 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
928 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
929 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
930 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
931 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
932 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
933 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
934 void c4iw_destroy_resource(struct c4iw_resource *rscp);
935 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
936 int c4iw_register_device(struct c4iw_dev *dev);
937 void c4iw_unregister_device(struct c4iw_dev *dev);
938 int __init c4iw_cm_init(void);
939 void c4iw_cm_term(void);
940 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
941 struct c4iw_dev_ucontext *uctx);
942 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
943 struct c4iw_dev_ucontext *uctx);
944 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
945 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
946 struct ib_send_wr **bad_wr);
947 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
948 struct ib_recv_wr **bad_wr);
949 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
950 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
951 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
952 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
953 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
954 void c4iw_qp_add_ref(struct ib_qp *qp);
955 void c4iw_qp_rem_ref(struct ib_qp *qp);
956 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
957 enum ib_mr_type mr_type,
958 u32 max_num_sg);
959 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
960 unsigned int *sg_offset);
961 int c4iw_dealloc_mw(struct ib_mw *mw);
962 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
963 struct ib_udata *udata);
964 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
965 u64 length, u64 virt, int acc,
966 struct ib_udata *udata);
967 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
968 int c4iw_dereg_mr(struct ib_mr *ib_mr);
969 int c4iw_destroy_cq(struct ib_cq *ib_cq);
970 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
971 const struct ib_cq_init_attr *attr,
972 struct ib_ucontext *ib_context,
973 struct ib_udata *udata);
974 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
975 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
976 int c4iw_destroy_qp(struct ib_qp *ib_qp);
977 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
978 struct ib_qp_init_attr *attrs,
979 struct ib_udata *udata);
980 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
981 int attr_mask, struct ib_udata *udata);
982 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
983 int attr_mask, struct ib_qp_init_attr *init_attr);
984 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
985 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
986 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
987 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
988 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
989 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
990 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
991 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
992 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
993 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
994 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
995 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
996 int c4iw_flush_sq(struct c4iw_qp *qhp);
997 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
998 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
999 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1000 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1001 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1002 struct c4iw_dev_ucontext *uctx);
1003 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1004 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1005 struct c4iw_dev_ucontext *uctx);
1006 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1007
1008 extern struct cxgb4_client t4c_client;
1009 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1010 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1011 enum cxgb4_bar2_qtype qtype,
1012 unsigned int *pbar2_qid, u64 *pbar2_pa);
1013 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1014 extern int c4iw_wr_log;
1015 extern int db_fc_threshold;
1016 extern int db_coalescing_threshold;
1017 extern int use_dsgl;
1018 void c4iw_drain_rq(struct ib_qp *qp);
1019 void c4iw_drain_sq(struct ib_qp *qp);
1020 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
1021
1022 #endif
1023