1 /*
2 * Based on arch/arm/include/asm/barrier.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #ifndef __ASM_BARRIER_H
19 #define __ASM_BARRIER_H
20
21 #ifndef __ASSEMBLY__
22
23 #define __nops(n) ".rept " #n "\nnop\n.endr\n"
24 #define nops(n) asm volatile(__nops(n))
25
26 #define sev() asm volatile("sev" : : : "memory")
27 #define wfe() asm volatile("wfe" : : : "memory")
28 #define wfi() asm volatile("wfi" : : : "memory")
29
30 #define isb() asm volatile("isb" : : : "memory")
31 #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
32 #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
33
34 #define csdb() asm volatile("hint #20" : : : "memory")
35
36 #define mb() dsb(sy)
37 #define rmb() dsb(ld)
38 #define wmb() dsb(st)
39
40 #define dma_rmb() dmb(oshld)
41 #define dma_wmb() dmb(oshst)
42
43 /*
44 * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz
45 * and 0 otherwise.
46 */
47 #define array_index_mask_nospec array_index_mask_nospec
array_index_mask_nospec(unsigned long idx,unsigned long sz)48 static inline unsigned long array_index_mask_nospec(unsigned long idx,
49 unsigned long sz)
50 {
51 unsigned long mask;
52
53 asm volatile(
54 " cmp %1, %2\n"
55 " sbc %0, xzr, xzr\n"
56 : "=r" (mask)
57 : "r" (idx), "Ir" (sz)
58 : "cc");
59
60 csdb();
61 return mask;
62 }
63
64 #define __smp_mb() dmb(ish)
65 #define __smp_rmb() dmb(ishld)
66 #define __smp_wmb() dmb(ishst)
67
68 #define __smp_store_release(p, v) \
69 do { \
70 union { typeof(*p) __val; char __c[1]; } __u = \
71 { .__val = (__force typeof(*p)) (v) }; \
72 compiletime_assert_atomic_type(*p); \
73 switch (sizeof(*p)) { \
74 case 1: \
75 asm volatile ("stlrb %w1, %0" \
76 : "=Q" (*p) \
77 : "r" (*(__u8 *)__u.__c) \
78 : "memory"); \
79 break; \
80 case 2: \
81 asm volatile ("stlrh %w1, %0" \
82 : "=Q" (*p) \
83 : "r" (*(__u16 *)__u.__c) \
84 : "memory"); \
85 break; \
86 case 4: \
87 asm volatile ("stlr %w1, %0" \
88 : "=Q" (*p) \
89 : "r" (*(__u32 *)__u.__c) \
90 : "memory"); \
91 break; \
92 case 8: \
93 asm volatile ("stlr %1, %0" \
94 : "=Q" (*p) \
95 : "r" (*(__u64 *)__u.__c) \
96 : "memory"); \
97 break; \
98 } \
99 } while (0)
100
101 #define __smp_load_acquire(p) \
102 ({ \
103 union { typeof(*p) __val; char __c[1]; } __u; \
104 compiletime_assert_atomic_type(*p); \
105 switch (sizeof(*p)) { \
106 case 1: \
107 asm volatile ("ldarb %w0, %1" \
108 : "=r" (*(__u8 *)__u.__c) \
109 : "Q" (*p) : "memory"); \
110 break; \
111 case 2: \
112 asm volatile ("ldarh %w0, %1" \
113 : "=r" (*(__u16 *)__u.__c) \
114 : "Q" (*p) : "memory"); \
115 break; \
116 case 4: \
117 asm volatile ("ldar %w0, %1" \
118 : "=r" (*(__u32 *)__u.__c) \
119 : "Q" (*p) : "memory"); \
120 break; \
121 case 8: \
122 asm volatile ("ldar %0, %1" \
123 : "=r" (*(__u64 *)__u.__c) \
124 : "Q" (*p) : "memory"); \
125 break; \
126 } \
127 __u.__val; \
128 })
129
130 #define smp_cond_load_acquire(ptr, cond_expr) \
131 ({ \
132 typeof(ptr) __PTR = (ptr); \
133 typeof(*ptr) VAL; \
134 for (;;) { \
135 VAL = smp_load_acquire(__PTR); \
136 if (cond_expr) \
137 break; \
138 __cmpwait_relaxed(__PTR, VAL); \
139 } \
140 VAL; \
141 })
142
143 #include <asm-generic/barrier.h>
144
145 #endif /* __ASSEMBLY__ */
146
147 #endif /* __ASM_BARRIER_H */
148