1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/kprobes.h>
13 #include <linux/kgdb.h>
14 #include <linux/smp.h>
15 #include <linux/io.h>
16 #include <linux/syscore_ops.h>
17
18 #include <asm/stackprotector.h>
19 #include <asm/perf_event.h>
20 #include <asm/mmu_context.h>
21 #include <asm/archrandom.h>
22 #include <asm/hypervisor.h>
23 #include <asm/processor.h>
24 #include <asm/tlbflush.h>
25 #include <asm/debugreg.h>
26 #include <asm/sections.h>
27 #include <asm/vsyscall.h>
28 #include <linux/topology.h>
29 #include <linux/cpumask.h>
30 #include <asm/pgtable.h>
31 #include <linux/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/setup.h>
34 #include <asm/apic.h>
35 #include <asm/desc.h>
36 #include <asm/fpu/internal.h>
37 #include <asm/mtrr.h>
38 #include <linux/numa.h>
39 #include <asm/asm.h>
40 #include <asm/bugs.h>
41 #include <asm/cpu.h>
42 #include <asm/mce.h>
43 #include <asm/msr.h>
44 #include <asm/pat.h>
45 #include <asm/microcode.h>
46 #include <asm/microcode_intel.h>
47 #include <asm/intel-family.h>
48 #include <asm/cpu_device_id.h>
49
50 #ifdef CONFIG_X86_LOCAL_APIC
51 #include <asm/uv/uv.h>
52 #endif
53
54 #include "cpu.h"
55
56 /* all of these masks are initialized in setup_cpu_local_masks() */
57 cpumask_var_t cpu_initialized_mask;
58 cpumask_var_t cpu_callout_mask;
59 cpumask_var_t cpu_callin_mask;
60
61 /* representing cpus for which sibling maps can be computed */
62 cpumask_var_t cpu_sibling_setup_mask;
63
64 /* correctly size the local cpu masks */
setup_cpu_local_masks(void)65 void __init setup_cpu_local_masks(void)
66 {
67 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
68 alloc_bootmem_cpumask_var(&cpu_callin_mask);
69 alloc_bootmem_cpumask_var(&cpu_callout_mask);
70 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
71 }
72
default_init(struct cpuinfo_x86 * c)73 static void default_init(struct cpuinfo_x86 *c)
74 {
75 #ifdef CONFIG_X86_64
76 cpu_detect_cache_sizes(c);
77 #else
78 /* Not much we can do here... */
79 /* Check if at least it has cpuid */
80 if (c->cpuid_level == -1) {
81 /* No cpuid. It must be an ancient CPU */
82 if (c->x86 == 4)
83 strcpy(c->x86_model_id, "486");
84 else if (c->x86 == 3)
85 strcpy(c->x86_model_id, "386");
86 }
87 #endif
88 }
89
90 static const struct cpu_dev default_cpu = {
91 .c_init = default_init,
92 .c_vendor = "Unknown",
93 .c_x86_vendor = X86_VENDOR_UNKNOWN,
94 };
95
96 static const struct cpu_dev *this_cpu = &default_cpu;
97
98 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(struct gdt_page, gdt_page) = { .gdt = {
99 #ifdef CONFIG_X86_64
100 /*
101 * We need valid kernel segments for data and code in long mode too
102 * IRET will check the segment types kkeil 2000/10/28
103 * Also sysret mandates a special GDT layout
104 *
105 * TLS descriptors are currently at a different place compared to i386.
106 * Hopefully nobody expects them at a fixed place (Wine?)
107 */
108 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
110 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
112 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
113 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
114 #else
115 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
116 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
118 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
119 /*
120 * Segments used for calling PnP BIOS have byte granularity.
121 * They code segments and data segments have fixed 64k limits,
122 * the transfer segment sizes are set at run time.
123 */
124 /* 32-bit code */
125 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
126 /* 16-bit code */
127 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
128 /* 16-bit data */
129 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
130 /* 16-bit data */
131 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
132 /* 16-bit data */
133 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
134 /*
135 * The APM segments have byte granularity and their bases
136 * are set at run time. All have 64k limits.
137 */
138 /* 32-bit code */
139 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
140 /* 16-bit code */
141 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
142 /* data */
143 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
144
145 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
146 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
147 GDT_STACK_CANARY_INIT
148 #endif
149 } };
150 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
151
x86_mpx_setup(char * s)152 static int __init x86_mpx_setup(char *s)
153 {
154 /* require an exact match without trailing characters */
155 if (strlen(s))
156 return 0;
157
158 /* do not emit a message if the feature is not present */
159 if (!boot_cpu_has(X86_FEATURE_MPX))
160 return 1;
161
162 setup_clear_cpu_cap(X86_FEATURE_MPX);
163 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
164 return 1;
165 }
166 __setup("nompx", x86_mpx_setup);
167
168 #ifdef CONFIG_X86_64
x86_pcid_setup(char * s)169 static int __init x86_pcid_setup(char *s)
170 {
171 /* require an exact match without trailing characters */
172 if (strlen(s))
173 return 0;
174
175 /* do not emit a message if the feature is not present */
176 if (!boot_cpu_has(X86_FEATURE_PCID))
177 return 1;
178
179 setup_clear_cpu_cap(X86_FEATURE_PCID);
180 pr_info("nopcid: PCID feature disabled\n");
181 return 1;
182 }
183 __setup("nopcid", x86_pcid_setup);
184 #endif
185
x86_noinvpcid_setup(char * s)186 static int __init x86_noinvpcid_setup(char *s)
187 {
188 /* noinvpcid doesn't accept parameters */
189 if (s)
190 return -EINVAL;
191
192 /* do not emit a message if the feature is not present */
193 if (!boot_cpu_has(X86_FEATURE_INVPCID))
194 return 0;
195
196 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
197 pr_info("noinvpcid: INVPCID feature disabled\n");
198 return 0;
199 }
200 early_param("noinvpcid", x86_noinvpcid_setup);
201
202 #ifdef CONFIG_X86_32
203 static int cachesize_override = -1;
204 static int disable_x86_serial_nr = 1;
205
cachesize_setup(char * str)206 static int __init cachesize_setup(char *str)
207 {
208 get_option(&str, &cachesize_override);
209 return 1;
210 }
211 __setup("cachesize=", cachesize_setup);
212
x86_sep_setup(char * s)213 static int __init x86_sep_setup(char *s)
214 {
215 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 return 1;
217 }
218 __setup("nosep", x86_sep_setup);
219
220 /* Standard macro to see if a specific flag is changeable */
flag_is_changeable_p(u32 flag)221 static inline int flag_is_changeable_p(u32 flag)
222 {
223 u32 f1, f2;
224
225 /*
226 * Cyrix and IDT cpus allow disabling of CPUID
227 * so the code below may return different results
228 * when it is executed before and after enabling
229 * the CPUID. Add "volatile" to not allow gcc to
230 * optimize the subsequent calls to this function.
231 */
232 asm volatile ("pushfl \n\t"
233 "pushfl \n\t"
234 "popl %0 \n\t"
235 "movl %0, %1 \n\t"
236 "xorl %2, %0 \n\t"
237 "pushl %0 \n\t"
238 "popfl \n\t"
239 "pushfl \n\t"
240 "popl %0 \n\t"
241 "popfl \n\t"
242
243 : "=&r" (f1), "=&r" (f2)
244 : "ir" (flag));
245
246 return ((f1^f2) & flag) != 0;
247 }
248
249 /* Probe for the CPUID instruction */
have_cpuid_p(void)250 int have_cpuid_p(void)
251 {
252 return flag_is_changeable_p(X86_EFLAGS_ID);
253 }
254
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)255 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256 {
257 unsigned long lo, hi;
258
259 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 return;
261
262 /* Disable processor serial number: */
263
264 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 lo |= 0x200000;
266 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267
268 pr_notice("CPU serial number disabled.\n");
269 clear_cpu_cap(c, X86_FEATURE_PN);
270
271 /* Disabling the serial number may affect the cpuid level */
272 c->cpuid_level = cpuid_eax(0);
273 }
274
x86_serial_nr_setup(char * s)275 static int __init x86_serial_nr_setup(char *s)
276 {
277 disable_x86_serial_nr = 0;
278 return 1;
279 }
280 __setup("serialnumber", x86_serial_nr_setup);
281 #else
flag_is_changeable_p(u32 flag)282 static inline int flag_is_changeable_p(u32 flag)
283 {
284 return 1;
285 }
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)286 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
287 {
288 }
289 #endif
290
setup_disable_smep(char * arg)291 static __init int setup_disable_smep(char *arg)
292 {
293 setup_clear_cpu_cap(X86_FEATURE_SMEP);
294 /* Check for things that depend on SMEP being enabled: */
295 check_mpx_erratum(&boot_cpu_data);
296 return 1;
297 }
298 __setup("nosmep", setup_disable_smep);
299
setup_smep(struct cpuinfo_x86 * c)300 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
301 {
302 if (cpu_has(c, X86_FEATURE_SMEP))
303 cr4_set_bits(X86_CR4_SMEP);
304 }
305
setup_disable_smap(char * arg)306 static __init int setup_disable_smap(char *arg)
307 {
308 setup_clear_cpu_cap(X86_FEATURE_SMAP);
309 return 1;
310 }
311 __setup("nosmap", setup_disable_smap);
312
setup_smap(struct cpuinfo_x86 * c)313 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
314 {
315 unsigned long eflags = native_save_fl();
316
317 /* This should have been cleared long ago */
318 BUG_ON(eflags & X86_EFLAGS_AC);
319
320 if (cpu_has(c, X86_FEATURE_SMAP)) {
321 #ifdef CONFIG_X86_SMAP
322 cr4_set_bits(X86_CR4_SMAP);
323 #else
324 cr4_clear_bits(X86_CR4_SMAP);
325 #endif
326 }
327 }
328
setup_pcid(struct cpuinfo_x86 * c)329 static void setup_pcid(struct cpuinfo_x86 *c)
330 {
331 if (cpu_has(c, X86_FEATURE_PCID)) {
332 if (cpu_has(c, X86_FEATURE_PGE) || kaiser_enabled) {
333 cr4_set_bits(X86_CR4_PCIDE);
334 /*
335 * INVPCID has two "groups" of types:
336 * 1/2: Invalidate an individual address
337 * 3/4: Invalidate all contexts
338 *
339 * 1/2 take a PCID, but 3/4 do not. So, 3/4
340 * ignore the PCID argument in the descriptor.
341 * But, we have to be careful not to call 1/2
342 * with an actual non-zero PCID in them before
343 * we do the above cr4_set_bits().
344 */
345 if (cpu_has(c, X86_FEATURE_INVPCID))
346 set_cpu_cap(c, X86_FEATURE_INVPCID_SINGLE);
347 } else {
348 /*
349 * flush_tlb_all(), as currently implemented, won't
350 * work if PCID is on but PGE is not. Since that
351 * combination doesn't exist on real hardware, there's
352 * no reason to try to fully support it, but it's
353 * polite to avoid corrupting data if we're on
354 * an improperly configured VM.
355 */
356 clear_cpu_cap(c, X86_FEATURE_PCID);
357 }
358 }
359 kaiser_setup_pcid();
360 }
361
362 /*
363 * Protection Keys are not available in 32-bit mode.
364 */
365 static bool pku_disabled;
366
setup_pku(struct cpuinfo_x86 * c)367 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
368 {
369 /* check the boot processor, plus compile options for PKU: */
370 if (!cpu_feature_enabled(X86_FEATURE_PKU))
371 return;
372 /* checks the actual processor's cpuid bits: */
373 if (!cpu_has(c, X86_FEATURE_PKU))
374 return;
375 if (pku_disabled)
376 return;
377
378 cr4_set_bits(X86_CR4_PKE);
379 /*
380 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
381 * cpuid bit to be set. We need to ensure that we
382 * update that bit in this CPU's "cpu_info".
383 */
384 get_cpu_cap(c);
385 }
386
387 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
setup_disable_pku(char * arg)388 static __init int setup_disable_pku(char *arg)
389 {
390 /*
391 * Do not clear the X86_FEATURE_PKU bit. All of the
392 * runtime checks are against OSPKE so clearing the
393 * bit does nothing.
394 *
395 * This way, we will see "pku" in cpuinfo, but not
396 * "ospke", which is exactly what we want. It shows
397 * that the CPU has PKU, but the OS has not enabled it.
398 * This happens to be exactly how a system would look
399 * if we disabled the config option.
400 */
401 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
402 pku_disabled = true;
403 return 1;
404 }
405 __setup("nopku", setup_disable_pku);
406 #endif /* CONFIG_X86_64 */
407
408 /*
409 * Some CPU features depend on higher CPUID levels, which may not always
410 * be available due to CPUID level capping or broken virtualization
411 * software. Add those features to this table to auto-disable them.
412 */
413 struct cpuid_dependent_feature {
414 u32 feature;
415 u32 level;
416 };
417
418 static const struct cpuid_dependent_feature
419 cpuid_dependent_features[] = {
420 { X86_FEATURE_MWAIT, 0x00000005 },
421 { X86_FEATURE_DCA, 0x00000009 },
422 { X86_FEATURE_XSAVE, 0x0000000d },
423 { 0, 0 }
424 };
425
filter_cpuid_features(struct cpuinfo_x86 * c,bool warn)426 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
427 {
428 const struct cpuid_dependent_feature *df;
429
430 for (df = cpuid_dependent_features; df->feature; df++) {
431
432 if (!cpu_has(c, df->feature))
433 continue;
434 /*
435 * Note: cpuid_level is set to -1 if unavailable, but
436 * extended_extended_level is set to 0 if unavailable
437 * and the legitimate extended levels are all negative
438 * when signed; hence the weird messing around with
439 * signs here...
440 */
441 if (!((s32)df->level < 0 ?
442 (u32)df->level > (u32)c->extended_cpuid_level :
443 (s32)df->level > (s32)c->cpuid_level))
444 continue;
445
446 clear_cpu_cap(c, df->feature);
447 if (!warn)
448 continue;
449
450 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
451 x86_cap_flag(df->feature), df->level);
452 }
453 }
454
455 /*
456 * Naming convention should be: <Name> [(<Codename>)]
457 * This table only is used unless init_<vendor>() below doesn't set it;
458 * in particular, if CPUID levels 0x80000002..4 are supported, this
459 * isn't used
460 */
461
462 /* Look up CPU names by table lookup. */
table_lookup_model(struct cpuinfo_x86 * c)463 static const char *table_lookup_model(struct cpuinfo_x86 *c)
464 {
465 #ifdef CONFIG_X86_32
466 const struct legacy_cpu_model_info *info;
467
468 if (c->x86_model >= 16)
469 return NULL; /* Range check */
470
471 if (!this_cpu)
472 return NULL;
473
474 info = this_cpu->legacy_models;
475
476 while (info->family) {
477 if (info->family == c->x86)
478 return info->model_names[c->x86_model];
479 info++;
480 }
481 #endif
482 return NULL; /* Not found */
483 }
484
485 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
486 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
487
load_percpu_segment(int cpu)488 void load_percpu_segment(int cpu)
489 {
490 #ifdef CONFIG_X86_32
491 loadsegment(fs, __KERNEL_PERCPU);
492 #else
493 __loadsegment_simple(gs, 0);
494 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
495 #endif
496 load_stack_canary_segment();
497 }
498
499 /*
500 * Current gdt points %fs at the "master" per-cpu area: after this,
501 * it's on the real one.
502 */
switch_to_new_gdt(int cpu)503 void switch_to_new_gdt(int cpu)
504 {
505 struct desc_ptr gdt_descr;
506
507 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
508 gdt_descr.size = GDT_SIZE - 1;
509 load_gdt(&gdt_descr);
510 /* Reload the per-cpu base */
511
512 load_percpu_segment(cpu);
513 }
514
515 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
516
get_model_name(struct cpuinfo_x86 * c)517 static void get_model_name(struct cpuinfo_x86 *c)
518 {
519 unsigned int *v;
520 char *p, *q, *s;
521
522 if (c->extended_cpuid_level < 0x80000004)
523 return;
524
525 v = (unsigned int *)c->x86_model_id;
526 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
527 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
528 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
529 c->x86_model_id[48] = 0;
530
531 /* Trim whitespace */
532 p = q = s = &c->x86_model_id[0];
533
534 while (*p == ' ')
535 p++;
536
537 while (*p) {
538 /* Note the last non-whitespace index */
539 if (!isspace(*p))
540 s = q;
541
542 *q++ = *p++;
543 }
544
545 *(s + 1) = '\0';
546 }
547
cpu_detect_cache_sizes(struct cpuinfo_x86 * c)548 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
549 {
550 unsigned int n, dummy, ebx, ecx, edx, l2size;
551
552 n = c->extended_cpuid_level;
553
554 if (n >= 0x80000005) {
555 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
556 c->x86_cache_size = (ecx>>24) + (edx>>24);
557 #ifdef CONFIG_X86_64
558 /* On K8 L1 TLB is inclusive, so don't count it */
559 c->x86_tlbsize = 0;
560 #endif
561 }
562
563 if (n < 0x80000006) /* Some chips just has a large L1. */
564 return;
565
566 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
567 l2size = ecx >> 16;
568
569 #ifdef CONFIG_X86_64
570 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
571 #else
572 /* do processor-specific cache resizing */
573 if (this_cpu->legacy_cache_size)
574 l2size = this_cpu->legacy_cache_size(c, l2size);
575
576 /* Allow user to override all this if necessary. */
577 if (cachesize_override != -1)
578 l2size = cachesize_override;
579
580 if (l2size == 0)
581 return; /* Again, no L2 cache is possible */
582 #endif
583
584 c->x86_cache_size = l2size;
585 }
586
587 u16 __read_mostly tlb_lli_4k[NR_INFO];
588 u16 __read_mostly tlb_lli_2m[NR_INFO];
589 u16 __read_mostly tlb_lli_4m[NR_INFO];
590 u16 __read_mostly tlb_lld_4k[NR_INFO];
591 u16 __read_mostly tlb_lld_2m[NR_INFO];
592 u16 __read_mostly tlb_lld_4m[NR_INFO];
593 u16 __read_mostly tlb_lld_1g[NR_INFO];
594
cpu_detect_tlb(struct cpuinfo_x86 * c)595 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
596 {
597 if (this_cpu->c_detect_tlb)
598 this_cpu->c_detect_tlb(c);
599
600 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
601 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
602 tlb_lli_4m[ENTRIES]);
603
604 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
605 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
606 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
607 }
608
detect_ht(struct cpuinfo_x86 * c)609 void detect_ht(struct cpuinfo_x86 *c)
610 {
611 #ifdef CONFIG_SMP
612 u32 eax, ebx, ecx, edx;
613 int index_msb, core_bits;
614 static bool printed;
615
616 if (!cpu_has(c, X86_FEATURE_HT))
617 return;
618
619 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
620 goto out;
621
622 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
623 return;
624
625 cpuid(1, &eax, &ebx, &ecx, &edx);
626
627 smp_num_siblings = (ebx & 0xff0000) >> 16;
628
629 if (smp_num_siblings == 1) {
630 pr_info_once("CPU0: Hyper-Threading is disabled\n");
631 goto out;
632 }
633
634 if (smp_num_siblings <= 1)
635 goto out;
636
637 index_msb = get_count_order(smp_num_siblings);
638 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
639
640 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
641
642 index_msb = get_count_order(smp_num_siblings);
643
644 core_bits = get_count_order(c->x86_max_cores);
645
646 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
647 ((1 << core_bits) - 1);
648
649 out:
650 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
651 pr_info("CPU: Physical Processor ID: %d\n",
652 c->phys_proc_id);
653 pr_info("CPU: Processor Core ID: %d\n",
654 c->cpu_core_id);
655 printed = 1;
656 }
657 #endif
658 }
659
get_cpu_vendor(struct cpuinfo_x86 * c)660 static void get_cpu_vendor(struct cpuinfo_x86 *c)
661 {
662 char *v = c->x86_vendor_id;
663 int i;
664
665 for (i = 0; i < X86_VENDOR_NUM; i++) {
666 if (!cpu_devs[i])
667 break;
668
669 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
670 (cpu_devs[i]->c_ident[1] &&
671 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
672
673 this_cpu = cpu_devs[i];
674 c->x86_vendor = this_cpu->c_x86_vendor;
675 return;
676 }
677 }
678
679 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
680 "CPU: Your system may be unstable.\n", v);
681
682 c->x86_vendor = X86_VENDOR_UNKNOWN;
683 this_cpu = &default_cpu;
684 }
685
cpu_detect(struct cpuinfo_x86 * c)686 void cpu_detect(struct cpuinfo_x86 *c)
687 {
688 /* Get vendor name */
689 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
690 (unsigned int *)&c->x86_vendor_id[0],
691 (unsigned int *)&c->x86_vendor_id[8],
692 (unsigned int *)&c->x86_vendor_id[4]);
693
694 c->x86 = 4;
695 /* Intel-defined flags: level 0x00000001 */
696 if (c->cpuid_level >= 0x00000001) {
697 u32 junk, tfms, cap0, misc;
698
699 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
700 c->x86 = x86_family(tfms);
701 c->x86_model = x86_model(tfms);
702 c->x86_stepping = x86_stepping(tfms);
703
704 if (cap0 & (1<<19)) {
705 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
706 c->x86_cache_alignment = c->x86_clflush_size;
707 }
708 }
709 }
710
apply_forced_caps(struct cpuinfo_x86 * c)711 static void apply_forced_caps(struct cpuinfo_x86 *c)
712 {
713 int i;
714
715 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
716 c->x86_capability[i] &= ~cpu_caps_cleared[i];
717 c->x86_capability[i] |= cpu_caps_set[i];
718 }
719 }
720
init_speculation_control(struct cpuinfo_x86 * c)721 static void init_speculation_control(struct cpuinfo_x86 *c)
722 {
723 /*
724 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
725 * and they also have a different bit for STIBP support. Also,
726 * a hypervisor might have set the individual AMD bits even on
727 * Intel CPUs, for finer-grained selection of what's available.
728 *
729 * We use the AMD bits in 0x8000_0008 EBX as the generic hardware
730 * features, which are visible in /proc/cpuinfo and used by the
731 * kernel. So set those accordingly from the Intel bits.
732 */
733 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
734 set_cpu_cap(c, X86_FEATURE_IBRS);
735 set_cpu_cap(c, X86_FEATURE_IBPB);
736 }
737 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
738 set_cpu_cap(c, X86_FEATURE_STIBP);
739 }
740
get_cpu_cap(struct cpuinfo_x86 * c)741 void get_cpu_cap(struct cpuinfo_x86 *c)
742 {
743 u32 eax, ebx, ecx, edx;
744
745 /* Intel-defined flags: level 0x00000001 */
746 if (c->cpuid_level >= 0x00000001) {
747 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
748
749 c->x86_capability[CPUID_1_ECX] = ecx;
750 c->x86_capability[CPUID_1_EDX] = edx;
751 }
752
753 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
754 if (c->cpuid_level >= 0x00000006)
755 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
756
757 /* Additional Intel-defined flags: level 0x00000007 */
758 if (c->cpuid_level >= 0x00000007) {
759 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
760 c->x86_capability[CPUID_7_0_EBX] = ebx;
761 c->x86_capability[CPUID_7_ECX] = ecx;
762 c->x86_capability[CPUID_7_EDX] = edx;
763 }
764
765 /* Extended state features: level 0x0000000d */
766 if (c->cpuid_level >= 0x0000000d) {
767 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
768
769 c->x86_capability[CPUID_D_1_EAX] = eax;
770 }
771
772 /* Additional Intel-defined flags: level 0x0000000F */
773 if (c->cpuid_level >= 0x0000000F) {
774
775 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
776 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
777 c->x86_capability[CPUID_F_0_EDX] = edx;
778
779 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
780 /* will be overridden if occupancy monitoring exists */
781 c->x86_cache_max_rmid = ebx;
782
783 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
784 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
785 c->x86_capability[CPUID_F_1_EDX] = edx;
786
787 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
788 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
789 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
790 c->x86_cache_max_rmid = ecx;
791 c->x86_cache_occ_scale = ebx;
792 }
793 } else {
794 c->x86_cache_max_rmid = -1;
795 c->x86_cache_occ_scale = -1;
796 }
797 }
798
799 /* AMD-defined flags: level 0x80000001 */
800 eax = cpuid_eax(0x80000000);
801 c->extended_cpuid_level = eax;
802
803 if ((eax & 0xffff0000) == 0x80000000) {
804 if (eax >= 0x80000001) {
805 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
806
807 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
808 c->x86_capability[CPUID_8000_0001_EDX] = edx;
809 }
810 }
811
812 if (c->extended_cpuid_level >= 0x80000007) {
813 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
814
815 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
816 c->x86_power = edx;
817 }
818
819 if (c->extended_cpuid_level >= 0x80000008) {
820 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
821
822 c->x86_virt_bits = (eax >> 8) & 0xff;
823 c->x86_phys_bits = eax & 0xff;
824 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
825 }
826 #ifdef CONFIG_X86_32
827 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
828 c->x86_phys_bits = 36;
829 #endif
830
831 if (c->extended_cpuid_level >= 0x8000000a)
832 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
833
834 init_scattered_cpuid_features(c);
835 init_speculation_control(c);
836 }
837
identify_cpu_without_cpuid(struct cpuinfo_x86 * c)838 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
839 {
840 #ifdef CONFIG_X86_32
841 int i;
842
843 /*
844 * First of all, decide if this is a 486 or higher
845 * It's a 486 if we can modify the AC flag
846 */
847 if (flag_is_changeable_p(X86_EFLAGS_AC))
848 c->x86 = 4;
849 else
850 c->x86 = 3;
851
852 for (i = 0; i < X86_VENDOR_NUM; i++)
853 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
854 c->x86_vendor_id[0] = 0;
855 cpu_devs[i]->c_identify(c);
856 if (c->x86_vendor_id[0]) {
857 get_cpu_vendor(c);
858 break;
859 }
860 }
861 #endif
862 }
863
864 static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
865 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY },
866 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY },
867 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY },
868 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY },
869 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY },
870 { X86_VENDOR_CENTAUR, 5 },
871 { X86_VENDOR_INTEL, 5 },
872 { X86_VENDOR_NSC, 5 },
873 { X86_VENDOR_ANY, 4 },
874 {}
875 };
876
877 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
878 { X86_VENDOR_AMD },
879 {}
880 };
881
cpu_vulnerable_to_meltdown(struct cpuinfo_x86 * c)882 static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c)
883 {
884 u64 ia32_cap = 0;
885
886 if (x86_match_cpu(cpu_no_meltdown))
887 return false;
888
889 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
890 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
891
892 /* Rogue Data Cache Load? No! */
893 if (ia32_cap & ARCH_CAP_RDCL_NO)
894 return false;
895
896 return true;
897 }
898
899 /*
900 * Do minimum CPU detection early.
901 * Fields really needed: vendor, cpuid_level, family, model, mask,
902 * cache alignment.
903 * The others are not touched to avoid unwanted side effects.
904 *
905 * WARNING: this function is only called on the BP. Don't add code here
906 * that is supposed to run on all CPUs.
907 */
early_identify_cpu(struct cpuinfo_x86 * c)908 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
909 {
910 #ifdef CONFIG_X86_64
911 c->x86_clflush_size = 64;
912 c->x86_phys_bits = 36;
913 c->x86_virt_bits = 48;
914 #else
915 c->x86_clflush_size = 32;
916 c->x86_phys_bits = 32;
917 c->x86_virt_bits = 32;
918 #endif
919 c->x86_cache_alignment = c->x86_clflush_size;
920
921 memset(&c->x86_capability, 0, sizeof c->x86_capability);
922 c->extended_cpuid_level = 0;
923
924 if (!have_cpuid_p())
925 identify_cpu_without_cpuid(c);
926
927 /* cyrix could have cpuid enabled via c_identify()*/
928 if (have_cpuid_p()) {
929 cpu_detect(c);
930 get_cpu_vendor(c);
931 get_cpu_cap(c);
932
933 if (this_cpu->c_early_init)
934 this_cpu->c_early_init(c);
935
936 c->cpu_index = 0;
937 filter_cpuid_features(c, false);
938
939 if (this_cpu->c_bsp_init)
940 this_cpu->c_bsp_init(c);
941 }
942
943 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
944
945 if (!x86_match_cpu(cpu_no_speculation)) {
946 if (cpu_vulnerable_to_meltdown(c))
947 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
948 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
949 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
950 }
951
952 fpu__init_system(c);
953
954 #ifdef CONFIG_X86_32
955 /*
956 * Regardless of whether PCID is enumerated, the SDM says
957 * that it can't be enabled in 32-bit mode.
958 */
959 setup_clear_cpu_cap(X86_FEATURE_PCID);
960 #endif
961 }
962
early_cpu_init(void)963 void __init early_cpu_init(void)
964 {
965 const struct cpu_dev *const *cdev;
966 int count = 0;
967
968 #ifdef CONFIG_PROCESSOR_SELECT
969 pr_info("KERNEL supported cpus:\n");
970 #endif
971
972 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
973 const struct cpu_dev *cpudev = *cdev;
974
975 if (count >= X86_VENDOR_NUM)
976 break;
977 cpu_devs[count] = cpudev;
978 count++;
979
980 #ifdef CONFIG_PROCESSOR_SELECT
981 {
982 unsigned int j;
983
984 for (j = 0; j < 2; j++) {
985 if (!cpudev->c_ident[j])
986 continue;
987 pr_info(" %s %s\n", cpudev->c_vendor,
988 cpudev->c_ident[j]);
989 }
990 }
991 #endif
992 }
993 early_identify_cpu(&boot_cpu_data);
994 }
995
996 /*
997 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
998 * unfortunately, that's not true in practice because of early VIA
999 * chips and (more importantly) broken virtualizers that are not easy
1000 * to detect. In the latter case it doesn't even *fail* reliably, so
1001 * probing for it doesn't even work. Disable it completely on 32-bit
1002 * unless we can find a reliable way to detect all the broken cases.
1003 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1004 */
detect_nopl(struct cpuinfo_x86 * c)1005 static void detect_nopl(struct cpuinfo_x86 *c)
1006 {
1007 #ifdef CONFIG_X86_32
1008 clear_cpu_cap(c, X86_FEATURE_NOPL);
1009 #else
1010 set_cpu_cap(c, X86_FEATURE_NOPL);
1011 #endif
1012 }
1013
detect_null_seg_behavior(struct cpuinfo_x86 * c)1014 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1015 {
1016 #ifdef CONFIG_X86_64
1017 /*
1018 * Empirically, writing zero to a segment selector on AMD does
1019 * not clear the base, whereas writing zero to a segment
1020 * selector on Intel does clear the base. Intel's behavior
1021 * allows slightly faster context switches in the common case
1022 * where GS is unused by the prev and next threads.
1023 *
1024 * Since neither vendor documents this anywhere that I can see,
1025 * detect it directly instead of hardcoding the choice by
1026 * vendor.
1027 *
1028 * I've designated AMD's behavior as the "bug" because it's
1029 * counterintuitive and less friendly.
1030 */
1031
1032 unsigned long old_base, tmp;
1033 rdmsrl(MSR_FS_BASE, old_base);
1034 wrmsrl(MSR_FS_BASE, 1);
1035 loadsegment(fs, 0);
1036 rdmsrl(MSR_FS_BASE, tmp);
1037 if (tmp != 0)
1038 set_cpu_bug(c, X86_BUG_NULL_SEG);
1039 wrmsrl(MSR_FS_BASE, old_base);
1040 #endif
1041 }
1042
generic_identify(struct cpuinfo_x86 * c)1043 static void generic_identify(struct cpuinfo_x86 *c)
1044 {
1045 c->extended_cpuid_level = 0;
1046
1047 if (!have_cpuid_p())
1048 identify_cpu_without_cpuid(c);
1049
1050 /* cyrix could have cpuid enabled via c_identify()*/
1051 if (!have_cpuid_p())
1052 return;
1053
1054 cpu_detect(c);
1055
1056 get_cpu_vendor(c);
1057
1058 get_cpu_cap(c);
1059
1060 if (c->cpuid_level >= 0x00000001) {
1061 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1062 #ifdef CONFIG_X86_32
1063 # ifdef CONFIG_SMP
1064 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1065 # else
1066 c->apicid = c->initial_apicid;
1067 # endif
1068 #endif
1069 c->phys_proc_id = c->initial_apicid;
1070 }
1071
1072 get_model_name(c); /* Default name */
1073
1074 detect_nopl(c);
1075
1076 detect_null_seg_behavior(c);
1077
1078 /*
1079 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1080 * systems that run Linux at CPL > 0 may or may not have the
1081 * issue, but, even if they have the issue, there's absolutely
1082 * nothing we can do about it because we can't use the real IRET
1083 * instruction.
1084 *
1085 * NB: For the time being, only 32-bit kernels support
1086 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1087 * whether to apply espfix using paravirt hooks. If any
1088 * non-paravirt system ever shows up that does *not* have the
1089 * ESPFIX issue, we can change this.
1090 */
1091 #ifdef CONFIG_X86_32
1092 # ifdef CONFIG_PARAVIRT
1093 do {
1094 extern void native_iret(void);
1095 if (pv_cpu_ops.iret == native_iret)
1096 set_cpu_bug(c, X86_BUG_ESPFIX);
1097 } while (0);
1098 # else
1099 set_cpu_bug(c, X86_BUG_ESPFIX);
1100 # endif
1101 #endif
1102 }
1103
x86_init_cache_qos(struct cpuinfo_x86 * c)1104 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1105 {
1106 /*
1107 * The heavy lifting of max_rmid and cache_occ_scale are handled
1108 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1109 * in case CQM bits really aren't there in this CPU.
1110 */
1111 if (c != &boot_cpu_data) {
1112 boot_cpu_data.x86_cache_max_rmid =
1113 min(boot_cpu_data.x86_cache_max_rmid,
1114 c->x86_cache_max_rmid);
1115 }
1116 }
1117
1118 /*
1119 * Validate that ACPI/mptables have the same information about the
1120 * effective APIC id and update the package map.
1121 */
validate_apic_and_package_id(struct cpuinfo_x86 * c)1122 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1123 {
1124 #ifdef CONFIG_SMP
1125 unsigned int apicid, cpu = smp_processor_id();
1126
1127 apicid = apic->cpu_present_to_apicid(cpu);
1128
1129 if (apicid != c->apicid) {
1130 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1131 cpu, apicid, c->initial_apicid);
1132 }
1133 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1134 #else
1135 c->logical_proc_id = 0;
1136 #endif
1137 }
1138
1139 /*
1140 * This does the hard work of actually picking apart the CPU stuff...
1141 */
identify_cpu(struct cpuinfo_x86 * c)1142 static void identify_cpu(struct cpuinfo_x86 *c)
1143 {
1144 int i;
1145
1146 c->loops_per_jiffy = loops_per_jiffy;
1147 c->x86_cache_size = 0;
1148 c->x86_vendor = X86_VENDOR_UNKNOWN;
1149 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1150 c->x86_vendor_id[0] = '\0'; /* Unset */
1151 c->x86_model_id[0] = '\0'; /* Unset */
1152 c->x86_max_cores = 1;
1153 c->x86_coreid_bits = 0;
1154 c->cu_id = 0xff;
1155 #ifdef CONFIG_X86_64
1156 c->x86_clflush_size = 64;
1157 c->x86_phys_bits = 36;
1158 c->x86_virt_bits = 48;
1159 #else
1160 c->cpuid_level = -1; /* CPUID not detected */
1161 c->x86_clflush_size = 32;
1162 c->x86_phys_bits = 32;
1163 c->x86_virt_bits = 32;
1164 #endif
1165 c->x86_cache_alignment = c->x86_clflush_size;
1166 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1167
1168 generic_identify(c);
1169
1170 if (this_cpu->c_identify)
1171 this_cpu->c_identify(c);
1172
1173 /* Clear/Set all flags overridden by options, after probe */
1174 apply_forced_caps(c);
1175
1176 #ifdef CONFIG_X86_64
1177 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1178 #endif
1179
1180 /*
1181 * Vendor-specific initialization. In this section we
1182 * canonicalize the feature flags, meaning if there are
1183 * features a certain CPU supports which CPUID doesn't
1184 * tell us, CPUID claiming incorrect flags, or other bugs,
1185 * we handle them here.
1186 *
1187 * At the end of this section, c->x86_capability better
1188 * indicate the features this CPU genuinely supports!
1189 */
1190 if (this_cpu->c_init)
1191 this_cpu->c_init(c);
1192
1193 /* Disable the PN if appropriate */
1194 squash_the_stupid_serial_number(c);
1195
1196 /* Set up SMEP/SMAP */
1197 setup_smep(c);
1198 setup_smap(c);
1199
1200 /* Set up PCID */
1201 setup_pcid(c);
1202
1203 /*
1204 * The vendor-specific functions might have changed features.
1205 * Now we do "generic changes."
1206 */
1207
1208 /* Filter out anything that depends on CPUID levels we don't have */
1209 filter_cpuid_features(c, true);
1210
1211 /* If the model name is still unset, do table lookup. */
1212 if (!c->x86_model_id[0]) {
1213 const char *p;
1214 p = table_lookup_model(c);
1215 if (p)
1216 strcpy(c->x86_model_id, p);
1217 else
1218 /* Last resort... */
1219 sprintf(c->x86_model_id, "%02x/%02x",
1220 c->x86, c->x86_model);
1221 }
1222
1223 #ifdef CONFIG_X86_64
1224 detect_ht(c);
1225 #endif
1226
1227 init_hypervisor(c);
1228 x86_init_rdrand(c);
1229 x86_init_cache_qos(c);
1230 setup_pku(c);
1231
1232 /*
1233 * Clear/Set all flags overridden by options, need do it
1234 * before following smp all cpus cap AND.
1235 */
1236 apply_forced_caps(c);
1237
1238 /*
1239 * On SMP, boot_cpu_data holds the common feature set between
1240 * all CPUs; so make sure that we indicate which features are
1241 * common between the CPUs. The first time this routine gets
1242 * executed, c == &boot_cpu_data.
1243 */
1244 if (c != &boot_cpu_data) {
1245 /* AND the already accumulated flags with these */
1246 for (i = 0; i < NCAPINTS; i++)
1247 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1248
1249 /* OR, i.e. replicate the bug flags */
1250 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1251 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1252 }
1253
1254 /* Init Machine Check Exception if available. */
1255 mcheck_cpu_init(c);
1256
1257 select_idle_routine(c);
1258
1259 #ifdef CONFIG_NUMA
1260 numa_add_cpu(smp_processor_id());
1261 #endif
1262 }
1263
1264 /*
1265 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1266 * on 32-bit kernels:
1267 */
1268 #ifdef CONFIG_X86_32
enable_sep_cpu(void)1269 void enable_sep_cpu(void)
1270 {
1271 struct tss_struct *tss;
1272 int cpu;
1273
1274 if (!boot_cpu_has(X86_FEATURE_SEP))
1275 return;
1276
1277 cpu = get_cpu();
1278 tss = &per_cpu(cpu_tss, cpu);
1279
1280 /*
1281 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1282 * see the big comment in struct x86_hw_tss's definition.
1283 */
1284
1285 tss->x86_tss.ss1 = __KERNEL_CS;
1286 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1287
1288 wrmsr(MSR_IA32_SYSENTER_ESP,
1289 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1290 0);
1291
1292 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1293
1294 put_cpu();
1295 }
1296 #endif
1297
identify_boot_cpu(void)1298 void __init identify_boot_cpu(void)
1299 {
1300 identify_cpu(&boot_cpu_data);
1301 init_amd_e400_c1e_mask();
1302 #ifdef CONFIG_X86_32
1303 sysenter_setup();
1304 enable_sep_cpu();
1305 #endif
1306 cpu_detect_tlb(&boot_cpu_data);
1307 }
1308
identify_secondary_cpu(struct cpuinfo_x86 * c)1309 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1310 {
1311 BUG_ON(c == &boot_cpu_data);
1312 identify_cpu(c);
1313 #ifdef CONFIG_X86_32
1314 enable_sep_cpu();
1315 #endif
1316 mtrr_ap_init();
1317 validate_apic_and_package_id(c);
1318 }
1319
1320 struct msr_range {
1321 unsigned min;
1322 unsigned max;
1323 };
1324
1325 static const struct msr_range msr_range_array[] = {
1326 { 0x00000000, 0x00000418},
1327 { 0xc0000000, 0xc000040b},
1328 { 0xc0010000, 0xc0010142},
1329 { 0xc0011000, 0xc001103b},
1330 };
1331
__print_cpu_msr(void)1332 static void __print_cpu_msr(void)
1333 {
1334 unsigned index_min, index_max;
1335 unsigned index;
1336 u64 val;
1337 int i;
1338
1339 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1340 index_min = msr_range_array[i].min;
1341 index_max = msr_range_array[i].max;
1342
1343 for (index = index_min; index < index_max; index++) {
1344 if (rdmsrl_safe(index, &val))
1345 continue;
1346 pr_info(" MSR%08x: %016llx\n", index, val);
1347 }
1348 }
1349 }
1350
1351 static int show_msr;
1352
setup_show_msr(char * arg)1353 static __init int setup_show_msr(char *arg)
1354 {
1355 int num;
1356
1357 get_option(&arg, &num);
1358
1359 if (num > 0)
1360 show_msr = num;
1361 return 1;
1362 }
1363 __setup("show_msr=", setup_show_msr);
1364
setup_noclflush(char * arg)1365 static __init int setup_noclflush(char *arg)
1366 {
1367 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1368 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1369 return 1;
1370 }
1371 __setup("noclflush", setup_noclflush);
1372
print_cpu_info(struct cpuinfo_x86 * c)1373 void print_cpu_info(struct cpuinfo_x86 *c)
1374 {
1375 const char *vendor = NULL;
1376
1377 if (c->x86_vendor < X86_VENDOR_NUM) {
1378 vendor = this_cpu->c_vendor;
1379 } else {
1380 if (c->cpuid_level >= 0)
1381 vendor = c->x86_vendor_id;
1382 }
1383
1384 if (vendor && !strstr(c->x86_model_id, vendor))
1385 pr_cont("%s ", vendor);
1386
1387 if (c->x86_model_id[0])
1388 pr_cont("%s", c->x86_model_id);
1389 else
1390 pr_cont("%d86", c->x86);
1391
1392 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1393
1394 if (c->x86_stepping || c->cpuid_level >= 0)
1395 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1396 else
1397 pr_cont(")\n");
1398
1399 print_cpu_msr(c);
1400 }
1401
print_cpu_msr(struct cpuinfo_x86 * c)1402 void print_cpu_msr(struct cpuinfo_x86 *c)
1403 {
1404 if (c->cpu_index < show_msr)
1405 __print_cpu_msr();
1406 }
1407
setup_disablecpuid(char * arg)1408 static __init int setup_disablecpuid(char *arg)
1409 {
1410 int bit;
1411
1412 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1413 setup_clear_cpu_cap(bit);
1414 else
1415 return 0;
1416
1417 return 1;
1418 }
1419 __setup("clearcpuid=", setup_disablecpuid);
1420
1421 #ifdef CONFIG_X86_64
1422 struct desc_ptr idt_descr __ro_after_init = {
1423 .size = NR_VECTORS * 16 - 1,
1424 .address = (unsigned long) idt_table,
1425 };
1426 const struct desc_ptr debug_idt_descr = {
1427 .size = NR_VECTORS * 16 - 1,
1428 .address = (unsigned long) debug_idt_table,
1429 };
1430
1431 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1432 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1433
1434 /*
1435 * The following percpu variables are hot. Align current_task to
1436 * cacheline size such that they fall in the same cacheline.
1437 */
1438 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1439 &init_task;
1440 EXPORT_PER_CPU_SYMBOL(current_task);
1441
1442 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1443 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1444
1445 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1446
1447 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1448 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1449
1450 /*
1451 * Special IST stacks which the CPU switches to when it calls
1452 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1453 * limit), all of them are 4K, except the debug stack which
1454 * is 8K.
1455 */
1456 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1457 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1458 [DEBUG_STACK - 1] = DEBUG_STKSZ
1459 };
1460
1461 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(char, exception_stacks
1462 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1463
1464 /* May not be marked __init: used by software suspend */
syscall_init(void)1465 void syscall_init(void)
1466 {
1467 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1468 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1469
1470 #ifdef CONFIG_IA32_EMULATION
1471 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1472 /*
1473 * This only works on Intel CPUs.
1474 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1475 * This does not cause SYSENTER to jump to the wrong location, because
1476 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1477 */
1478 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1479 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1480 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1481 #else
1482 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1483 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1484 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1485 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1486 #endif
1487
1488 /* Flags to clear on syscall */
1489 wrmsrl(MSR_SYSCALL_MASK,
1490 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1491 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1492 }
1493
1494 /*
1495 * Copies of the original ist values from the tss are only accessed during
1496 * debugging, no special alignment required.
1497 */
1498 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1499
1500 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1501 DEFINE_PER_CPU(int, debug_stack_usage);
1502
is_debug_stack(unsigned long addr)1503 int is_debug_stack(unsigned long addr)
1504 {
1505 return __this_cpu_read(debug_stack_usage) ||
1506 (addr <= __this_cpu_read(debug_stack_addr) &&
1507 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1508 }
1509 NOKPROBE_SYMBOL(is_debug_stack);
1510
1511 DEFINE_PER_CPU(u32, debug_idt_ctr);
1512
debug_stack_set_zero(void)1513 void debug_stack_set_zero(void)
1514 {
1515 this_cpu_inc(debug_idt_ctr);
1516 load_current_idt();
1517 }
1518 NOKPROBE_SYMBOL(debug_stack_set_zero);
1519
debug_stack_reset(void)1520 void debug_stack_reset(void)
1521 {
1522 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1523 return;
1524 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1525 load_current_idt();
1526 }
1527 NOKPROBE_SYMBOL(debug_stack_reset);
1528
1529 #else /* CONFIG_X86_64 */
1530
1531 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1532 EXPORT_PER_CPU_SYMBOL(current_task);
1533 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1534 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1535
1536 /*
1537 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1538 * the top of the kernel stack. Use an extra percpu variable to track the
1539 * top of the kernel stack directly.
1540 */
1541 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1542 (unsigned long)&init_thread_union + THREAD_SIZE;
1543 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1544
1545 #ifdef CONFIG_CC_STACKPROTECTOR
1546 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1547 #endif
1548
1549 #endif /* CONFIG_X86_64 */
1550
1551 /*
1552 * Clear all 6 debug registers:
1553 */
clear_all_debug_regs(void)1554 static void clear_all_debug_regs(void)
1555 {
1556 int i;
1557
1558 for (i = 0; i < 8; i++) {
1559 /* Ignore db4, db5 */
1560 if ((i == 4) || (i == 5))
1561 continue;
1562
1563 set_debugreg(0, i);
1564 }
1565 }
1566
1567 #ifdef CONFIG_KGDB
1568 /*
1569 * Restore debug regs if using kgdbwait and you have a kernel debugger
1570 * connection established.
1571 */
dbg_restore_debug_regs(void)1572 static void dbg_restore_debug_regs(void)
1573 {
1574 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1575 arch_kgdb_ops.correct_hw_break();
1576 }
1577 #else /* ! CONFIG_KGDB */
1578 #define dbg_restore_debug_regs()
1579 #endif /* ! CONFIG_KGDB */
1580
wait_for_master_cpu(int cpu)1581 static void wait_for_master_cpu(int cpu)
1582 {
1583 #ifdef CONFIG_SMP
1584 /*
1585 * wait for ACK from master CPU before continuing
1586 * with AP initialization
1587 */
1588 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1589 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1590 cpu_relax();
1591 #endif
1592 }
1593
1594 /*
1595 * cpu_init() initializes state that is per-CPU. Some data is already
1596 * initialized (naturally) in the bootstrap process, such as the GDT
1597 * and IDT. We reload them nevertheless, this function acts as a
1598 * 'CPU state barrier', nothing should get across.
1599 * A lot of state is already set up in PDA init for 64 bit
1600 */
1601 #ifdef CONFIG_X86_64
1602
cpu_init(void)1603 void cpu_init(void)
1604 {
1605 struct orig_ist *oist;
1606 struct task_struct *me;
1607 struct tss_struct *t;
1608 unsigned long v;
1609 int cpu = raw_smp_processor_id();
1610 int i;
1611
1612 wait_for_master_cpu(cpu);
1613
1614 /*
1615 * Initialize the CR4 shadow before doing anything that could
1616 * try to read it.
1617 */
1618 cr4_init_shadow();
1619 if (!kaiser_enabled) {
1620 /*
1621 * secondary_startup_64() deferred setting PGE in cr4:
1622 * probe_page_size_mask() sets it on the boot cpu,
1623 * but it needs to be set on each secondary cpu.
1624 */
1625 cr4_set_bits(X86_CR4_PGE);
1626 }
1627
1628 /*
1629 * Load microcode on this cpu if a valid microcode is available.
1630 * This is early microcode loading procedure.
1631 */
1632 load_ucode_ap();
1633
1634 t = &per_cpu(cpu_tss, cpu);
1635 oist = &per_cpu(orig_ist, cpu);
1636
1637 #ifdef CONFIG_NUMA
1638 if (this_cpu_read(numa_node) == 0 &&
1639 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1640 set_numa_node(early_cpu_to_node(cpu));
1641 #endif
1642
1643 me = current;
1644
1645 pr_debug("Initializing CPU#%d\n", cpu);
1646
1647 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1648
1649 /*
1650 * Initialize the per-CPU GDT with the boot GDT,
1651 * and set up the GDT descriptor:
1652 */
1653
1654 switch_to_new_gdt(cpu);
1655 loadsegment(fs, 0);
1656
1657 load_current_idt();
1658
1659 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1660 syscall_init();
1661
1662 wrmsrl(MSR_FS_BASE, 0);
1663 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1664 barrier();
1665
1666 x86_configure_nx();
1667 x2apic_setup();
1668
1669 /*
1670 * set up and load the per-CPU TSS
1671 */
1672 if (!oist->ist[0]) {
1673 char *estacks = per_cpu(exception_stacks, cpu);
1674
1675 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1676 estacks += exception_stack_sizes[v];
1677 oist->ist[v] = t->x86_tss.ist[v] =
1678 (unsigned long)estacks;
1679 if (v == DEBUG_STACK-1)
1680 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1681 }
1682 }
1683
1684 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1685
1686 /*
1687 * <= is required because the CPU will access up to
1688 * 8 bits beyond the end of the IO permission bitmap.
1689 */
1690 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1691 t->io_bitmap[i] = ~0UL;
1692
1693 atomic_inc(&init_mm.mm_count);
1694 me->active_mm = &init_mm;
1695 BUG_ON(me->mm);
1696 enter_lazy_tlb(&init_mm, me);
1697
1698 load_sp0(t, ¤t->thread);
1699 set_tss_desc(cpu, t);
1700 load_TR_desc();
1701 load_mm_ldt(&init_mm);
1702
1703 clear_all_debug_regs();
1704 dbg_restore_debug_regs();
1705
1706 fpu__init_cpu();
1707
1708 if (is_uv_system())
1709 uv_cpu_init();
1710 }
1711
1712 #else
1713
cpu_init(void)1714 void cpu_init(void)
1715 {
1716 int cpu = smp_processor_id();
1717 struct task_struct *curr = current;
1718 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1719 struct thread_struct *thread = &curr->thread;
1720
1721 wait_for_master_cpu(cpu);
1722
1723 /*
1724 * Initialize the CR4 shadow before doing anything that could
1725 * try to read it.
1726 */
1727 cr4_init_shadow();
1728
1729 show_ucode_info_early();
1730
1731 pr_info("Initializing CPU#%d\n", cpu);
1732
1733 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1734 boot_cpu_has(X86_FEATURE_TSC) ||
1735 boot_cpu_has(X86_FEATURE_DE))
1736 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1737
1738 load_current_idt();
1739 switch_to_new_gdt(cpu);
1740
1741 /*
1742 * Set up and load the per-CPU TSS and LDT
1743 */
1744 atomic_inc(&init_mm.mm_count);
1745 curr->active_mm = &init_mm;
1746 BUG_ON(curr->mm);
1747 enter_lazy_tlb(&init_mm, curr);
1748
1749 load_sp0(t, thread);
1750 set_tss_desc(cpu, t);
1751 load_TR_desc();
1752 load_mm_ldt(&init_mm);
1753
1754 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1755
1756 #ifdef CONFIG_DOUBLEFAULT
1757 /* Set up doublefault TSS pointer in the GDT */
1758 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1759 #endif
1760
1761 clear_all_debug_regs();
1762 dbg_restore_debug_regs();
1763
1764 fpu__init_cpu();
1765 }
1766 #endif
1767
bsp_resume(void)1768 static void bsp_resume(void)
1769 {
1770 if (this_cpu->c_bsp_resume)
1771 this_cpu->c_bsp_resume(&boot_cpu_data);
1772 }
1773
1774 static struct syscore_ops cpu_syscore_ops = {
1775 .resume = bsp_resume,
1776 };
1777
init_cpu_syscore(void)1778 static int __init init_cpu_syscore(void)
1779 {
1780 register_syscore_ops(&cpu_syscore_ops);
1781 return 0;
1782 }
1783 core_initcall(init_cpu_syscore);
1784