1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _AMD_POWERPLAY_H_ 24 #define _AMD_POWERPLAY_H_ 25 26 #include <linux/seq_file.h> 27 #include <linux/types.h> 28 #include <linux/errno.h> 29 #include "amd_shared.h" 30 #include "cgs_common.h" 31 32 enum amd_pp_sensors { 33 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 34 AMDGPU_PP_SENSOR_VDDNB, 35 AMDGPU_PP_SENSOR_VDDGFX, 36 AMDGPU_PP_SENSOR_UVD_VCLK, 37 AMDGPU_PP_SENSOR_UVD_DCLK, 38 AMDGPU_PP_SENSOR_VCE_ECCLK, 39 AMDGPU_PP_SENSOR_GPU_LOAD, 40 AMDGPU_PP_SENSOR_GFX_MCLK, 41 AMDGPU_PP_SENSOR_GPU_TEMP, 42 AMDGPU_PP_SENSOR_VCE_POWER, 43 AMDGPU_PP_SENSOR_UVD_POWER, 44 }; 45 46 enum amd_pp_event { 47 AMD_PP_EVENT_INITIALIZE = 0, 48 AMD_PP_EVENT_UNINITIALIZE, 49 AMD_PP_EVENT_POWER_SOURCE_CHANGE, 50 AMD_PP_EVENT_SUSPEND, 51 AMD_PP_EVENT_RESUME, 52 AMD_PP_EVENT_ENTER_REST_STATE, 53 AMD_PP_EVENT_EXIT_REST_STATE, 54 AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, 55 AMD_PP_EVENT_THERMAL_NOTIFICATION, 56 AMD_PP_EVENT_VBIOS_NOTIFICATION, 57 AMD_PP_EVENT_ENTER_THERMAL_STATE, 58 AMD_PP_EVENT_EXIT_THERMAL_STATE, 59 AMD_PP_EVENT_ENTER_FORCED_STATE, 60 AMD_PP_EVENT_EXIT_FORCED_STATE, 61 AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE, 62 AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE, 63 AMD_PP_EVENT_ENTER_SCREEN_SAVER, 64 AMD_PP_EVENT_EXIT_SCREEN_SAVER, 65 AMD_PP_EVENT_VPU_RECOVERY_BEGIN, 66 AMD_PP_EVENT_VPU_RECOVERY_END, 67 AMD_PP_EVENT_ENABLE_POWER_PLAY, 68 AMD_PP_EVENT_DISABLE_POWER_PLAY, 69 AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL, 70 AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE, 71 AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE, 72 AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE, 73 AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE, 74 AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST, 75 AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST, 76 AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE, 77 AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE, 78 AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING, 79 AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING, 80 AMD_PP_EVENT_ENABLE_CGPG, 81 AMD_PP_EVENT_DISABLE_CGPG, 82 AMD_PP_EVENT_ENTER_TEXT_MODE, 83 AMD_PP_EVENT_EXIT_TEXT_MODE, 84 AMD_PP_EVENT_VIDEO_START, 85 AMD_PP_EVENT_VIDEO_STOP, 86 AMD_PP_EVENT_ENABLE_USER_STATE, 87 AMD_PP_EVENT_DISABLE_USER_STATE, 88 AMD_PP_EVENT_READJUST_POWER_STATE, 89 AMD_PP_EVENT_START_INACTIVITY, 90 AMD_PP_EVENT_STOP_INACTIVITY, 91 AMD_PP_EVENT_LINKED_ADAPTERS_READY, 92 AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE, 93 AMD_PP_EVENT_COMPLETE_INIT, 94 AMD_PP_EVENT_CRITICAL_THERMAL_FAULT, 95 AMD_PP_EVENT_BACKLIGHT_CHANGED, 96 AMD_PP_EVENT_ENABLE_VARI_BRIGHT, 97 AMD_PP_EVENT_DISABLE_VARI_BRIGHT, 98 AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS, 99 AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS, 100 AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL, 101 AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT, 102 AMD_PP_EVENT_SCREEN_ON, 103 AMD_PP_EVENT_SCREEN_OFF, 104 AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE, 105 AMD_PP_EVENT_ENTER_ULP_STATE, 106 AMD_PP_EVENT_EXIT_ULP_STATE, 107 AMD_PP_EVENT_REGISTER_IP_STATE, 108 AMD_PP_EVENT_UNREGISTER_IP_STATE, 109 AMD_PP_EVENT_ENTER_MGPU_MODE, 110 AMD_PP_EVENT_EXIT_MGPU_MODE, 111 AMD_PP_EVENT_ENTER_MULTI_GPU_MODE, 112 AMD_PP_EVENT_PRE_SUSPEND, 113 AMD_PP_EVENT_PRE_RESUME, 114 AMD_PP_EVENT_ENTER_BACOS, 115 AMD_PP_EVENT_EXIT_BACOS, 116 AMD_PP_EVENT_RESUME_BACO, 117 AMD_PP_EVENT_RESET_BACO, 118 AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS, 119 AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS, 120 AMD_PP_EVENT_START_COMPUTE_APPLICATION, 121 AMD_PP_EVENT_STOP_COMPUTE_APPLICATION, 122 AMD_PP_EVENT_REDUCE_POWER_LIMIT, 123 AMD_PP_EVENT_ENTER_FRAME_LOCK, 124 AMD_PP_EVENT_EXIT_FRAME_LOOCK, 125 AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO, 126 AMD_PP_EVENT_LONG_IDLE_ENTER_BACO, 127 AMD_PP_EVENT_LONG_IDLE_EXIT_BACO, 128 AMD_PP_EVENT_HIBERNATE, 129 AMD_PP_EVENT_CONNECTED_STANDBY, 130 AMD_PP_EVENT_ENTER_SELF_REFRESH, 131 AMD_PP_EVENT_EXIT_SELF_REFRESH, 132 AMD_PP_EVENT_START_AVFS_BTC, 133 AMD_PP_EVENT_MAX 134 }; 135 136 enum amd_dpm_forced_level { 137 AMD_DPM_FORCED_LEVEL_AUTO = 0, 138 AMD_DPM_FORCED_LEVEL_LOW = 1, 139 AMD_DPM_FORCED_LEVEL_HIGH = 2, 140 AMD_DPM_FORCED_LEVEL_MANUAL = 3, 141 }; 142 143 struct amd_pp_init { 144 struct cgs_device *device; 145 uint32_t chip_family; 146 uint32_t chip_id; 147 }; 148 149 enum amd_pp_display_config_type{ 150 AMD_PP_DisplayConfigType_None = 0, 151 AMD_PP_DisplayConfigType_DP54 , 152 AMD_PP_DisplayConfigType_DP432 , 153 AMD_PP_DisplayConfigType_DP324 , 154 AMD_PP_DisplayConfigType_DP27, 155 AMD_PP_DisplayConfigType_DP243, 156 AMD_PP_DisplayConfigType_DP216, 157 AMD_PP_DisplayConfigType_DP162, 158 AMD_PP_DisplayConfigType_HDMI6G , 159 AMD_PP_DisplayConfigType_HDMI297 , 160 AMD_PP_DisplayConfigType_HDMI162, 161 AMD_PP_DisplayConfigType_LVDS, 162 AMD_PP_DisplayConfigType_DVI, 163 AMD_PP_DisplayConfigType_WIRELESS, 164 AMD_PP_DisplayConfigType_VGA 165 }; 166 167 struct single_display_configuration 168 { 169 uint32_t controller_index; 170 uint32_t controller_id; 171 uint32_t signal_type; 172 uint32_t display_state; 173 /* phy id for the primary internal transmitter */ 174 uint8_t primary_transmitter_phyi_d; 175 /* bitmap with the active lanes */ 176 uint8_t primary_transmitter_active_lanemap; 177 /* phy id for the secondary internal transmitter (for dual-link dvi) */ 178 uint8_t secondary_transmitter_phy_id; 179 /* bitmap with the active lanes */ 180 uint8_t secondary_transmitter_active_lanemap; 181 /* misc phy settings for SMU. */ 182 uint32_t config_flags; 183 uint32_t display_type; 184 uint32_t view_resolution_cx; 185 uint32_t view_resolution_cy; 186 enum amd_pp_display_config_type displayconfigtype; 187 uint32_t vertical_refresh; /* for active display */ 188 }; 189 190 #define MAX_NUM_DISPLAY 32 191 192 struct amd_pp_display_configuration { 193 bool nb_pstate_switch_disable;/* controls NB PState switch */ 194 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 195 bool cpu_pstate_disable; 196 uint32_t cpu_pstate_separation_time; 197 198 uint32_t num_display; /* total number of display*/ 199 uint32_t num_path_including_non_display; 200 uint32_t crossfire_display_index; 201 uint32_t min_mem_set_clock; 202 uint32_t min_core_set_clock; 203 /* unit 10KHz x bit*/ 204 uint32_t min_bus_bandwidth; 205 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ 206 uint32_t min_core_set_clock_in_sr; 207 208 struct single_display_configuration displays[MAX_NUM_DISPLAY]; 209 210 uint32_t vrefresh; /* for active display*/ 211 212 uint32_t min_vblank_time; /* for active display*/ 213 bool multi_monitor_in_sync; 214 /* Controller Index of primary display - used in MCLK SMC switching hang 215 * SW Workaround*/ 216 uint32_t crtc_index; 217 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ 218 uint32_t line_time_in_us; 219 bool invalid_vblank_time; 220 221 uint32_t display_clk; 222 /* 223 * for given display configuration if multimonitormnsync == false then 224 * Memory clock DPMS with this latency or below is allowed, DPMS with 225 * higher latency not allowed. 226 */ 227 uint32_t dce_tolerable_mclk_in_active_latency; 228 }; 229 230 struct amd_pp_simple_clock_info { 231 uint32_t engine_max_clock; 232 uint32_t memory_max_clock; 233 uint32_t level; 234 }; 235 236 enum PP_DAL_POWERLEVEL { 237 PP_DAL_POWERLEVEL_INVALID = 0, 238 PP_DAL_POWERLEVEL_ULTRALOW, 239 PP_DAL_POWERLEVEL_LOW, 240 PP_DAL_POWERLEVEL_NOMINAL, 241 PP_DAL_POWERLEVEL_PERFORMANCE, 242 243 PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, 244 PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, 245 PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, 246 PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, 247 PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, 248 PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, 249 PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, 250 PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, 251 }; 252 253 struct amd_pp_clock_info { 254 uint32_t min_engine_clock; 255 uint32_t max_engine_clock; 256 uint32_t min_memory_clock; 257 uint32_t max_memory_clock; 258 uint32_t min_bus_bandwidth; 259 uint32_t max_bus_bandwidth; 260 uint32_t max_engine_clock_in_sr; 261 uint32_t min_engine_clock_in_sr; 262 enum PP_DAL_POWERLEVEL max_clocks_state; 263 }; 264 265 enum amd_pp_clock_type { 266 amd_pp_disp_clock = 1, 267 amd_pp_sys_clock, 268 amd_pp_mem_clock 269 }; 270 271 #define MAX_NUM_CLOCKS 16 272 273 struct amd_pp_clocks { 274 uint32_t count; 275 uint32_t clock[MAX_NUM_CLOCKS]; 276 uint32_t latency[MAX_NUM_CLOCKS]; 277 }; 278 279 280 enum { 281 PP_GROUP_UNKNOWN = 0, 282 PP_GROUP_GFX = 1, 283 PP_GROUP_SYS, 284 PP_GROUP_MAX 285 }; 286 287 enum pp_clock_type { 288 PP_SCLK, 289 PP_MCLK, 290 PP_PCIE, 291 }; 292 293 struct pp_states_info { 294 uint32_t nums; 295 uint32_t states[16]; 296 }; 297 298 #define PP_GROUP_MASK 0xF0000000 299 #define PP_GROUP_SHIFT 28 300 301 #define PP_BLOCK_MASK 0x0FFFFF00 302 #define PP_BLOCK_SHIFT 8 303 304 #define PP_BLOCK_GFX_CG 0x01 305 #define PP_BLOCK_GFX_MG 0x02 306 #define PP_BLOCK_GFX_3D 0x04 307 #define PP_BLOCK_GFX_RLC 0x08 308 #define PP_BLOCK_GFX_CP 0x10 309 #define PP_BLOCK_SYS_BIF 0x01 310 #define PP_BLOCK_SYS_MC 0x02 311 #define PP_BLOCK_SYS_ROM 0x04 312 #define PP_BLOCK_SYS_DRM 0x08 313 #define PP_BLOCK_SYS_HDP 0x10 314 #define PP_BLOCK_SYS_SDMA 0x20 315 316 #define PP_STATE_MASK 0x0000000F 317 #define PP_STATE_SHIFT 0 318 #define PP_STATE_SUPPORT_MASK 0x000000F0 319 #define PP_STATE_SUPPORT_SHIFT 0 320 321 #define PP_STATE_CG 0x01 322 #define PP_STATE_LS 0x02 323 #define PP_STATE_DS 0x04 324 #define PP_STATE_SD 0x08 325 #define PP_STATE_SUPPORT_CG 0x10 326 #define PP_STATE_SUPPORT_LS 0x20 327 #define PP_STATE_SUPPORT_DS 0x40 328 #define PP_STATE_SUPPORT_SD 0x80 329 330 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ 331 block << PP_BLOCK_SHIFT |\ 332 support << PP_STATE_SUPPORT_SHIFT |\ 333 state << PP_STATE_SHIFT) 334 335 struct amd_powerplay_funcs { 336 int (*get_temperature)(void *handle); 337 int (*load_firmware)(void *handle); 338 int (*wait_for_fw_loading_complete)(void *handle); 339 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 340 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 341 enum amd_pm_state_type (*get_current_power_state)(void *handle); 342 int (*get_sclk)(void *handle, bool low); 343 int (*get_mclk)(void *handle, bool low); 344 int (*powergate_vce)(void *handle, bool gate); 345 int (*powergate_uvd)(void *handle, bool gate); 346 int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id, 347 void *input, void *output); 348 int (*set_fan_control_mode)(void *handle, uint32_t mode); 349 int (*get_fan_control_mode)(void *handle); 350 int (*set_fan_speed_percent)(void *handle, uint32_t percent); 351 int (*get_fan_speed_percent)(void *handle, uint32_t *speed); 352 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 353 int (*get_pp_table)(void *handle, char **table); 354 int (*set_pp_table)(void *handle, const char *buf, size_t size); 355 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 356 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 357 int (*get_sclk_od)(void *handle); 358 int (*set_sclk_od)(void *handle, uint32_t value); 359 int (*get_mclk_od)(void *handle); 360 int (*set_mclk_od)(void *handle, uint32_t value); 361 int (*read_sensor)(void *handle, int idx, int32_t *value); 362 }; 363 364 struct amd_powerplay { 365 void *pp_handle; 366 const struct amd_ip_funcs *ip_funcs; 367 const struct amd_powerplay_funcs *pp_funcs; 368 }; 369 370 int amd_powerplay_init(struct amd_pp_init *pp_init, 371 struct amd_powerplay *amd_pp); 372 373 int amd_powerplay_fini(void *handle); 374 375 int amd_powerplay_reset(void *handle); 376 377 int amd_powerplay_display_configuration_change(void *handle, 378 const struct amd_pp_display_configuration *input); 379 380 int amd_powerplay_get_display_power_level(void *handle, 381 struct amd_pp_simple_clock_info *output); 382 383 int amd_powerplay_get_current_clocks(void *handle, 384 struct amd_pp_clock_info *output); 385 386 int amd_powerplay_get_clock_by_type(void *handle, 387 enum amd_pp_clock_type type, 388 struct amd_pp_clocks *clocks); 389 390 int amd_powerplay_get_display_mode_validation_clocks(void *handle, 391 struct amd_pp_simple_clock_info *output); 392 393 int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id); 394 395 #endif /* _AMD_POWERPLAY_H_ */ 396