1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/tcp.h>
13 #include <linux/ip.h>
14 #include <linux/in.h>
15 #include <linux/ipv6.h>
16 #include <linux/slab.h>
17 #include <net/ipv6.h>
18 #include <linux/if_ether.h>
19 #include <linux/highmem.h>
20 #include <linux/cache.h>
21 #include "net_driver.h"
22 #include "efx.h"
23 #include "io.h"
24 #include "nic.h"
25 #include "workarounds.h"
26 #include "ef10_regs.h"
27
28 #ifdef EFX_USE_PIO
29
30 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
31 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
32
33 #endif /* EFX_USE_PIO */
34
35 static inline unsigned int
efx_tx_queue_get_insert_index(const struct efx_tx_queue * tx_queue)36 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
37 {
38 return tx_queue->insert_count & tx_queue->ptr_mask;
39 }
40
41 static inline struct efx_tx_buffer *
__efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)42 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
43 {
44 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
45 }
46
47 static inline struct efx_tx_buffer *
efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)48 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
49 {
50 struct efx_tx_buffer *buffer =
51 __efx_tx_queue_get_insert_buffer(tx_queue);
52
53 EFX_BUG_ON_PARANOID(buffer->len);
54 EFX_BUG_ON_PARANOID(buffer->flags);
55 EFX_BUG_ON_PARANOID(buffer->unmap_len);
56
57 return buffer;
58 }
59
efx_dequeue_buffer(struct efx_tx_queue * tx_queue,struct efx_tx_buffer * buffer,unsigned int * pkts_compl,unsigned int * bytes_compl)60 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
61 struct efx_tx_buffer *buffer,
62 unsigned int *pkts_compl,
63 unsigned int *bytes_compl)
64 {
65 if (buffer->unmap_len) {
66 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
67 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
68 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
69 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
70 DMA_TO_DEVICE);
71 else
72 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
73 DMA_TO_DEVICE);
74 buffer->unmap_len = 0;
75 }
76
77 if (buffer->flags & EFX_TX_BUF_SKB) {
78 (*pkts_compl)++;
79 (*bytes_compl) += buffer->skb->len;
80 dev_consume_skb_any((struct sk_buff *)buffer->skb);
81 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
82 "TX queue %d transmission id %x complete\n",
83 tx_queue->queue, tx_queue->read_count);
84 } else if (buffer->flags & EFX_TX_BUF_HEAP) {
85 kfree(buffer->heap_buf);
86 }
87
88 buffer->len = 0;
89 buffer->flags = 0;
90 }
91
92 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
93 struct sk_buff *skb);
94
95 static inline unsigned
efx_max_tx_len(struct efx_nic * efx,dma_addr_t dma_addr)96 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
97 {
98 /* Depending on the NIC revision, we can use descriptor
99 * lengths up to 8K or 8K-1. However, since PCI Express
100 * devices must split read requests at 4K boundaries, there is
101 * little benefit from using descriptors that cross those
102 * boundaries and we keep things simple by not doing so.
103 */
104 unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
105
106 /* Work around hardware bug for unaligned buffers. */
107 if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
108 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
109
110 return len;
111 }
112
efx_tx_max_skb_descs(struct efx_nic * efx)113 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
114 {
115 /* Header and payload descriptor for each output segment, plus
116 * one for every input fragment boundary within a segment
117 */
118 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
119
120 /* Possibly one more per segment for the alignment workaround,
121 * or for option descriptors
122 */
123 if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
124 max_descs += EFX_TSO_MAX_SEGS;
125
126 /* Possibly more for PCIe page boundaries within input fragments */
127 if (PAGE_SIZE > EFX_PAGE_SIZE)
128 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
129 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
130
131 return max_descs;
132 }
133
efx_tx_maybe_stop_queue(struct efx_tx_queue * txq1)134 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
135 {
136 /* We need to consider both queues that the net core sees as one */
137 struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
138 struct efx_nic *efx = txq1->efx;
139 unsigned int fill_level;
140
141 fill_level = max(txq1->insert_count - txq1->old_read_count,
142 txq2->insert_count - txq2->old_read_count);
143 if (likely(fill_level < efx->txq_stop_thresh))
144 return;
145
146 /* We used the stale old_read_count above, which gives us a
147 * pessimistic estimate of the fill level (which may even
148 * validly be >= efx->txq_entries). Now try again using
149 * read_count (more likely to be a cache miss).
150 *
151 * If we read read_count and then conditionally stop the
152 * queue, it is possible for the completion path to race with
153 * us and complete all outstanding descriptors in the middle,
154 * after which there will be no more completions to wake it.
155 * Therefore we stop the queue first, then read read_count
156 * (with a memory barrier to ensure the ordering), then
157 * restart the queue if the fill level turns out to be low
158 * enough.
159 */
160 netif_tx_stop_queue(txq1->core_txq);
161 smp_mb();
162 txq1->old_read_count = ACCESS_ONCE(txq1->read_count);
163 txq2->old_read_count = ACCESS_ONCE(txq2->read_count);
164
165 fill_level = max(txq1->insert_count - txq1->old_read_count,
166 txq2->insert_count - txq2->old_read_count);
167 EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
168 if (likely(fill_level < efx->txq_stop_thresh)) {
169 smp_mb();
170 if (likely(!efx->loopback_selftest))
171 netif_tx_start_queue(txq1->core_txq);
172 }
173 }
174
175 #ifdef EFX_USE_PIO
176
177 struct efx_short_copy_buffer {
178 int used;
179 u8 buf[L1_CACHE_BYTES];
180 };
181
182 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
183 * Advances piobuf pointer. Leaves additional data in the copy buffer.
184 */
efx_memcpy_toio_aligned(struct efx_nic * efx,u8 __iomem ** piobuf,u8 * data,int len,struct efx_short_copy_buffer * copy_buf)185 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
186 u8 *data, int len,
187 struct efx_short_copy_buffer *copy_buf)
188 {
189 int block_len = len & ~(sizeof(copy_buf->buf) - 1);
190
191 __iowrite64_copy(*piobuf, data, block_len >> 3);
192 *piobuf += block_len;
193 len -= block_len;
194
195 if (len) {
196 data += block_len;
197 BUG_ON(copy_buf->used);
198 BUG_ON(len > sizeof(copy_buf->buf));
199 memcpy(copy_buf->buf, data, len);
200 copy_buf->used = len;
201 }
202 }
203
204 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
205 * Advances piobuf pointer. Leaves additional data in the copy buffer.
206 */
efx_memcpy_toio_aligned_cb(struct efx_nic * efx,u8 __iomem ** piobuf,u8 * data,int len,struct efx_short_copy_buffer * copy_buf)207 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
208 u8 *data, int len,
209 struct efx_short_copy_buffer *copy_buf)
210 {
211 if (copy_buf->used) {
212 /* if the copy buffer is partially full, fill it up and write */
213 int copy_to_buf =
214 min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
215
216 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
217 copy_buf->used += copy_to_buf;
218
219 /* if we didn't fill it up then we're done for now */
220 if (copy_buf->used < sizeof(copy_buf->buf))
221 return;
222
223 __iowrite64_copy(*piobuf, copy_buf->buf,
224 sizeof(copy_buf->buf) >> 3);
225 *piobuf += sizeof(copy_buf->buf);
226 data += copy_to_buf;
227 len -= copy_to_buf;
228 copy_buf->used = 0;
229 }
230
231 efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
232 }
233
efx_flush_copy_buffer(struct efx_nic * efx,u8 __iomem * piobuf,struct efx_short_copy_buffer * copy_buf)234 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
235 struct efx_short_copy_buffer *copy_buf)
236 {
237 /* if there's anything in it, write the whole buffer, including junk */
238 if (copy_buf->used)
239 __iowrite64_copy(piobuf, copy_buf->buf,
240 sizeof(copy_buf->buf) >> 3);
241 }
242
243 /* Traverse skb structure and copy fragments in to PIO buffer.
244 * Advances piobuf pointer.
245 */
efx_skb_copy_bits_to_pio(struct efx_nic * efx,struct sk_buff * skb,u8 __iomem ** piobuf,struct efx_short_copy_buffer * copy_buf)246 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
247 u8 __iomem **piobuf,
248 struct efx_short_copy_buffer *copy_buf)
249 {
250 int i;
251
252 efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
253 copy_buf);
254
255 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
256 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
257 u8 *vaddr;
258
259 vaddr = kmap_atomic(skb_frag_page(f));
260
261 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset,
262 skb_frag_size(f), copy_buf);
263 kunmap_atomic(vaddr);
264 }
265
266 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list);
267 }
268
269 static struct efx_tx_buffer *
efx_enqueue_skb_pio(struct efx_tx_queue * tx_queue,struct sk_buff * skb)270 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
271 {
272 struct efx_tx_buffer *buffer =
273 efx_tx_queue_get_insert_buffer(tx_queue);
274 u8 __iomem *piobuf = tx_queue->piobuf;
275
276 /* Copy to PIO buffer. Ensure the writes are padded to the end
277 * of a cache line, as this is required for write-combining to be
278 * effective on at least x86.
279 */
280
281 if (skb_shinfo(skb)->nr_frags) {
282 /* The size of the copy buffer will ensure all writes
283 * are the size of a cache line.
284 */
285 struct efx_short_copy_buffer copy_buf;
286
287 copy_buf.used = 0;
288
289 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
290 &piobuf, ©_buf);
291 efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf);
292 } else {
293 /* Pad the write to the size of a cache line.
294 * We can do this because we know the skb_shared_info sruct is
295 * after the source, and the destination buffer is big enough.
296 */
297 BUILD_BUG_ON(L1_CACHE_BYTES >
298 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
299 __iowrite64_copy(tx_queue->piobuf, skb->data,
300 ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
301 }
302
303 EFX_POPULATE_QWORD_5(buffer->option,
304 ESF_DZ_TX_DESC_IS_OPT, 1,
305 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
306 ESF_DZ_TX_PIO_CONT, 0,
307 ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
308 ESF_DZ_TX_PIO_BUF_ADDR,
309 tx_queue->piobuf_offset);
310 ++tx_queue->pio_packets;
311 ++tx_queue->insert_count;
312 return buffer;
313 }
314 #endif /* EFX_USE_PIO */
315
316 /*
317 * Add a socket buffer to a TX queue
318 *
319 * This maps all fragments of a socket buffer for DMA and adds them to
320 * the TX queue. The queue's insert pointer will be incremented by
321 * the number of fragments in the socket buffer.
322 *
323 * If any DMA mapping fails, any mapped fragments will be unmapped,
324 * the queue's insert pointer will be restored to its original value.
325 *
326 * This function is split out from efx_hard_start_xmit to allow the
327 * loopback test to direct packets via specific TX queues.
328 *
329 * Returns NETDEV_TX_OK.
330 * You must hold netif_tx_lock() to call this function.
331 */
efx_enqueue_skb(struct efx_tx_queue * tx_queue,struct sk_buff * skb)332 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
333 {
334 struct efx_nic *efx = tx_queue->efx;
335 struct device *dma_dev = &efx->pci_dev->dev;
336 struct efx_tx_buffer *buffer;
337 unsigned int old_insert_count = tx_queue->insert_count;
338 skb_frag_t *fragment;
339 unsigned int len, unmap_len = 0;
340 dma_addr_t dma_addr, unmap_addr = 0;
341 unsigned int dma_len;
342 unsigned short dma_flags;
343 int i = 0;
344
345 if (skb_shinfo(skb)->gso_size)
346 return efx_enqueue_skb_tso(tx_queue, skb);
347
348 /* Get size of the initial fragment */
349 len = skb_headlen(skb);
350
351 /* Pad if necessary */
352 if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
353 EFX_BUG_ON_PARANOID(skb->data_len);
354 len = 32 + 1;
355 if (skb_pad(skb, len - skb->len))
356 return NETDEV_TX_OK;
357 }
358
359 /* Consider using PIO for short packets */
360 #ifdef EFX_USE_PIO
361 if (skb->len <= efx_piobuf_size && !skb->xmit_more &&
362 efx_nic_may_tx_pio(tx_queue)) {
363 buffer = efx_enqueue_skb_pio(tx_queue, skb);
364 dma_flags = EFX_TX_BUF_OPTION;
365 goto finish_packet;
366 }
367 #endif
368
369 /* Map for DMA. Use dma_map_single rather than dma_map_page
370 * since this is more efficient on machines with sparse
371 * memory.
372 */
373 dma_flags = EFX_TX_BUF_MAP_SINGLE;
374 dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE);
375
376 /* Process all fragments */
377 while (1) {
378 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
379 goto dma_err;
380
381 /* Store fields for marking in the per-fragment final
382 * descriptor */
383 unmap_len = len;
384 unmap_addr = dma_addr;
385
386 /* Add to TX queue, splitting across DMA boundaries */
387 do {
388 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
389
390 dma_len = efx_max_tx_len(efx, dma_addr);
391 if (likely(dma_len >= len))
392 dma_len = len;
393
394 /* Fill out per descriptor fields */
395 buffer->len = dma_len;
396 buffer->dma_addr = dma_addr;
397 buffer->flags = EFX_TX_BUF_CONT;
398 len -= dma_len;
399 dma_addr += dma_len;
400 ++tx_queue->insert_count;
401 } while (len);
402
403 /* Transfer ownership of the unmapping to the final buffer */
404 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
405 buffer->unmap_len = unmap_len;
406 buffer->dma_offset = buffer->dma_addr - unmap_addr;
407 unmap_len = 0;
408
409 /* Get address and size of next fragment */
410 if (i >= skb_shinfo(skb)->nr_frags)
411 break;
412 fragment = &skb_shinfo(skb)->frags[i];
413 len = skb_frag_size(fragment);
414 i++;
415 /* Map for DMA */
416 dma_flags = 0;
417 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
418 DMA_TO_DEVICE);
419 }
420
421 /* Transfer ownership of the skb to the final buffer */
422 #ifdef EFX_USE_PIO
423 finish_packet:
424 #endif
425 buffer->skb = skb;
426 buffer->flags = EFX_TX_BUF_SKB | dma_flags;
427
428 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
429
430 efx_tx_maybe_stop_queue(tx_queue);
431
432 /* Pass off to hardware */
433 if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) {
434 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
435
436 /* There could be packets left on the partner queue if those
437 * SKBs had skb->xmit_more set. If we do not push those they
438 * could be left for a long time and cause a netdev watchdog.
439 */
440 if (txq2->xmit_more_available)
441 efx_nic_push_buffers(txq2);
442
443 efx_nic_push_buffers(tx_queue);
444 } else {
445 tx_queue->xmit_more_available = skb->xmit_more;
446 }
447
448 tx_queue->tx_packets++;
449
450 return NETDEV_TX_OK;
451
452 dma_err:
453 netif_err(efx, tx_err, efx->net_dev,
454 " TX queue %d could not map skb with %d bytes %d "
455 "fragments for DMA\n", tx_queue->queue, skb->len,
456 skb_shinfo(skb)->nr_frags + 1);
457
458 /* Mark the packet as transmitted, and free the SKB ourselves */
459 dev_kfree_skb_any(skb);
460
461 /* Work backwards until we hit the original insert pointer value */
462 while (tx_queue->insert_count != old_insert_count) {
463 unsigned int pkts_compl = 0, bytes_compl = 0;
464 --tx_queue->insert_count;
465 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
466 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
467 }
468
469 /* Free the fragment we were mid-way through pushing */
470 if (unmap_len) {
471 if (dma_flags & EFX_TX_BUF_MAP_SINGLE)
472 dma_unmap_single(dma_dev, unmap_addr, unmap_len,
473 DMA_TO_DEVICE);
474 else
475 dma_unmap_page(dma_dev, unmap_addr, unmap_len,
476 DMA_TO_DEVICE);
477 }
478
479 return NETDEV_TX_OK;
480 }
481
482 /* Remove packets from the TX queue
483 *
484 * This removes packets from the TX queue, up to and including the
485 * specified index.
486 */
efx_dequeue_buffers(struct efx_tx_queue * tx_queue,unsigned int index,unsigned int * pkts_compl,unsigned int * bytes_compl)487 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
488 unsigned int index,
489 unsigned int *pkts_compl,
490 unsigned int *bytes_compl)
491 {
492 struct efx_nic *efx = tx_queue->efx;
493 unsigned int stop_index, read_ptr;
494
495 stop_index = (index + 1) & tx_queue->ptr_mask;
496 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
497
498 while (read_ptr != stop_index) {
499 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
500
501 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
502 unlikely(buffer->len == 0)) {
503 netif_err(efx, tx_err, efx->net_dev,
504 "TX queue %d spurious TX completion id %x\n",
505 tx_queue->queue, read_ptr);
506 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
507 return;
508 }
509
510 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
511
512 ++tx_queue->read_count;
513 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
514 }
515 }
516
517 /* Initiate a packet transmission. We use one channel per CPU
518 * (sharing when we have more CPUs than channels). On Falcon, the TX
519 * completion events will be directed back to the CPU that transmitted
520 * the packet, which should be cache-efficient.
521 *
522 * Context: non-blocking.
523 * Note that returning anything other than NETDEV_TX_OK will cause the
524 * OS to free the skb.
525 */
efx_hard_start_xmit(struct sk_buff * skb,struct net_device * net_dev)526 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
527 struct net_device *net_dev)
528 {
529 struct efx_nic *efx = netdev_priv(net_dev);
530 struct efx_tx_queue *tx_queue;
531 unsigned index, type;
532
533 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
534
535 /* PTP "event" packet */
536 if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
537 unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
538 return efx_ptp_tx(efx, skb);
539 }
540
541 index = skb_get_queue_mapping(skb);
542 type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
543 if (index >= efx->n_tx_channels) {
544 index -= efx->n_tx_channels;
545 type |= EFX_TXQ_TYPE_HIGHPRI;
546 }
547 tx_queue = efx_get_tx_queue(efx, index, type);
548
549 return efx_enqueue_skb(tx_queue, skb);
550 }
551
efx_init_tx_queue_core_txq(struct efx_tx_queue * tx_queue)552 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
553 {
554 struct efx_nic *efx = tx_queue->efx;
555
556 /* Must be inverse of queue lookup in efx_hard_start_xmit() */
557 tx_queue->core_txq =
558 netdev_get_tx_queue(efx->net_dev,
559 tx_queue->queue / EFX_TXQ_TYPES +
560 ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
561 efx->n_tx_channels : 0));
562 }
563
efx_setup_tc(struct net_device * net_dev,u32 handle,__be16 proto,struct tc_to_netdev * ntc)564 int efx_setup_tc(struct net_device *net_dev, u32 handle, __be16 proto,
565 struct tc_to_netdev *ntc)
566 {
567 struct efx_nic *efx = netdev_priv(net_dev);
568 struct efx_channel *channel;
569 struct efx_tx_queue *tx_queue;
570 unsigned tc, num_tc;
571 int rc;
572
573 if (ntc->type != TC_SETUP_MQPRIO)
574 return -EINVAL;
575
576 num_tc = ntc->tc;
577
578 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC)
579 return -EINVAL;
580
581 if (num_tc == net_dev->num_tc)
582 return 0;
583
584 for (tc = 0; tc < num_tc; tc++) {
585 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
586 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
587 }
588
589 if (num_tc > net_dev->num_tc) {
590 /* Initialise high-priority queues as necessary */
591 efx_for_each_channel(channel, efx) {
592 efx_for_each_possible_channel_tx_queue(tx_queue,
593 channel) {
594 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
595 continue;
596 if (!tx_queue->buffer) {
597 rc = efx_probe_tx_queue(tx_queue);
598 if (rc)
599 return rc;
600 }
601 if (!tx_queue->initialised)
602 efx_init_tx_queue(tx_queue);
603 efx_init_tx_queue_core_txq(tx_queue);
604 }
605 }
606 } else {
607 /* Reduce number of classes before number of queues */
608 net_dev->num_tc = num_tc;
609 }
610
611 rc = netif_set_real_num_tx_queues(net_dev,
612 max_t(int, num_tc, 1) *
613 efx->n_tx_channels);
614 if (rc)
615 return rc;
616
617 /* Do not destroy high-priority queues when they become
618 * unused. We would have to flush them first, and it is
619 * fairly difficult to flush a subset of TX queues. Leave
620 * it to efx_fini_channels().
621 */
622
623 net_dev->num_tc = num_tc;
624 return 0;
625 }
626
efx_xmit_done(struct efx_tx_queue * tx_queue,unsigned int index)627 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
628 {
629 unsigned fill_level;
630 struct efx_nic *efx = tx_queue->efx;
631 struct efx_tx_queue *txq2;
632 unsigned int pkts_compl = 0, bytes_compl = 0;
633
634 EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
635
636 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
637 tx_queue->pkts_compl += pkts_compl;
638 tx_queue->bytes_compl += bytes_compl;
639
640 if (pkts_compl > 1)
641 ++tx_queue->merge_events;
642
643 /* See if we need to restart the netif queue. This memory
644 * barrier ensures that we write read_count (inside
645 * efx_dequeue_buffers()) before reading the queue status.
646 */
647 smp_mb();
648 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
649 likely(efx->port_enabled) &&
650 likely(netif_device_present(efx->net_dev))) {
651 txq2 = efx_tx_queue_partner(tx_queue);
652 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
653 txq2->insert_count - txq2->read_count);
654 if (fill_level <= efx->txq_wake_thresh)
655 netif_tx_wake_queue(tx_queue->core_txq);
656 }
657
658 /* Check whether the hardware queue is now empty */
659 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
660 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
661 if (tx_queue->read_count == tx_queue->old_write_count) {
662 smp_mb();
663 tx_queue->empty_read_count =
664 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
665 }
666 }
667 }
668
669 /* Size of page-based TSO header buffers. Larger blocks must be
670 * allocated from the heap.
671 */
672 #define TSOH_STD_SIZE 128
673 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE)
674
675 /* At most half the descriptors in the queue at any time will refer to
676 * a TSO header buffer, since they must always be followed by a
677 * payload descriptor referring to an skb.
678 */
efx_tsoh_page_count(struct efx_tx_queue * tx_queue)679 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue)
680 {
681 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE);
682 }
683
efx_probe_tx_queue(struct efx_tx_queue * tx_queue)684 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
685 {
686 struct efx_nic *efx = tx_queue->efx;
687 unsigned int entries;
688 int rc;
689
690 /* Create the smallest power-of-two aligned ring */
691 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
692 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
693 tx_queue->ptr_mask = entries - 1;
694
695 netif_dbg(efx, probe, efx->net_dev,
696 "creating TX queue %d size %#x mask %#x\n",
697 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
698
699 /* Allocate software ring */
700 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
701 GFP_KERNEL);
702 if (!tx_queue->buffer)
703 return -ENOMEM;
704
705 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) {
706 tx_queue->tsoh_page =
707 kcalloc(efx_tsoh_page_count(tx_queue),
708 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL);
709 if (!tx_queue->tsoh_page) {
710 rc = -ENOMEM;
711 goto fail1;
712 }
713 }
714
715 /* Allocate hardware ring */
716 rc = efx_nic_probe_tx(tx_queue);
717 if (rc)
718 goto fail2;
719
720 return 0;
721
722 fail2:
723 kfree(tx_queue->tsoh_page);
724 tx_queue->tsoh_page = NULL;
725 fail1:
726 kfree(tx_queue->buffer);
727 tx_queue->buffer = NULL;
728 return rc;
729 }
730
efx_init_tx_queue(struct efx_tx_queue * tx_queue)731 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
732 {
733 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
734 "initialising TX queue %d\n", tx_queue->queue);
735
736 tx_queue->insert_count = 0;
737 tx_queue->write_count = 0;
738 tx_queue->old_write_count = 0;
739 tx_queue->read_count = 0;
740 tx_queue->old_read_count = 0;
741 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
742 tx_queue->xmit_more_available = false;
743
744 /* Set up TX descriptor ring */
745 efx_nic_init_tx(tx_queue);
746
747 tx_queue->initialised = true;
748 }
749
efx_fini_tx_queue(struct efx_tx_queue * tx_queue)750 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
751 {
752 struct efx_tx_buffer *buffer;
753
754 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
755 "shutting down TX queue %d\n", tx_queue->queue);
756
757 if (!tx_queue->buffer)
758 return;
759
760 /* Free any buffers left in the ring */
761 while (tx_queue->read_count != tx_queue->write_count) {
762 unsigned int pkts_compl = 0, bytes_compl = 0;
763 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
764 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
765
766 ++tx_queue->read_count;
767 }
768 tx_queue->xmit_more_available = false;
769 netdev_tx_reset_queue(tx_queue->core_txq);
770 }
771
efx_remove_tx_queue(struct efx_tx_queue * tx_queue)772 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
773 {
774 int i;
775
776 if (!tx_queue->buffer)
777 return;
778
779 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
780 "destroying TX queue %d\n", tx_queue->queue);
781 efx_nic_remove_tx(tx_queue);
782
783 if (tx_queue->tsoh_page) {
784 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++)
785 efx_nic_free_buffer(tx_queue->efx,
786 &tx_queue->tsoh_page[i]);
787 kfree(tx_queue->tsoh_page);
788 tx_queue->tsoh_page = NULL;
789 }
790
791 kfree(tx_queue->buffer);
792 tx_queue->buffer = NULL;
793 }
794
795
796 /* Efx TCP segmentation acceleration.
797 *
798 * Why? Because by doing it here in the driver we can go significantly
799 * faster than the GSO.
800 *
801 * Requires TX checksum offload support.
802 */
803
804 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
805
806 /**
807 * struct tso_state - TSO state for an SKB
808 * @out_len: Remaining length in current segment
809 * @seqnum: Current sequence number
810 * @ipv4_id: Current IPv4 ID, host endian
811 * @packet_space: Remaining space in current packet
812 * @dma_addr: DMA address of current position
813 * @in_len: Remaining length in current SKB fragment
814 * @unmap_len: Length of SKB fragment
815 * @unmap_addr: DMA address of SKB fragment
816 * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
817 * @protocol: Network protocol (after any VLAN header)
818 * @ip_off: Offset of IP header
819 * @tcp_off: Offset of TCP header
820 * @header_len: Number of bytes of header
821 * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
822 * @header_dma_addr: Header DMA address, when using option descriptors
823 * @header_unmap_len: Header DMA mapped length, or 0 if not using option
824 * descriptors
825 *
826 * The state used during segmentation. It is put into this data structure
827 * just to make it easy to pass into inline functions.
828 */
829 struct tso_state {
830 /* Output position */
831 unsigned out_len;
832 unsigned seqnum;
833 u16 ipv4_id;
834 unsigned packet_space;
835
836 /* Input position */
837 dma_addr_t dma_addr;
838 unsigned in_len;
839 unsigned unmap_len;
840 dma_addr_t unmap_addr;
841 unsigned short dma_flags;
842
843 __be16 protocol;
844 unsigned int ip_off;
845 unsigned int tcp_off;
846 unsigned header_len;
847 unsigned int ip_base_len;
848 dma_addr_t header_dma_addr;
849 unsigned int header_unmap_len;
850 };
851
852
853 /*
854 * Verify that our various assumptions about sk_buffs and the conditions
855 * under which TSO will be attempted hold true. Return the protocol number.
856 */
efx_tso_check_protocol(struct sk_buff * skb)857 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
858 {
859 __be16 protocol = skb->protocol;
860
861 EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
862 protocol);
863 if (protocol == htons(ETH_P_8021Q)) {
864 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
865 protocol = veh->h_vlan_encapsulated_proto;
866 }
867
868 if (protocol == htons(ETH_P_IP)) {
869 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
870 } else {
871 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
872 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
873 }
874 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
875 + (tcp_hdr(skb)->doff << 2u)) >
876 skb_headlen(skb));
877
878 return protocol;
879 }
880
efx_tsoh_get_buffer(struct efx_tx_queue * tx_queue,struct efx_tx_buffer * buffer,unsigned int len)881 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue,
882 struct efx_tx_buffer *buffer, unsigned int len)
883 {
884 u8 *result;
885
886 EFX_BUG_ON_PARANOID(buffer->len);
887 EFX_BUG_ON_PARANOID(buffer->flags);
888 EFX_BUG_ON_PARANOID(buffer->unmap_len);
889
890 if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) {
891 unsigned index =
892 (tx_queue->insert_count & tx_queue->ptr_mask) / 2;
893 struct efx_buffer *page_buf =
894 &tx_queue->tsoh_page[index / TSOH_PER_PAGE];
895 unsigned offset =
896 TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN;
897
898 if (unlikely(!page_buf->addr) &&
899 efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
900 GFP_ATOMIC))
901 return NULL;
902
903 result = (u8 *)page_buf->addr + offset;
904 buffer->dma_addr = page_buf->dma_addr + offset;
905 buffer->flags = EFX_TX_BUF_CONT;
906 } else {
907 tx_queue->tso_long_headers++;
908
909 buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC);
910 if (unlikely(!buffer->heap_buf))
911 return NULL;
912 result = (u8 *)buffer->heap_buf + NET_IP_ALIGN;
913 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP;
914 }
915
916 buffer->len = len;
917
918 return result;
919 }
920
921 /**
922 * efx_tx_queue_insert - push descriptors onto the TX queue
923 * @tx_queue: Efx TX queue
924 * @dma_addr: DMA address of fragment
925 * @len: Length of fragment
926 * @final_buffer: The final buffer inserted into the queue
927 *
928 * Push descriptors onto the TX queue.
929 */
efx_tx_queue_insert(struct efx_tx_queue * tx_queue,dma_addr_t dma_addr,unsigned len,struct efx_tx_buffer ** final_buffer)930 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
931 dma_addr_t dma_addr, unsigned len,
932 struct efx_tx_buffer **final_buffer)
933 {
934 struct efx_tx_buffer *buffer;
935 struct efx_nic *efx = tx_queue->efx;
936 unsigned dma_len;
937
938 EFX_BUG_ON_PARANOID(len <= 0);
939
940 while (1) {
941 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
942 ++tx_queue->insert_count;
943
944 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
945 tx_queue->read_count >=
946 efx->txq_entries);
947
948 buffer->dma_addr = dma_addr;
949
950 dma_len = efx_max_tx_len(efx, dma_addr);
951
952 /* If there is enough space to send then do so */
953 if (dma_len >= len)
954 break;
955
956 buffer->len = dma_len;
957 buffer->flags = EFX_TX_BUF_CONT;
958 dma_addr += dma_len;
959 len -= dma_len;
960 }
961
962 EFX_BUG_ON_PARANOID(!len);
963 buffer->len = len;
964 *final_buffer = buffer;
965 }
966
967
968 /*
969 * Put a TSO header into the TX queue.
970 *
971 * This is special-cased because we know that it is small enough to fit in
972 * a single fragment, and we know it doesn't cross a page boundary. It
973 * also allows us to not worry about end-of-packet etc.
974 */
efx_tso_put_header(struct efx_tx_queue * tx_queue,struct efx_tx_buffer * buffer,u8 * header)975 static int efx_tso_put_header(struct efx_tx_queue *tx_queue,
976 struct efx_tx_buffer *buffer, u8 *header)
977 {
978 if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) {
979 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev,
980 header, buffer->len,
981 DMA_TO_DEVICE);
982 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev,
983 buffer->dma_addr))) {
984 kfree(buffer->heap_buf);
985 buffer->len = 0;
986 buffer->flags = 0;
987 return -ENOMEM;
988 }
989 buffer->unmap_len = buffer->len;
990 buffer->dma_offset = 0;
991 buffer->flags |= EFX_TX_BUF_MAP_SINGLE;
992 }
993
994 ++tx_queue->insert_count;
995 return 0;
996 }
997
998
999 /* Remove buffers put into a tx_queue. None of the buffers must have
1000 * an skb attached.
1001 */
efx_enqueue_unwind(struct efx_tx_queue * tx_queue,unsigned int insert_count)1002 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
1003 unsigned int insert_count)
1004 {
1005 struct efx_tx_buffer *buffer;
1006
1007 /* Work backwards until we hit the original insert pointer value */
1008 while (tx_queue->insert_count != insert_count) {
1009 --tx_queue->insert_count;
1010 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
1011 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL);
1012 }
1013 }
1014
1015
1016 /* Parse the SKB header and initialise state. */
tso_start(struct tso_state * st,struct efx_nic * efx,struct efx_tx_queue * tx_queue,const struct sk_buff * skb)1017 static int tso_start(struct tso_state *st, struct efx_nic *efx,
1018 struct efx_tx_queue *tx_queue,
1019 const struct sk_buff *skb)
1020 {
1021 struct device *dma_dev = &efx->pci_dev->dev;
1022 unsigned int header_len, in_len;
1023 bool use_opt_desc = false;
1024 dma_addr_t dma_addr;
1025
1026 if (tx_queue->tso_version == 1)
1027 use_opt_desc = true;
1028
1029 st->ip_off = skb_network_header(skb) - skb->data;
1030 st->tcp_off = skb_transport_header(skb) - skb->data;
1031 header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u);
1032 in_len = skb_headlen(skb) - header_len;
1033 st->header_len = header_len;
1034 st->in_len = in_len;
1035 if (st->protocol == htons(ETH_P_IP)) {
1036 st->ip_base_len = st->header_len - st->ip_off;
1037 st->ipv4_id = ntohs(ip_hdr(skb)->id);
1038 } else {
1039 st->ip_base_len = st->header_len - st->tcp_off;
1040 st->ipv4_id = 0;
1041 }
1042 st->seqnum = ntohl(tcp_hdr(skb)->seq);
1043
1044 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
1045 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
1046 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
1047
1048 st->out_len = skb->len - header_len;
1049
1050 if (!use_opt_desc) {
1051 st->header_unmap_len = 0;
1052
1053 if (likely(in_len == 0)) {
1054 st->dma_flags = 0;
1055 st->unmap_len = 0;
1056 return 0;
1057 }
1058
1059 dma_addr = dma_map_single(dma_dev, skb->data + header_len,
1060 in_len, DMA_TO_DEVICE);
1061 st->dma_flags = EFX_TX_BUF_MAP_SINGLE;
1062 st->dma_addr = dma_addr;
1063 st->unmap_addr = dma_addr;
1064 st->unmap_len = in_len;
1065 } else {
1066 dma_addr = dma_map_single(dma_dev, skb->data,
1067 skb_headlen(skb), DMA_TO_DEVICE);
1068 st->header_dma_addr = dma_addr;
1069 st->header_unmap_len = skb_headlen(skb);
1070 st->dma_flags = 0;
1071 st->dma_addr = dma_addr + header_len;
1072 st->unmap_len = 0;
1073 }
1074
1075 return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0;
1076 }
1077
tso_get_fragment(struct tso_state * st,struct efx_nic * efx,skb_frag_t * frag)1078 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
1079 skb_frag_t *frag)
1080 {
1081 st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0,
1082 skb_frag_size(frag), DMA_TO_DEVICE);
1083 if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) {
1084 st->dma_flags = 0;
1085 st->unmap_len = skb_frag_size(frag);
1086 st->in_len = skb_frag_size(frag);
1087 st->dma_addr = st->unmap_addr;
1088 return 0;
1089 }
1090 return -ENOMEM;
1091 }
1092
1093
1094 /**
1095 * tso_fill_packet_with_fragment - form descriptors for the current fragment
1096 * @tx_queue: Efx TX queue
1097 * @skb: Socket buffer
1098 * @st: TSO state
1099 *
1100 * Form descriptors for the current fragment, until we reach the end
1101 * of fragment or end-of-packet.
1102 */
tso_fill_packet_with_fragment(struct efx_tx_queue * tx_queue,const struct sk_buff * skb,struct tso_state * st)1103 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
1104 const struct sk_buff *skb,
1105 struct tso_state *st)
1106 {
1107 struct efx_tx_buffer *buffer;
1108 int n;
1109
1110 if (st->in_len == 0)
1111 return;
1112 if (st->packet_space == 0)
1113 return;
1114
1115 EFX_BUG_ON_PARANOID(st->in_len <= 0);
1116 EFX_BUG_ON_PARANOID(st->packet_space <= 0);
1117
1118 n = min(st->in_len, st->packet_space);
1119
1120 st->packet_space -= n;
1121 st->out_len -= n;
1122 st->in_len -= n;
1123
1124 efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
1125
1126 if (st->out_len == 0) {
1127 /* Transfer ownership of the skb */
1128 buffer->skb = skb;
1129 buffer->flags = EFX_TX_BUF_SKB;
1130 } else if (st->packet_space != 0) {
1131 buffer->flags = EFX_TX_BUF_CONT;
1132 }
1133
1134 if (st->in_len == 0) {
1135 /* Transfer ownership of the DMA mapping */
1136 buffer->unmap_len = st->unmap_len;
1137 buffer->dma_offset = buffer->unmap_len - buffer->len;
1138 buffer->flags |= st->dma_flags;
1139 st->unmap_len = 0;
1140 }
1141
1142 st->dma_addr += n;
1143 }
1144
1145
1146 /**
1147 * tso_start_new_packet - generate a new header and prepare for the new packet
1148 * @tx_queue: Efx TX queue
1149 * @skb: Socket buffer
1150 * @st: TSO state
1151 *
1152 * Generate a new header and prepare for the new packet. Return 0 on
1153 * success, or -%ENOMEM if failed to alloc header.
1154 */
tso_start_new_packet(struct efx_tx_queue * tx_queue,const struct sk_buff * skb,struct tso_state * st)1155 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
1156 const struct sk_buff *skb,
1157 struct tso_state *st)
1158 {
1159 struct efx_tx_buffer *buffer =
1160 efx_tx_queue_get_insert_buffer(tx_queue);
1161 bool is_last = st->out_len <= skb_shinfo(skb)->gso_size;
1162 u8 tcp_flags_clear;
1163
1164 if (!is_last) {
1165 st->packet_space = skb_shinfo(skb)->gso_size;
1166 tcp_flags_clear = 0x09; /* mask out FIN and PSH */
1167 } else {
1168 st->packet_space = st->out_len;
1169 tcp_flags_clear = 0x00;
1170 }
1171
1172 if (!st->header_unmap_len) {
1173 /* Allocate and insert a DMA-mapped header buffer. */
1174 struct tcphdr *tsoh_th;
1175 unsigned ip_length;
1176 u8 *header;
1177 int rc;
1178
1179 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len);
1180 if (!header)
1181 return -ENOMEM;
1182
1183 tsoh_th = (struct tcphdr *)(header + st->tcp_off);
1184
1185 /* Copy and update the headers. */
1186 memcpy(header, skb->data, st->header_len);
1187
1188 tsoh_th->seq = htonl(st->seqnum);
1189 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear;
1190
1191 ip_length = st->ip_base_len + st->packet_space;
1192
1193 if (st->protocol == htons(ETH_P_IP)) {
1194 struct iphdr *tsoh_iph =
1195 (struct iphdr *)(header + st->ip_off);
1196
1197 tsoh_iph->tot_len = htons(ip_length);
1198 tsoh_iph->id = htons(st->ipv4_id);
1199 } else {
1200 struct ipv6hdr *tsoh_iph =
1201 (struct ipv6hdr *)(header + st->ip_off);
1202
1203 tsoh_iph->payload_len = htons(ip_length);
1204 }
1205
1206 rc = efx_tso_put_header(tx_queue, buffer, header);
1207 if (unlikely(rc))
1208 return rc;
1209 } else {
1210 /* Send the original headers with a TSO option descriptor
1211 * in front
1212 */
1213 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear;
1214
1215 buffer->flags = EFX_TX_BUF_OPTION;
1216 buffer->len = 0;
1217 buffer->unmap_len = 0;
1218 EFX_POPULATE_QWORD_5(buffer->option,
1219 ESF_DZ_TX_DESC_IS_OPT, 1,
1220 ESF_DZ_TX_OPTION_TYPE,
1221 ESE_DZ_TX_OPTION_DESC_TSO,
1222 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
1223 ESF_DZ_TX_TSO_IP_ID, st->ipv4_id,
1224 ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum);
1225 ++tx_queue->insert_count;
1226
1227 /* We mapped the headers in tso_start(). Unmap them
1228 * when the last segment is completed.
1229 */
1230 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
1231 buffer->dma_addr = st->header_dma_addr;
1232 buffer->len = st->header_len;
1233 if (is_last) {
1234 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE;
1235 buffer->unmap_len = st->header_unmap_len;
1236 buffer->dma_offset = 0;
1237 /* Ensure we only unmap them once in case of a
1238 * later DMA mapping error and rollback
1239 */
1240 st->header_unmap_len = 0;
1241 } else {
1242 buffer->flags = EFX_TX_BUF_CONT;
1243 buffer->unmap_len = 0;
1244 }
1245 ++tx_queue->insert_count;
1246 }
1247
1248 st->seqnum += skb_shinfo(skb)->gso_size;
1249
1250 /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1251 ++st->ipv4_id;
1252
1253 ++tx_queue->tso_packets;
1254
1255 ++tx_queue->tx_packets;
1256
1257 return 0;
1258 }
1259
1260
1261 /**
1262 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1263 * @tx_queue: Efx TX queue
1264 * @skb: Socket buffer
1265 *
1266 * Context: You must hold netif_tx_lock() to call this function.
1267 *
1268 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1269 * @skb was not enqueued. In all cases @skb is consumed. Return
1270 * %NETDEV_TX_OK.
1271 */
efx_enqueue_skb_tso(struct efx_tx_queue * tx_queue,struct sk_buff * skb)1272 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1273 struct sk_buff *skb)
1274 {
1275 struct efx_nic *efx = tx_queue->efx;
1276 unsigned int old_insert_count = tx_queue->insert_count;
1277 int frag_i, rc;
1278 struct tso_state state;
1279
1280 /* Find the packet protocol and sanity-check it */
1281 state.protocol = efx_tso_check_protocol(skb);
1282
1283 rc = tso_start(&state, efx, tx_queue, skb);
1284 if (rc)
1285 goto mem_err;
1286
1287 if (likely(state.in_len == 0)) {
1288 /* Grab the first payload fragment. */
1289 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1290 frag_i = 0;
1291 rc = tso_get_fragment(&state, efx,
1292 skb_shinfo(skb)->frags + frag_i);
1293 if (rc)
1294 goto mem_err;
1295 } else {
1296 /* Payload starts in the header area. */
1297 frag_i = -1;
1298 }
1299
1300 if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1301 goto mem_err;
1302
1303 while (1) {
1304 tso_fill_packet_with_fragment(tx_queue, skb, &state);
1305
1306 /* Move onto the next fragment? */
1307 if (state.in_len == 0) {
1308 if (++frag_i >= skb_shinfo(skb)->nr_frags)
1309 /* End of payload reached. */
1310 break;
1311 rc = tso_get_fragment(&state, efx,
1312 skb_shinfo(skb)->frags + frag_i);
1313 if (rc)
1314 goto mem_err;
1315 }
1316
1317 /* Start at new packet? */
1318 if (state.packet_space == 0 &&
1319 tso_start_new_packet(tx_queue, skb, &state) < 0)
1320 goto mem_err;
1321 }
1322
1323 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
1324
1325 efx_tx_maybe_stop_queue(tx_queue);
1326
1327 /* Pass off to hardware */
1328 if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) {
1329 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
1330
1331 /* There could be packets left on the partner queue if those
1332 * SKBs had skb->xmit_more set. If we do not push those they
1333 * could be left for a long time and cause a netdev watchdog.
1334 */
1335 if (txq2->xmit_more_available)
1336 efx_nic_push_buffers(txq2);
1337
1338 efx_nic_push_buffers(tx_queue);
1339 } else {
1340 tx_queue->xmit_more_available = skb->xmit_more;
1341 }
1342
1343 tx_queue->tso_bursts++;
1344 return NETDEV_TX_OK;
1345
1346 mem_err:
1347 netif_err(efx, tx_err, efx->net_dev,
1348 "Out of memory for TSO headers, or DMA mapping error\n");
1349 dev_kfree_skb_any(skb);
1350
1351 /* Free the DMA mapping we were in the process of writing out */
1352 if (state.unmap_len) {
1353 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE)
1354 dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr,
1355 state.unmap_len, DMA_TO_DEVICE);
1356 else
1357 dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr,
1358 state.unmap_len, DMA_TO_DEVICE);
1359 }
1360
1361 /* Free the header DMA mapping, if using option descriptors */
1362 if (state.header_unmap_len)
1363 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr,
1364 state.header_unmap_len, DMA_TO_DEVICE);
1365
1366 efx_enqueue_unwind(tx_queue, old_insert_count);
1367 return NETDEV_TX_OK;
1368 }
1369