1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36 #include "i40e_devids.h"
37
38 /* I40E_MASK is a macro used on 32 bit registers */
39 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
40
41 #define I40E_MAX_VSI_QP 16
42 #define I40E_MAX_VF_VSI 3
43 #define I40E_MAX_CHAINED_RX_BUFFERS 5
44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46 /* Max default timeout in ms, */
47 #define I40E_MAX_NVM_TIMEOUT 18000
48
49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
50 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52 /* forward declaration */
53 struct i40e_hw;
54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56 /* Data type manipulation macros. */
57
58 #define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* bitfields for Tx queue mapping in QTX_CTL */
63 #define I40E_QTX_CTL_VF_QUEUE 0x0
64 #define I40E_QTX_CTL_VM_QUEUE 0x1
65 #define I40E_QTX_CTL_PF_QUEUE 0x2
66
67 /* debug masks - set these bits in hw->debug_mask to control output */
68 enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81 I40E_DEBUG_IWARP = 0x00F00000,
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91 };
92
93 #define I40E_MDIO_STCODE 0
94 #define I40E_MDIO_OPCODE_ADDRESS 0
95 #define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
96 I40E_GLGEN_MSCA_OPCODE_SHIFT)
97 #define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
98 I40E_GLGEN_MSCA_OPCODE_SHIFT)
99 #define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
100 I40E_GLGEN_MSCA_OPCODE_SHIFT)
101
102 #define I40E_PHY_COM_REG_PAGE 0x1E
103 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
104 #define I40E_PHY_LED_MANUAL_ON 0x100
105 #define I40E_PHY_LED_PROV_REG_1 0xC430
106 #define I40E_PHY_LED_MODE_MASK 0xFFFF
107 #define I40E_PHY_LED_MODE_ORIG 0x80000000
108
109 /* These are structs for managing the hardware information and the operations.
110 * The structures of function pointers are filled out at init time when we
111 * know for sure exactly which hardware we're working with. This gives us the
112 * flexibility of using the same main driver code but adapting to slightly
113 * different hardware needs as new parts are developed. For this architecture,
114 * the Firmware and AdminQ are intended to insulate the driver from most of the
115 * future changes, but these structures will also do part of the job.
116 */
117 enum i40e_mac_type {
118 I40E_MAC_UNKNOWN = 0,
119 I40E_MAC_X710,
120 I40E_MAC_XL710,
121 I40E_MAC_VF,
122 I40E_MAC_X722,
123 I40E_MAC_X722_VF,
124 I40E_MAC_GENERIC,
125 };
126
127 enum i40e_media_type {
128 I40E_MEDIA_TYPE_UNKNOWN = 0,
129 I40E_MEDIA_TYPE_FIBER,
130 I40E_MEDIA_TYPE_BASET,
131 I40E_MEDIA_TYPE_BACKPLANE,
132 I40E_MEDIA_TYPE_CX4,
133 I40E_MEDIA_TYPE_DA,
134 I40E_MEDIA_TYPE_VIRTUAL
135 };
136
137 enum i40e_fc_mode {
138 I40E_FC_NONE = 0,
139 I40E_FC_RX_PAUSE,
140 I40E_FC_TX_PAUSE,
141 I40E_FC_FULL,
142 I40E_FC_PFC,
143 I40E_FC_DEFAULT
144 };
145
146 enum i40e_set_fc_aq_failures {
147 I40E_SET_FC_AQ_FAIL_NONE = 0,
148 I40E_SET_FC_AQ_FAIL_GET = 1,
149 I40E_SET_FC_AQ_FAIL_SET = 2,
150 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
151 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
152 };
153
154 enum i40e_vsi_type {
155 I40E_VSI_MAIN = 0,
156 I40E_VSI_VMDQ1 = 1,
157 I40E_VSI_VMDQ2 = 2,
158 I40E_VSI_CTRL = 3,
159 I40E_VSI_FCOE = 4,
160 I40E_VSI_MIRROR = 5,
161 I40E_VSI_SRIOV = 6,
162 I40E_VSI_FDIR = 7,
163 I40E_VSI_IWARP = 8,
164 I40E_VSI_TYPE_UNKNOWN
165 };
166
167 enum i40e_queue_type {
168 I40E_QUEUE_TYPE_RX = 0,
169 I40E_QUEUE_TYPE_TX,
170 I40E_QUEUE_TYPE_PE_CEQ,
171 I40E_QUEUE_TYPE_UNKNOWN
172 };
173
174 struct i40e_link_status {
175 enum i40e_aq_phy_type phy_type;
176 enum i40e_aq_link_speed link_speed;
177 u8 link_info;
178 u8 an_info;
179 u8 ext_info;
180 u8 loopback;
181 /* is Link Status Event notification to SW enabled */
182 bool lse_enable;
183 u16 max_frame_size;
184 bool crc_enable;
185 u8 pacing;
186 u8 requested_speeds;
187 u8 module_type[3];
188 /* 1st byte: module identifier */
189 #define I40E_MODULE_TYPE_SFP 0x03
190 #define I40E_MODULE_TYPE_QSFP 0x0D
191 /* 2nd byte: ethernet compliance codes for 10/40G */
192 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
193 #define I40E_MODULE_TYPE_40G_LR4 0x02
194 #define I40E_MODULE_TYPE_40G_SR4 0x04
195 #define I40E_MODULE_TYPE_40G_CR4 0x08
196 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
197 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
198 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
199 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
200 /* 3rd byte: ethernet compliance codes for 1G */
201 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
202 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
203 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
204 #define I40E_MODULE_TYPE_1000BASE_T 0x08
205 };
206
207 enum i40e_aq_capabilities_phy_type {
208 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
209 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
210 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
211 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
212 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
213 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
214 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
215 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
216 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
217 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
218 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
219 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
220 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
221 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
222 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
223 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
224 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
225 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
226 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
227 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
228 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
229 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
230 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
231 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
232 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
233 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
234 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
235 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
236 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
237 };
238
239 struct i40e_phy_info {
240 struct i40e_link_status link_info;
241 struct i40e_link_status link_info_old;
242 bool get_link_info;
243 enum i40e_media_type media_type;
244 /* all the phy types the NVM is capable of */
245 enum i40e_aq_capabilities_phy_type phy_types;
246 };
247
248 #define I40E_HW_CAP_MAX_GPIO 30
249 /* Capabilities of a PF or a VF or the whole device */
250 struct i40e_hw_capabilities {
251 u32 switch_mode;
252 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
253 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
254 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
255
256 u32 management_mode;
257 u32 npar_enable;
258 u32 os2bmc;
259 u32 valid_functions;
260 bool sr_iov_1_1;
261 bool vmdq;
262 bool evb_802_1_qbg; /* Edge Virtual Bridging */
263 bool evb_802_1_qbh; /* Bridge Port Extension */
264 bool dcb;
265 bool fcoe;
266 bool iscsi; /* Indicates iSCSI enabled */
267 bool flex10_enable;
268 bool flex10_capable;
269 u32 flex10_mode;
270 #define I40E_FLEX10_MODE_UNKNOWN 0x0
271 #define I40E_FLEX10_MODE_DCC 0x1
272 #define I40E_FLEX10_MODE_DCI 0x2
273
274 u32 flex10_status;
275 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
276 #define I40E_FLEX10_STATUS_VC_MODE 0x2
277
278 bool sec_rev_disabled;
279 bool update_disabled;
280 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
281 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
282
283 bool mgmt_cem;
284 bool ieee_1588;
285 bool iwarp;
286 bool fd;
287 u32 fd_filters_guaranteed;
288 u32 fd_filters_best_effort;
289 bool rss;
290 u32 rss_table_size;
291 u32 rss_table_entry_width;
292 bool led[I40E_HW_CAP_MAX_GPIO];
293 bool sdp[I40E_HW_CAP_MAX_GPIO];
294 u32 nvm_image_type;
295 u32 num_flow_director_filters;
296 u32 num_vfs;
297 u32 vf_base_id;
298 u32 num_vsis;
299 u32 num_rx_qp;
300 u32 num_tx_qp;
301 u32 base_queue;
302 u32 num_msix_vectors;
303 u32 num_msix_vectors_vf;
304 u32 led_pin_num;
305 u32 sdp_pin_num;
306 u32 mdio_port_num;
307 u32 mdio_port_mode;
308 u8 rx_buf_chain_len;
309 u32 enabled_tcmap;
310 u32 maxtc;
311 u64 wr_csr_prot;
312 };
313
314 struct i40e_mac_info {
315 enum i40e_mac_type type;
316 u8 addr[ETH_ALEN];
317 u8 perm_addr[ETH_ALEN];
318 u8 san_addr[ETH_ALEN];
319 u8 port_addr[ETH_ALEN];
320 u16 max_fcoeq;
321 };
322
323 enum i40e_aq_resources_ids {
324 I40E_NVM_RESOURCE_ID = 1
325 };
326
327 enum i40e_aq_resource_access_type {
328 I40E_RESOURCE_READ = 1,
329 I40E_RESOURCE_WRITE
330 };
331
332 struct i40e_nvm_info {
333 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
334 u32 timeout; /* [ms] */
335 u16 sr_size; /* Shadow RAM size in words */
336 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
337 u16 version; /* NVM package version */
338 u32 eetrack; /* NVM data version */
339 u32 oem_ver; /* OEM version info */
340 };
341
342 /* definitions used in NVM update support */
343
344 enum i40e_nvmupd_cmd {
345 I40E_NVMUPD_INVALID,
346 I40E_NVMUPD_READ_CON,
347 I40E_NVMUPD_READ_SNT,
348 I40E_NVMUPD_READ_LCB,
349 I40E_NVMUPD_READ_SA,
350 I40E_NVMUPD_WRITE_ERA,
351 I40E_NVMUPD_WRITE_CON,
352 I40E_NVMUPD_WRITE_SNT,
353 I40E_NVMUPD_WRITE_LCB,
354 I40E_NVMUPD_WRITE_SA,
355 I40E_NVMUPD_CSUM_CON,
356 I40E_NVMUPD_CSUM_SA,
357 I40E_NVMUPD_CSUM_LCB,
358 I40E_NVMUPD_STATUS,
359 I40E_NVMUPD_EXEC_AQ,
360 I40E_NVMUPD_GET_AQ_RESULT,
361 };
362
363 enum i40e_nvmupd_state {
364 I40E_NVMUPD_STATE_INIT,
365 I40E_NVMUPD_STATE_READING,
366 I40E_NVMUPD_STATE_WRITING,
367 I40E_NVMUPD_STATE_INIT_WAIT,
368 I40E_NVMUPD_STATE_WRITE_WAIT,
369 };
370
371 /* nvm_access definition and its masks/shifts need to be accessible to
372 * application, core driver, and shared code. Where is the right file?
373 */
374 #define I40E_NVM_READ 0xB
375 #define I40E_NVM_WRITE 0xC
376
377 #define I40E_NVM_MOD_PNT_MASK 0xFF
378
379 #define I40E_NVM_TRANS_SHIFT 8
380 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
381 #define I40E_NVM_CON 0x0
382 #define I40E_NVM_SNT 0x1
383 #define I40E_NVM_LCB 0x2
384 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
385 #define I40E_NVM_ERA 0x4
386 #define I40E_NVM_CSUM 0x8
387 #define I40E_NVM_EXEC 0xf
388
389 #define I40E_NVM_ADAPT_SHIFT 16
390 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
391
392 #define I40E_NVMUPD_MAX_DATA 4096
393 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
394
395 struct i40e_nvm_access {
396 u32 command;
397 u32 config;
398 u32 offset; /* in bytes */
399 u32 data_size; /* in bytes */
400 u8 data[1];
401 };
402
403 /* PCI bus types */
404 enum i40e_bus_type {
405 i40e_bus_type_unknown = 0,
406 i40e_bus_type_pci,
407 i40e_bus_type_pcix,
408 i40e_bus_type_pci_express,
409 i40e_bus_type_reserved
410 };
411
412 /* PCI bus speeds */
413 enum i40e_bus_speed {
414 i40e_bus_speed_unknown = 0,
415 i40e_bus_speed_33 = 33,
416 i40e_bus_speed_66 = 66,
417 i40e_bus_speed_100 = 100,
418 i40e_bus_speed_120 = 120,
419 i40e_bus_speed_133 = 133,
420 i40e_bus_speed_2500 = 2500,
421 i40e_bus_speed_5000 = 5000,
422 i40e_bus_speed_8000 = 8000,
423 i40e_bus_speed_reserved
424 };
425
426 /* PCI bus widths */
427 enum i40e_bus_width {
428 i40e_bus_width_unknown = 0,
429 i40e_bus_width_pcie_x1 = 1,
430 i40e_bus_width_pcie_x2 = 2,
431 i40e_bus_width_pcie_x4 = 4,
432 i40e_bus_width_pcie_x8 = 8,
433 i40e_bus_width_32 = 32,
434 i40e_bus_width_64 = 64,
435 i40e_bus_width_reserved
436 };
437
438 /* Bus parameters */
439 struct i40e_bus_info {
440 enum i40e_bus_speed speed;
441 enum i40e_bus_width width;
442 enum i40e_bus_type type;
443
444 u16 func;
445 u16 device;
446 u16 lan_id;
447 };
448
449 /* Flow control (FC) parameters */
450 struct i40e_fc_info {
451 enum i40e_fc_mode current_mode; /* FC mode in effect */
452 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
453 };
454
455 #define I40E_MAX_TRAFFIC_CLASS 8
456 #define I40E_MAX_USER_PRIORITY 8
457 #define I40E_DCBX_MAX_APPS 32
458 #define I40E_LLDPDU_SIZE 1500
459 #define I40E_TLV_STATUS_OPER 0x1
460 #define I40E_TLV_STATUS_SYNC 0x2
461 #define I40E_TLV_STATUS_ERR 0x4
462 #define I40E_CEE_OPER_MAX_APPS 3
463 #define I40E_APP_PROTOID_FCOE 0x8906
464 #define I40E_APP_PROTOID_ISCSI 0x0cbc
465 #define I40E_APP_PROTOID_FIP 0x8914
466 #define I40E_APP_SEL_ETHTYPE 0x1
467 #define I40E_APP_SEL_TCPIP 0x2
468 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
469 #define I40E_CEE_APP_SEL_TCPIP 0x1
470
471 /* CEE or IEEE 802.1Qaz ETS Configuration data */
472 struct i40e_dcb_ets_config {
473 u8 willing;
474 u8 cbs;
475 u8 maxtcs;
476 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
477 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
478 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
479 };
480
481 /* CEE or IEEE 802.1Qaz PFC Configuration data */
482 struct i40e_dcb_pfc_config {
483 u8 willing;
484 u8 mbc;
485 u8 pfccap;
486 u8 pfcenable;
487 };
488
489 /* CEE or IEEE 802.1Qaz Application Priority data */
490 struct i40e_dcb_app_priority_table {
491 u8 priority;
492 u8 selector;
493 u16 protocolid;
494 };
495
496 struct i40e_dcbx_config {
497 u8 dcbx_mode;
498 #define I40E_DCBX_MODE_CEE 0x1
499 #define I40E_DCBX_MODE_IEEE 0x2
500 u8 app_mode;
501 #define I40E_DCBX_APPS_NON_WILLING 0x1
502 u32 numapps;
503 u32 tlv_status; /* CEE mode TLV status */
504 struct i40e_dcb_ets_config etscfg;
505 struct i40e_dcb_ets_config etsrec;
506 struct i40e_dcb_pfc_config pfc;
507 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
508 };
509
510 /* Port hardware description */
511 struct i40e_hw {
512 u8 __iomem *hw_addr;
513 void *back;
514
515 /* subsystem structs */
516 struct i40e_phy_info phy;
517 struct i40e_mac_info mac;
518 struct i40e_bus_info bus;
519 struct i40e_nvm_info nvm;
520 struct i40e_fc_info fc;
521
522 /* pci info */
523 u16 device_id;
524 u16 vendor_id;
525 u16 subsystem_device_id;
526 u16 subsystem_vendor_id;
527 u8 revision_id;
528 u8 port;
529 bool adapter_stopped;
530
531 /* capabilities for entire device and PCI func */
532 struct i40e_hw_capabilities dev_caps;
533 struct i40e_hw_capabilities func_caps;
534
535 /* Flow Director shared filter space */
536 u16 fdir_shared_filter_count;
537
538 /* device profile info */
539 u8 pf_id;
540 u16 main_vsi_seid;
541
542 /* for multi-function MACs */
543 u16 partition_id;
544 u16 num_partitions;
545 u16 num_ports;
546
547 /* Closest numa node to the device */
548 u16 numa_node;
549
550 /* Admin Queue info */
551 struct i40e_adminq_info aq;
552
553 /* state of nvm update process */
554 enum i40e_nvmupd_state nvmupd_state;
555 struct i40e_aq_desc nvm_wb_desc;
556 struct i40e_virt_mem nvm_buff;
557 bool nvm_release_on_done;
558 u16 nvm_wait_opcode;
559
560 /* HMC info */
561 struct i40e_hmc_info hmc; /* HMC info struct */
562
563 /* LLDP/DCBX Status */
564 u16 dcbx_status;
565
566 /* DCBX info */
567 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
568 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
569 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
570
571 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
572 u64 flags;
573
574 /* debug mask */
575 u32 debug_mask;
576 char err_str[16];
577 };
578
i40e_is_vf(struct i40e_hw * hw)579 static inline bool i40e_is_vf(struct i40e_hw *hw)
580 {
581 return (hw->mac.type == I40E_MAC_VF ||
582 hw->mac.type == I40E_MAC_X722_VF);
583 }
584
585 struct i40e_driver_version {
586 u8 major_version;
587 u8 minor_version;
588 u8 build_version;
589 u8 subbuild_version;
590 u8 driver_string[32];
591 };
592
593 /* RX Descriptors */
594 union i40e_16byte_rx_desc {
595 struct {
596 __le64 pkt_addr; /* Packet buffer address */
597 __le64 hdr_addr; /* Header buffer address */
598 } read;
599 struct {
600 struct {
601 struct {
602 union {
603 __le16 mirroring_status;
604 __le16 fcoe_ctx_id;
605 } mirr_fcoe;
606 __le16 l2tag1;
607 } lo_dword;
608 union {
609 __le32 rss; /* RSS Hash */
610 __le32 fd_id; /* Flow director filter id */
611 __le32 fcoe_param; /* FCoE DDP Context id */
612 } hi_dword;
613 } qword0;
614 struct {
615 /* ext status/error/pktype/length */
616 __le64 status_error_len;
617 } qword1;
618 } wb; /* writeback */
619 };
620
621 union i40e_32byte_rx_desc {
622 struct {
623 __le64 pkt_addr; /* Packet buffer address */
624 __le64 hdr_addr; /* Header buffer address */
625 /* bit 0 of hdr_buffer_addr is DD bit */
626 __le64 rsvd1;
627 __le64 rsvd2;
628 } read;
629 struct {
630 struct {
631 struct {
632 union {
633 __le16 mirroring_status;
634 __le16 fcoe_ctx_id;
635 } mirr_fcoe;
636 __le16 l2tag1;
637 } lo_dword;
638 union {
639 __le32 rss; /* RSS Hash */
640 __le32 fcoe_param; /* FCoE DDP Context id */
641 /* Flow director filter id in case of
642 * Programming status desc WB
643 */
644 __le32 fd_id;
645 } hi_dword;
646 } qword0;
647 struct {
648 /* status/error/pktype/length */
649 __le64 status_error_len;
650 } qword1;
651 struct {
652 __le16 ext_status; /* extended status */
653 __le16 rsvd;
654 __le16 l2tag2_1;
655 __le16 l2tag2_2;
656 } qword2;
657 struct {
658 union {
659 __le32 flex_bytes_lo;
660 __le32 pe_status;
661 } lo_dword;
662 union {
663 __le32 flex_bytes_hi;
664 __le32 fd_id;
665 } hi_dword;
666 } qword3;
667 } wb; /* writeback */
668 };
669
670 enum i40e_rx_desc_status_bits {
671 /* Note: These are predefined bit offsets */
672 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
673 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
674 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
675 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
676 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
677 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
678 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
679 /* Note: Bit 8 is reserved in X710 and XL710 */
680 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
681 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
682 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
683 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
684 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
685 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
686 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
687 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
688 * UDP header
689 */
690 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
691 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
692 };
693
694 #define I40E_RXD_QW1_STATUS_SHIFT 0
695 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
696 << I40E_RXD_QW1_STATUS_SHIFT)
697
698 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
699 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
700 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
701
702 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
703 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
704 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
705
706 enum i40e_rx_desc_fltstat_values {
707 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
708 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
709 I40E_RX_DESC_FLTSTAT_RSV = 2,
710 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
711 };
712
713 #define I40E_RXD_QW1_ERROR_SHIFT 19
714 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
715
716 enum i40e_rx_desc_error_bits {
717 /* Note: These are predefined bit offsets */
718 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
719 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
720 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
721 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
722 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
723 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
724 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
725 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
726 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
727 };
728
729 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
730 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
731 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
732 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
733 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
734 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
735 };
736
737 #define I40E_RXD_QW1_PTYPE_SHIFT 30
738 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
739
740 /* Packet type non-ip values */
741 enum i40e_rx_l2_ptype {
742 I40E_RX_PTYPE_L2_RESERVED = 0,
743 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
744 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
745 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
746 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
747 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
748 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
749 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
750 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
751 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
752 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
753 I40E_RX_PTYPE_L2_ARP = 11,
754 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
755 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
756 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
757 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
758 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
759 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
760 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
761 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
762 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
763 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
764 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
765 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
766 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
767 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
768 };
769
770 struct i40e_rx_ptype_decoded {
771 u32 ptype:8;
772 u32 known:1;
773 u32 outer_ip:1;
774 u32 outer_ip_ver:1;
775 u32 outer_frag:1;
776 u32 tunnel_type:3;
777 u32 tunnel_end_prot:2;
778 u32 tunnel_end_frag:1;
779 u32 inner_prot:4;
780 u32 payload_layer:3;
781 };
782
783 enum i40e_rx_ptype_outer_ip {
784 I40E_RX_PTYPE_OUTER_L2 = 0,
785 I40E_RX_PTYPE_OUTER_IP = 1
786 };
787
788 enum i40e_rx_ptype_outer_ip_ver {
789 I40E_RX_PTYPE_OUTER_NONE = 0,
790 I40E_RX_PTYPE_OUTER_IPV4 = 0,
791 I40E_RX_PTYPE_OUTER_IPV6 = 1
792 };
793
794 enum i40e_rx_ptype_outer_fragmented {
795 I40E_RX_PTYPE_NOT_FRAG = 0,
796 I40E_RX_PTYPE_FRAG = 1
797 };
798
799 enum i40e_rx_ptype_tunnel_type {
800 I40E_RX_PTYPE_TUNNEL_NONE = 0,
801 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
802 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
803 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
804 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
805 };
806
807 enum i40e_rx_ptype_tunnel_end_prot {
808 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
809 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
810 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
811 };
812
813 enum i40e_rx_ptype_inner_prot {
814 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
815 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
816 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
817 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
818 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
819 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
820 };
821
822 enum i40e_rx_ptype_payload_layer {
823 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
824 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
825 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
826 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
827 };
828
829 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
830 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
831 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
832
833 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
834 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
835 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
836
837 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
838 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
839
840 enum i40e_rx_desc_ext_status_bits {
841 /* Note: These are predefined bit offsets */
842 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
843 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
844 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
845 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
846 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
847 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
848 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
849 };
850
851 enum i40e_rx_desc_pe_status_bits {
852 /* Note: These are predefined bit offsets */
853 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
854 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
855 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
856 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
857 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
858 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
859 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
860 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
861 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
862 };
863
864 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
865 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
866
867 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
868 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
869 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
870
871 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
872 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
873 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
874
875 enum i40e_rx_prog_status_desc_status_bits {
876 /* Note: These are predefined bit offsets */
877 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
878 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
879 };
880
881 enum i40e_rx_prog_status_desc_prog_id_masks {
882 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
883 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
884 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
885 };
886
887 enum i40e_rx_prog_status_desc_error_bits {
888 /* Note: These are predefined bit offsets */
889 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
890 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
891 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
892 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
893 };
894
895 /* TX Descriptor */
896 struct i40e_tx_desc {
897 __le64 buffer_addr; /* Address of descriptor's data buf */
898 __le64 cmd_type_offset_bsz;
899 };
900
901 #define I40E_TXD_QW1_DTYPE_SHIFT 0
902 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
903
904 enum i40e_tx_desc_dtype_value {
905 I40E_TX_DESC_DTYPE_DATA = 0x0,
906 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
907 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
908 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
909 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
910 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
911 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
912 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
913 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
914 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
915 };
916
917 #define I40E_TXD_QW1_CMD_SHIFT 4
918 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
919
920 enum i40e_tx_desc_cmd_bits {
921 I40E_TX_DESC_CMD_EOP = 0x0001,
922 I40E_TX_DESC_CMD_RS = 0x0002,
923 I40E_TX_DESC_CMD_ICRC = 0x0004,
924 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
925 I40E_TX_DESC_CMD_DUMMY = 0x0010,
926 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
927 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
928 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
929 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
930 I40E_TX_DESC_CMD_FCOET = 0x0080,
931 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
932 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
933 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
934 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
935 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
936 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
937 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
938 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
939 };
940
941 #define I40E_TXD_QW1_OFFSET_SHIFT 16
942 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
943 I40E_TXD_QW1_OFFSET_SHIFT)
944
945 enum i40e_tx_desc_length_fields {
946 /* Note: These are predefined bit offsets */
947 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
948 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
949 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
950 };
951
952 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
953 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
954 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
955
956 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
957 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
958
959 /* Context descriptors */
960 struct i40e_tx_context_desc {
961 __le32 tunneling_params;
962 __le16 l2tag2;
963 __le16 rsvd;
964 __le64 type_cmd_tso_mss;
965 };
966
967 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
968 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
969
970 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
971 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
972
973 enum i40e_tx_ctx_desc_cmd_bits {
974 I40E_TX_CTX_DESC_TSO = 0x01,
975 I40E_TX_CTX_DESC_TSYN = 0x02,
976 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
977 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
978 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
979 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
980 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
981 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
982 I40E_TX_CTX_DESC_SWPE = 0x40
983 };
984
985 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
986 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
987 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
988
989 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
990 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
991 I40E_TXD_CTX_QW1_MSS_SHIFT)
992
993 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
994 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
995
996 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
997 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
998 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
999
1000 enum i40e_tx_ctx_desc_eipt_offload {
1001 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1002 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1003 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1004 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1005 };
1006
1007 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1008 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1009 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1010
1011 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1012 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1013
1014 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1015 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1016
1017 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1018 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1019 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1020
1021 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1022
1023 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1024 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1025 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1026
1027 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1028 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1029 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1030
1031 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1032 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1033 struct i40e_filter_program_desc {
1034 __le32 qindex_flex_ptype_vsi;
1035 __le32 rsvd;
1036 __le32 dtype_cmd_cntindex;
1037 __le32 fd_id;
1038 };
1039 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1040 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1041 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1042 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1043 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1044 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1045 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1046 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1047 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1048
1049 /* Packet Classifier Types for filters */
1050 enum i40e_filter_pctype {
1051 /* Note: Values 0-28 are reserved for future use.
1052 * Value 29, 30, 32 are not supported on XL710 and X710.
1053 */
1054 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1055 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1056 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1057 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1058 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1059 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1060 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1061 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1062 /* Note: Values 37-38 are reserved for future use.
1063 * Value 39, 40, 42 are not supported on XL710 and X710.
1064 */
1065 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1066 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1067 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1068 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1069 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1070 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1071 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1072 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1073 /* Note: Value 47 is reserved for future use */
1074 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1075 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1076 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1077 /* Note: Values 51-62 are reserved for future use */
1078 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1079 };
1080
1081 enum i40e_filter_program_desc_dest {
1082 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1083 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1084 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1085 };
1086
1087 enum i40e_filter_program_desc_fd_status {
1088 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1089 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1090 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1091 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1092 };
1093
1094 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1095 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1096 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1097
1098 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1099 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1100 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1101
1102 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1103 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1104
1105 enum i40e_filter_program_desc_pcmd {
1106 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1107 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1108 };
1109
1110 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1111 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1112
1113 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1114 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1115
1116 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1117 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1118 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1119 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1120
1121 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1122 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1123 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1124
1125 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1126 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1127 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1128
1129 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1130 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1131 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1132
1133 enum i40e_filter_type {
1134 I40E_FLOW_DIRECTOR_FLTR = 0,
1135 I40E_PE_QUAD_HASH_FLTR = 1,
1136 I40E_ETHERTYPE_FLTR,
1137 I40E_FCOE_CTX_FLTR,
1138 I40E_MAC_VLAN_FLTR,
1139 I40E_HASH_FLTR
1140 };
1141
1142 struct i40e_vsi_context {
1143 u16 seid;
1144 u16 uplink_seid;
1145 u16 vsi_number;
1146 u16 vsis_allocated;
1147 u16 vsis_unallocated;
1148 u16 flags;
1149 u8 pf_num;
1150 u8 vf_num;
1151 u8 connection_type;
1152 struct i40e_aqc_vsi_properties_data info;
1153 };
1154
1155 struct i40e_veb_context {
1156 u16 seid;
1157 u16 uplink_seid;
1158 u16 veb_number;
1159 u16 vebs_allocated;
1160 u16 vebs_unallocated;
1161 u16 flags;
1162 struct i40e_aqc_get_veb_parameters_completion info;
1163 };
1164
1165 /* Statistics collected by each port, VSI, VEB, and S-channel */
1166 struct i40e_eth_stats {
1167 u64 rx_bytes; /* gorc */
1168 u64 rx_unicast; /* uprc */
1169 u64 rx_multicast; /* mprc */
1170 u64 rx_broadcast; /* bprc */
1171 u64 rx_discards; /* rdpc */
1172 u64 rx_unknown_protocol; /* rupp */
1173 u64 tx_bytes; /* gotc */
1174 u64 tx_unicast; /* uptc */
1175 u64 tx_multicast; /* mptc */
1176 u64 tx_broadcast; /* bptc */
1177 u64 tx_discards; /* tdpc */
1178 u64 tx_errors; /* tepc */
1179 };
1180
1181 /* Statistics collected per VEB per TC */
1182 struct i40e_veb_tc_stats {
1183 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1184 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1185 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1186 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1187 };
1188
1189 #ifdef I40E_FCOE
1190 /* Statistics collected per function for FCoE */
1191 struct i40e_fcoe_stats {
1192 u64 rx_fcoe_packets; /* fcoeprc */
1193 u64 rx_fcoe_dwords; /* focedwrc */
1194 u64 rx_fcoe_dropped; /* fcoerpdc */
1195 u64 tx_fcoe_packets; /* fcoeptc */
1196 u64 tx_fcoe_dwords; /* focedwtc */
1197 u64 fcoe_bad_fccrc; /* fcoecrc */
1198 u64 fcoe_last_error; /* fcoelast */
1199 u64 fcoe_ddp_count; /* fcoeddpc */
1200 };
1201
1202 /* offset to per function FCoE statistics block */
1203 #define I40E_FCOE_VF_STAT_OFFSET 0
1204 #define I40E_FCOE_PF_STAT_OFFSET 128
1205 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1206
1207 #endif
1208 /* Statistics collected by the MAC */
1209 struct i40e_hw_port_stats {
1210 /* eth stats collected by the port */
1211 struct i40e_eth_stats eth;
1212
1213 /* additional port specific stats */
1214 u64 tx_dropped_link_down; /* tdold */
1215 u64 crc_errors; /* crcerrs */
1216 u64 illegal_bytes; /* illerrc */
1217 u64 error_bytes; /* errbc */
1218 u64 mac_local_faults; /* mlfc */
1219 u64 mac_remote_faults; /* mrfc */
1220 u64 rx_length_errors; /* rlec */
1221 u64 link_xon_rx; /* lxonrxc */
1222 u64 link_xoff_rx; /* lxoffrxc */
1223 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1224 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1225 u64 link_xon_tx; /* lxontxc */
1226 u64 link_xoff_tx; /* lxofftxc */
1227 u64 priority_xon_tx[8]; /* pxontxc[8] */
1228 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1229 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1230 u64 rx_size_64; /* prc64 */
1231 u64 rx_size_127; /* prc127 */
1232 u64 rx_size_255; /* prc255 */
1233 u64 rx_size_511; /* prc511 */
1234 u64 rx_size_1023; /* prc1023 */
1235 u64 rx_size_1522; /* prc1522 */
1236 u64 rx_size_big; /* prc9522 */
1237 u64 rx_undersize; /* ruc */
1238 u64 rx_fragments; /* rfc */
1239 u64 rx_oversize; /* roc */
1240 u64 rx_jabber; /* rjc */
1241 u64 tx_size_64; /* ptc64 */
1242 u64 tx_size_127; /* ptc127 */
1243 u64 tx_size_255; /* ptc255 */
1244 u64 tx_size_511; /* ptc511 */
1245 u64 tx_size_1023; /* ptc1023 */
1246 u64 tx_size_1522; /* ptc1522 */
1247 u64 tx_size_big; /* ptc9522 */
1248 u64 mac_short_packet_dropped; /* mspdc */
1249 u64 checksum_error; /* xec */
1250 /* flow director stats */
1251 u64 fd_atr_match;
1252 u64 fd_sb_match;
1253 u64 fd_atr_tunnel_match;
1254 u32 fd_atr_status;
1255 u32 fd_sb_status;
1256 /* EEE LPI */
1257 u32 tx_lpi_status;
1258 u32 rx_lpi_status;
1259 u64 tx_lpi_count; /* etlpic */
1260 u64 rx_lpi_count; /* erlpic */
1261 };
1262
1263 /* Checksum and Shadow RAM pointers */
1264 #define I40E_SR_NVM_CONTROL_WORD 0x00
1265 #define I40E_SR_EMP_MODULE_PTR 0x0F
1266 #define I40E_SR_PBA_FLAGS 0x15
1267 #define I40E_SR_PBA_BLOCK_PTR 0x16
1268 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1269 #define I40E_NVM_OEM_VER_OFF 0x83
1270 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1271 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1272 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1273 #define I40E_SR_NVM_EETRACK_LO 0x2D
1274 #define I40E_SR_NVM_EETRACK_HI 0x2E
1275 #define I40E_SR_VPD_PTR 0x2F
1276 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1277 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1278
1279 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1280 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1281 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1282 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1283 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1284
1285 /* Shadow RAM related */
1286 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1287 #define I40E_SR_WORDS_IN_1KB 512
1288 /* Checksum should be calculated such that after adding all the words,
1289 * including the checksum word itself, the sum should be 0xBABA.
1290 */
1291 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1292
1293 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1294
1295 #ifdef I40E_FCOE
1296 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1297
1298 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1299 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1300 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1301 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1302 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1303 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1304 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1305 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1306 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1307 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1308 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1309 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1310 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1311 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1312 };
1313
1314 /* FCoE DDP Context descriptor */
1315 struct i40e_fcoe_ddp_context_desc {
1316 __le64 rsvd;
1317 __le64 type_cmd_foff_lsize;
1318 };
1319
1320 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1321 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1322 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1323
1324 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1325 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1326 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1327
1328 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1329 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1330 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1331 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1332 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1333 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1334 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1335 };
1336
1337 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1338 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1339 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1340
1341 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1342 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1343 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1344
1345 /* FCoE DDP/DWO Queue Context descriptor */
1346 struct i40e_fcoe_queue_context_desc {
1347 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1348 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1349 };
1350
1351 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1352 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1353 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1354
1355 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1356 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1357 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1358
1359 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1360 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1361 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1362
1363 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1364 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1365 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1366
1367 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1368 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1369 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1370 };
1371
1372 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1373 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1374 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1375
1376 /* FCoE DDP/DWO Filter Context descriptor */
1377 struct i40e_fcoe_filter_context_desc {
1378 __le32 param;
1379 __le16 seqn;
1380
1381 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1382 __le16 rsvd_dmaindx;
1383
1384 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1385 __le64 flags_rsvd_lanq;
1386 };
1387
1388 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1389 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1390 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1391
1392 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1393 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1394 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1395 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1396 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1397 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1398 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1399 };
1400
1401 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1402 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1403 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1404
1405 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1406 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1407 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1408
1409 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1410 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1411 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1412
1413 #endif /* I40E_FCOE */
1414 enum i40e_switch_element_types {
1415 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1416 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1417 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1418 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1419 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1420 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1421 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1422 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1423 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1424 };
1425
1426 /* Supported EtherType filters */
1427 enum i40e_ether_type_index {
1428 I40E_ETHER_TYPE_1588 = 0,
1429 I40E_ETHER_TYPE_FIP = 1,
1430 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1431 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1432 I40E_ETHER_TYPE_LLDP = 4,
1433 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1434 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1435 I40E_ETHER_TYPE_QCN_CNM = 7,
1436 I40E_ETHER_TYPE_8021X = 8,
1437 I40E_ETHER_TYPE_ARP = 9,
1438 I40E_ETHER_TYPE_RSV1 = 10,
1439 I40E_ETHER_TYPE_RSV2 = 11,
1440 };
1441
1442 /* Filter context base size is 1K */
1443 #define I40E_HASH_FILTER_BASE_SIZE 1024
1444 /* Supported Hash filter values */
1445 enum i40e_hash_filter_size {
1446 I40E_HASH_FILTER_SIZE_1K = 0,
1447 I40E_HASH_FILTER_SIZE_2K = 1,
1448 I40E_HASH_FILTER_SIZE_4K = 2,
1449 I40E_HASH_FILTER_SIZE_8K = 3,
1450 I40E_HASH_FILTER_SIZE_16K = 4,
1451 I40E_HASH_FILTER_SIZE_32K = 5,
1452 I40E_HASH_FILTER_SIZE_64K = 6,
1453 I40E_HASH_FILTER_SIZE_128K = 7,
1454 I40E_HASH_FILTER_SIZE_256K = 8,
1455 I40E_HASH_FILTER_SIZE_512K = 9,
1456 I40E_HASH_FILTER_SIZE_1M = 10,
1457 };
1458
1459 /* DMA context base size is 0.5K */
1460 #define I40E_DMA_CNTX_BASE_SIZE 512
1461 /* Supported DMA context values */
1462 enum i40e_dma_cntx_size {
1463 I40E_DMA_CNTX_SIZE_512 = 0,
1464 I40E_DMA_CNTX_SIZE_1K = 1,
1465 I40E_DMA_CNTX_SIZE_2K = 2,
1466 I40E_DMA_CNTX_SIZE_4K = 3,
1467 I40E_DMA_CNTX_SIZE_8K = 4,
1468 I40E_DMA_CNTX_SIZE_16K = 5,
1469 I40E_DMA_CNTX_SIZE_32K = 6,
1470 I40E_DMA_CNTX_SIZE_64K = 7,
1471 I40E_DMA_CNTX_SIZE_128K = 8,
1472 I40E_DMA_CNTX_SIZE_256K = 9,
1473 };
1474
1475 /* Supported Hash look up table (LUT) sizes */
1476 enum i40e_hash_lut_size {
1477 I40E_HASH_LUT_SIZE_128 = 0,
1478 I40E_HASH_LUT_SIZE_512 = 1,
1479 };
1480
1481 /* Structure to hold a per PF filter control settings */
1482 struct i40e_filter_control_settings {
1483 /* number of PE Quad Hash filter buckets */
1484 enum i40e_hash_filter_size pe_filt_num;
1485 /* number of PE Quad Hash contexts */
1486 enum i40e_dma_cntx_size pe_cntx_num;
1487 /* number of FCoE filter buckets */
1488 enum i40e_hash_filter_size fcoe_filt_num;
1489 /* number of FCoE DDP contexts */
1490 enum i40e_dma_cntx_size fcoe_cntx_num;
1491 /* size of the Hash LUT */
1492 enum i40e_hash_lut_size hash_lut_size;
1493 /* enable FDIR filters for PF and its VFs */
1494 bool enable_fdir;
1495 /* enable Ethertype filters for PF and its VFs */
1496 bool enable_ethtype;
1497 /* enable MAC/VLAN filters for PF and its VFs */
1498 bool enable_macvlan;
1499 };
1500
1501 /* Structure to hold device level control filter counts */
1502 struct i40e_control_filter_stats {
1503 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1504 u16 etype_used; /* Used perfect EtherType filters */
1505 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1506 u16 etype_free; /* Un-used perfect EtherType filters */
1507 };
1508
1509 enum i40e_reset_type {
1510 I40E_RESET_POR = 0,
1511 I40E_RESET_CORER = 1,
1512 I40E_RESET_GLOBR = 2,
1513 I40E_RESET_EMPR = 3,
1514 };
1515
1516 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1517 #define I40E_NVM_LLDP_CFG_PTR 0xD
1518 struct i40e_lldp_variables {
1519 u16 length;
1520 u16 adminstatus;
1521 u16 msgfasttx;
1522 u16 msgtxinterval;
1523 u16 txparams;
1524 u16 timers;
1525 u16 crc8;
1526 };
1527
1528 /* Offsets into Alternate Ram */
1529 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1530 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1531 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1532 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1533 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1534 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1535
1536 /* Alternate Ram Bandwidth Masks */
1537 #define I40E_ALT_BW_VALUE_MASK 0xFF
1538 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1539 #define I40E_ALT_BW_VALID_MASK 0x80000000
1540
1541 /* RSS Hash Table Size */
1542 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1543
1544 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1545 #define I40E_L3_SRC_SHIFT 47
1546 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1547 #define I40E_L3_V6_SRC_SHIFT 43
1548 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1549 #define I40E_L3_DST_SHIFT 35
1550 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1551 #define I40E_L3_V6_DST_SHIFT 35
1552 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1553 #define I40E_L4_SRC_SHIFT 34
1554 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1555 #define I40E_L4_DST_SHIFT 33
1556 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1557 #define I40E_VERIFY_TAG_SHIFT 31
1558 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1559
1560 #define I40E_FLEX_50_SHIFT 13
1561 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1562 #define I40E_FLEX_51_SHIFT 12
1563 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1564 #define I40E_FLEX_52_SHIFT 11
1565 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1566 #define I40E_FLEX_53_SHIFT 10
1567 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1568 #define I40E_FLEX_54_SHIFT 9
1569 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1570 #define I40E_FLEX_55_SHIFT 8
1571 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1572 #define I40E_FLEX_56_SHIFT 7
1573 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1574 #define I40E_FLEX_57_SHIFT 6
1575 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1576 #endif /* _I40E_TYPE_H_ */
1577