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/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5.xml.h254 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W()
256 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG()
276 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R()
278 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG()
308 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC()
310 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _… in REG_MDP5_IGC_LUT()
312 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000… in REG_MDP5_IGC_LUT_REG()
349 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL()
363 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_… in REG_MDP5_CTL_LAYER()
365 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP5_CTL_LAYER_REG()
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/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4.xml.h319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP()
321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG()
323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE()
337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE()
339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE()
341 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE()
353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset… in REG_MDP4_OVLP_STAGE()
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP4_OVLP_STAGE_OP()
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +… in REG_MDP4_OVLP_STAGE_FG_ALPHA()
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +… in REG_MDP4_OVLP_STAGE_BG_ALPHA()
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/drivers/gpu/drm/msm/dsi/
Dmmss_cc.xml.h64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK()
66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i… in REG_MMSS_CC_CLK_CC()
83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i… in REG_MMSS_CC_CLK_MD()
97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i… in REG_MMSS_CC_CLK_NS()
Ddsi.xml.h357 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK()
359 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA()
571 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
573 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
575 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
577 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
579 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
581 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
583 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
800 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
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/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h974 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT()
976 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL()
994 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO()
1027 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE()
1029 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3()
1037 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL()
1516 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP()
1518 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN()
1520 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX()
1526 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP()
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Da3xx.xml.h918 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT()
920 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG()
1219 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT()
1221 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL()
1244 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO()
1271 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_BASE()
1279 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } in REG_A3XX_RB_MRT_BLEND_CONTROL()
1859 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK()
1861 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0;… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE()
1863 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET()
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Da2xx.xml.h456 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE()
458 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } in REG_A2XX_VSC_PIPE_CONFIG()
460 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_ADDRESS()
462 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } in REG_A2XX_VSC_PIPE_DATA_LENGTH()
/drivers/gpu/drm/etnaviv/
Dstate.xml.h31 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
157 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
161 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) argument
163 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
165 #define VIVS_FE_UNK00700(i0) (0x00000700 + 0x4*(i0)) argument
169 #define VIVS_FE_UNK00740(i0) (0x00000740 + 0x4*(i0)) argument
173 #define VIVS_FE_UNK00780(i0) (0x00000780 + 0x4*(i0)) argument
271 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) argument
Dstate_hi.xml.h278 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) argument
/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h145 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO()
149 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0()
153 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1()
155 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR()
157 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0()
165 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1()
362 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION()
364 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG()
/drivers/gpu/drm/msm/edp/
Dedp.xml.h276 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } in REG_EDP_PHY_LN()
278 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } in REG_EDP_PHY_LN_PD_CTL()
/drivers/gpu/drm/savage/
Dsavage_drv.h473 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ argument